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SEU hardening of CNFGMEM

CPPM, Université de la méditerranée, CNRS/IN2P3, Marseille, France

2 13/07/2011 FEI-4 Design Collaboration Meeting

Global register

Memory32 x 132 bits

A0A1A2A3 B

uffe

rs

Add

ress

dec

ode

rLi

nes

(x)

WE

Data in Data out

L 0

L 31

Address : 5 bits

Memory for 1 bit data

Can be easily extended to 16 bits data

TRL latch

A4

Loadi =Li and WE

readi =Li and WEbar

To config

Datain

3 13/07/2011 FEI-4 Design Collaboration Meeting

SEU results

During SEU test at CERN, Sasha observed strange properties for events with Global Register

12 of such events classified as "Write glitch" were observed

Variable    Writen(hex) Read(hex) 1)errmask0  FFFF    FFFE 2)prmpvbp_l    0    10 3)lvdsdrvvos    69    6D 4)plsrvgoamp    FF    FB 5)amp2vbpfol    0    80 6)pllibias    58    18 7)bonndac      ED    CD 8)dac8spare1    0    1 9)pllibias    58    59 10)bonndac     ED    CD 11)errmask1    FFFF    DFFF

Only One bit is concerned each time

Rate is 0.016 event/spill

We estimate that only 0.001 to 0.002 event/spill attributed to a “true” SEU in the Triple DICE latch

For the others we assume that are the consequence of internal glitches

4 13/07/2011 FEI-4 Design Collaboration Meeting

Memory Cell

A glitch in the internal NAND or inverter causes a glitch in the load signal

In this case the current value on the data bus is copied in the memory (we have to check this assumption)

5 13/07/2011 FEI-4 Design Collaboration Meeting

Memory cell layout

We still have some space in the memory cell layout

6 13/07/2011 FEI-4 Design Collaboration Meeting

What can we modify ?

Increase the area of the gates used to generate the load

Add a load capacitance at the internal load path

Introduce a delay between load signal of each latch

Depending on the option, this work can necessitate to 1 week of work including all verifications

Risk : minor