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Scaleable Architecture for Real-Time Applications, SARA

Lennart Lindh, Tommy Klevin and Johan Furunäs,

Department of Computer Engineering (IDT), Mälardalens Real-Time Center (MRTC)

Mälardalens University, Sweden

(http://www.mrtc.mdh.se/cal/)

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ApplicationControl System

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“Robot” Problems Today• Performance (>3 Processors today)

• Functionality in the base system (RTOS)– Communication protocol

• Static coupled multi-processor system

• We have added:– Predictability (robotics have some hard deadlines)– Observability and controllability– Small Overhead (simplification)– Fault Tolerance– Component oriented design

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Mixed HW/SW implementation

Hardware

Software

Software SoftwareHardware

HardwareHardware

The research question is: will it be possible to meet the SARA’s objectives if software functions and functions implements in hardware?

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Yesterday, Today and Tomorrow

OperatingSystem

Processors(hardware)

HardwareAccelerator

OperatingSystem

Component based/Application Software

ConventionalSolution

SARA- Scaleable Architecture for

Realtime Applications -

Processor(s)(hardware)

OperatingSystem

(software)

ApplicationSoftware

”New”HardwareFunctions

Architecture

”New” OperatingSystems functions

FASTCHART,FASTHARD and

RTUSolution

ApplicationSoftware

Processor(s)(hardware)

HardwareAccelerator

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Presentation of SARA, Scaleable Architecture for Real-Time Applications

• The SARA Approach

• Logical and physical architecture

• Hardware and Software

• Some benchmark results

• Conclusions

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SARA Approach (main objectives)

• Performance– Scalability

• Predictability (HW/SW)

• Simple

• Observability and controllability

• Component oriented design– “adapter” for different standards

• Fault Tolerance

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Logical architecture

Task 1

Task 2 Task N

IPC-bus

Free slot

MessageQueues

Slots

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Priority inheritanceof the mail priorities

Event A, Low priority

Event B, High priority

Tasks

(Servers)

IPC-SEND // For asynchrony messagesIPC-SENDWAIT// For synchrony messagesIPC-BROADCAST// For broadcast messages IPC-DISTRIBUTE//For multicast messages

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Hard tasks (Servers)

Software part for the IPC bus

Hardware part for the IPC bus

IPC Bus

Hardware Task

Hardware design

Formal methods Deadline controls8-16 bits applications

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Use of old software

Software part for the IPC bus

Hardware part for the IPC bus

IPC Bus

Old RTOS

Old Application

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Physical architecture

CPU

PCI-PCIBridge

Bridge

MemCPUMemMem CPU

BridgeBridge

PCI-PCIBridge

PCI-PCIBridge

System Board

Non System Boards

... Local bus toPCI bridge

RTUPMCBoard

Local PCI-Bus

Transparent Bridge

Non transparentBridge

DoorbellRegister

CompactPCI-Bus

GlobalMemory

PPC750, L1,L2

System on a Chip

Standard systems

Write/Read

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Hardware and Software

XilinxXC4085XL

PLX9080

Local bus

PCIbus

Bus-InterfaceReal Time Unit

PMC-slotInternal bus-protocol

Local bus-PCI busBridge

EPROM for configurationof the RTU and businterface

SROM for some pre-configuration of the Bridge

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Communication between RTU and CPU

RT-clock

IRQ Handler

RTUHW-Interrupt

Scheduler

CPU

RTU-gränssnitt

Avbrottsrutinför taskswitch

Semaphore

CPU

RTU-I/O

Task switchhandler

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IRQ-HandlerHardware and Software

• mult_resp2 (utan Cach)– task1 470.7 s– task2 634.4 s

• mult_resp2 (with Cach)– task1 452.9 s– task2 602.9 s

• mult_resp2 – task1 156,2 s– task2 326,5 s

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Kernel Overhead in Hardware

Round-Robin tid (ms):Antal task: 0.1 0.5 1 5 10 25 50

1 0.0004% 0.0004% 0.0004% 0.0004% 0.0004% 0.0004% 0.0004%5 19.1845% 4.7057% 2.4216% 0.4962% 0.2490% 0.1000% 0.0502%

10 19.1846% 4.7057% 2.4216% 0.4962% 0.2508% 0.1018% 0.0502%25 19.1846% 4.7058% 2.4216% 0.4962% 0.2490% 0.1000% 0.0520%50 19.1859% 4.7059% 2.4216% 0.4962% 0.2490% 0.1000% 0.0520%

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Conclusion

• The IPC is easy to use

• When a software function implements in hardware the response time and time gap between best and worst case execution time decrease, ex in RTU clock tick is 1us, in a software system 1ms. (RTU need 5 MHz)

• Demonstration of the SARA on SNART.

• Are you interesting in corporation?