1. Relationship Between Voltage and S 21 in a Two-port Network

Lecture #7 Richard Li, 2009 1

1. Relationship Between Voltage and S21 in a Two-port Network

2. Characterizing a Chip Capacitor by Means of S21 Testing

3. “Zero” Capacitor o What is “Zero” capacitor? ” o Selection of the “Zero” Capacitor o Bandwidth of the “Zero” Capacitor o Combined Effect of Multiple “Zero” Capacitors o “Zero” Capacitor in RFIC Design

4. Characterizing a Chip Inductor by Means of S21 Testing

5. “Infinite” Inductor o Chip Inductor is a Good Assistant in Grounding

6. Characterizing a Chip Resistor by Means of S11 Testing o Special Characters of Chip Resistor

Lecture 27 : Characterization of Chip Parts Richard Chi-Hsi Li 李缉熙

Cellular phone: 13917441363 (PRC)Email : [email protected]


1

2

02

0121 2

E

v

R

RS

E2 = 0,

Two-portNetwork

Port 2Port 1

E2E1

v1 v2

R02R01

Figure 1 Source and load parameters in a two-port network

500201 RR Ω,

1

221 2

E

vS

• Relationship Between Voltage and of S21 in a Two-port Network

[Ralph S. Carson, “High-Frequency Amplifiers,” (Book) , John Wiley & Sons, Inc., 1975.]


2. Characterizing a Chip Capacitor by Means of S21 Testing

Figure 2 S21 testing for a chip capacitor.

Chip C

DTU

GND

50 Ω 50 Ω

Network Analyzer(S21 testing)

Port 1 Port 2


2

2

222

1

2

150

1150

150

CLR

CLR

CLR

CLRR

E

v

SS

SSSSSSS

CLS

SRF

1

S

S

R

R

E

v

501

2

S

SSRF R

R

E

vS

502log202log20,

1

221

1102

50

20,21

SRFSSR

CL

SRF

S 2

1

specifiedCC

LS

RS

C

Port 2Port 1

E1

v1 v250 ohm 50 ohm

Figure 3 Replacement of “Two port Network” in Figure 2 by chip capacitor’s equivalent model

.


Figure 4 S21 Frequency response of chip capacitor C= Cspecified =15 pF with test setup as shown in Figure 14A.1.

f , GHz

0

-20

-40

-60

20

40

S21, dB

1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2

-10

-30

-50

30

10

15 pF

Cspecified = 15 pFS21,SRF = -45.1dBSRF = 1.394 GHz


Cspecified, pF

fSRF = 5400 / C 1/2

(MHz) (pF)

1. 8 pF < Cspecified < 18000 pFSize : 30x60 & 50x80 mils2

10000

10

100

1000

1000010 100 1000 10000000

10000001000001

InductiveApplication Region

CapacitiveApplication Region

Figure 5 Plot of the self-resonant frequency fSRF vs specified value of chip capacitor Cspecified, extrated from testing of MuRata chip capacitors.

fSRF , MHz


SRFC Value of chip capacitor, (MHz) (pF)

40 18,000 150 1,296 450 144 500 117

800 46 900 36

1,000 29 1,500 13 2,400 5.1 5,400 1.0

Table 1 Some important SRFC (Self Resonant Frequency) values of chip capacitors


LS = 0.86 nH

1. 8 pF < Cspecified < 18000 pFSize : 30x60 & 50x80 mils2

1

0.01

0.1

1000010 100 1000 1000000010000001000001

Cspecified, pF

LS , nH

Figure 6 Plot of in-series parasitic inductance LS vs specified capacitance Cspecified, extracted from testing of MuRata chip capacitors.


RS = 0.08 to 0.52 Ω

1. 8 pF < Cspecified < 18000 pFSize : 30x60 & 50x80 mils

1

0.01

0.1

1000010 100 1000 1000000010000001000001

Cspecified, pF

RS , Ω

Figure 7 Plot of in-series resistance RS vs specified capacitance Cspecified, extrated from testing of MuRata chip capacitors.


3. “Zero” Capacitor

o What is a “Zero” Capacitor?

Vcc

Q1

R1

L1

Figure 8 “Zero” capacitor functions as a bypass or a blocking capacitor

In

Out

Bias

DC Blocking Capacitor

DC Blocking Capacitor

AC BypassCapacitor

AC BypassCapacitor

GND

GND

GND

“Zero” Capacitor = AC Bypass capacitor = DC Blocking capacitor


(b) Equivalent of an actual capacitor

Figure 9 An actual chip capacitor and its equivalent

(a) An actual chip capacitor

C C

L

r

jCZ c

1

Theory

Chip “zero” capacitor

LCSRFc 2

1

o Selection of the “Zero” Capacitor

specicied

cC

SRF5400

For MuRata capacitorsCspecified = 0.5 pF to 18000

pF. for both sizes W x L = 50 x 80 mils and 30

x 40 mils

where SRFc = Self resonant frequency in MHz, Cspecified= Specified capacitance by the manufacturer in pF.


Figure 10 RF or AC grounded by a “zero” capacitor on a PCB (Printed Circuit Board).Top metallic area; P : Point to be grounded;Bottom metallic area; G : Reference ground point..Conductive via from top to bottom;“Zero” capacitor

G

PC B

P

“Zero” capacitor

Vdd

* “Zero” capacitor on PCB in narrow band case


Figure 11 RF or AC grounded by more than one “zero” capacitor on a PCB (Printed Circuit Board).

Top metallic area; P : Point to be grounded;Bottom metallic area; G : Well-grounded point.Conductive via from top to bottom;“Zero” capacitor

G

PC B

P

“Zero” capacitors

Vdd

* “Zero” capacitor on PCB in wide band or multi-band case


* Number of “zero” Capacitors in a RF system are much more than in a RF block

Top metallic area; P : Point to be grounded;Bottom metallic area; G : Reference ground point..Conductive via from top to bottom;“Zero” capacitor

Figure 12 Number difference of “zero” capacitor in a RF system and in a RF block

Vdd1

RF system

(b) More “Zero” capacitors for a RF block

Vdd2

Vdd3

Vdd

(a) 1 or 2 “Zero” capacitors for a RF block

Vdd

RF blockRF block

or


* “Zero” Capacitors in RFIC

Figure 13 “Zero” capacitor works in the RF/AC grounding for a IC die

Bond wirePadTop metallic areaBottom metallic areaIC dieRunner in IC die

Runner on IC dieSoldering pad on PCBConductive via from top to bottom Chip “zero” CapacitorGround ring of RF block

PCB (Printed Circuit Board)


RF Block

IC die


o Bandwidth of the “Zero” Capacitor

Figure 14 S21 testing for a chip capacitor.

Chip C

DUT

GND

50 Ω 50 Ω


Port 1 Port 2


f , GHz

0

-20

-40

-60

20

40

S21, dB

Cspecified = 15 pFS21,SRF = -45.1dBSRF = 1.394 GHz

Figure 15 S21 frequency response of a chip capacitor tested with setup as shown in Figure 14.11

1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2

-10

-30

-50

30

10

BW =1.475 - 1.310 = 0.165 GHz

BW =1.600 - 1.230 = 0.370 GHz

BW =1.422 - 1.352 = 0.070 GHz

15 pF


f , GHz

0

-20

-40

-60

20

40

S21, dB

Figure 16 Frequency bandwidth 250 MHz =1.560 -1.310 GHz is covered by a “zero” capacitor combined by two capacitors C= 15 pF and C= 13 pF connected together in parallel.

1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2

-10

-30

-50

30

10

Cspecified = 13 pFS21,SRF = -42.6 dBSRF = 1.456 GHz

BW =1.560 - 1.310 = 0.250 GHz

Cspecified = 15 pFS21,SRF = -45.1 dBSRF = 1.394 GHz

15 pF 13 pF


* Combined Effect of Multiple “Zero” Capacitors

An interesting question is then raised:

Does a resultant SRF due to the combination of all the individual “zero” capacitors exist, superseding the SRFs of the individual “zero” capacitors, since these “zero” capacitors are connected between the positive terminal of DC power supply or DC bias and a real grounded point, GND, in parallel?

According to empirical experimentation, a resultant SRF combined by individual “zero” capacitors may appear while the behavior of the individual“zero” capacitors is unchanged.

The resultant SRF is usually located outside of the expected bandwidth.

Figure 17 Modified equivalent model of “zero” chip capacitor by adding of soldering pads and runners for RF modules

Runner on IC die “Zero” chip capacitorSoldering pad on PCB


4. Characterizing a Chip Inductor by Means of S21 Testing

Figure 18 S21 testing for a chip inductor.

50 Ω 50 Ω


Port 1 Port 2

Chip L

DTU

GND


50 Ω

Two-port network

Port 2Port 1

E1

v1 v250Ω

LRP

CP

Figure 19 Replacement of “Two port Network” in Figure 14A.3 by chip inductor’s equivalent model

2

12

2

2

1

2

111100

50

PPPp LC

CRR

E

v

2

12

2

2

1

221

111100

100log202log20

PPPp LC

CRR

E

vS

2

1

1

P

SRF

LC

PSRF R

S

100

100log20,21

110100 20

,21 SRFS

PR

LC

SRF

P 2

1

specifiedLL


f , GHz

0

-20

-40

-60

20

40

S21, dB

Figure 20 S21 Frequency response of chip inductor L= 62 nH with test setup as shown in Figure 14A.2.

1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2

-10

-30

-50

30

10

L = Lspecified S21,SRF = - 46.7 dBSRF = 1.57 GHz

62nH


SRFL Value of chip inductor, (MHz) (nH)

210 1,800 300884 450393 500318 800124 900981,00079.61,50035.42,40013.85,4002.7

Table 2 Some SRFL (Self Resonant Frequency) values of chip inductors


fSRF = 8920 / L 1/2

(MHz) (nH)

22 nH < Lspecified,< 1800 nH

10000

100

1000

1000100 1000010

Lspecified,, nH

fSRF , MHz

CapacitiveApplication Region

InductiveApplication Region

Figure 21 Plot of the self-resonant frequency fSRF vs specified value of chip inductor Lspecified, extracted from testing of MuRata chip inductors.


Lspecified, nH

CP = 0.2 pF

22 nH < Lspecified < 1800 nH

10

0.1

1

1000100 1000010

CP , pF

Figure 22 Plot of in-parallel capacitance CP vs specified inductance Lspecified, extracted from testing of MuRata chip inductors.


1000000RP = 2580 x L 1/2

(Ω) (nH)

22 nH < Lspecified < 1800 nH

1000

10000

100000

1000100 1000010Lspecified, nH

RP , Ω

Figure 23 Plot of in-parallel resistance RP vs specified inductance Lspecified, extrated from testing of MuRata chip inductors.


o Chip Inductor is a Good Assistant

specicied

LL

SRF8920

where SRFL = Self resonant frequency in MHz,Lspecified= Specified capacitance by the

manufacturer in nH.

For MuRata inductorsLspecified = 22 nH to

1800 nH.

Theory

Chip “Infinite” inductor

LCSRFL 2

1

jLZL

r

C L

Figure 24 An actual inductor and its equivalent

(a) An actual inductor (b) Equivalent of an actual inductor

C


Figure 25 RF or AC grounded by a “zero” capacitor with assistance of an “infinite” inductor on a PCB.

Top metallic area; P : Point to be grounded;Bottom metallic area; GND : Reference grounded point.Conductive via from top to bottom;“Zero” capacitor“Infinite” inductor

PC B

Vdd or Vcc

GNDP

“Zero” capacitor

“Infinite” inductor

Po


Figure 26 “Zero” capacitor is connected between the P+ guard ring in IC die and the ground frame on PCB

PCB (Printed Circuit Board)


RF Block

IC die

Bond wirePadTop metallic areaBottom metallic areaIC dieRunner in IC die

Runner on IC dieSoldering pad on PCBConductive via from top to bottom Chip “zero” CapacitorGround ring of RF block

o “Zero” Capacitor in RFIC Design


Figure 27 Difference of “Zero” capacitors RF/AC grounding for a IC die and for a RF module or a RF block module

Bond wirePadIC dieRunner in IC die

Runner on IC dieSoldering pad on PCBChip “zero” Capacitor

(a) “Zero” capacitor grounding for a RFIC die (b) “Zero” capacitor grounding for a RF module or for a RF block built by discrete parts

• A runner on PCB from the point to be grounded to a soldering pad,• Soldering pad on PCB,• A chip “zero” capacitor,• Soldering pad on PCB,• A runner on PCB between the chip “zero” capacitor and the ground frame on PCB.

• A shout runner in IC die from the ground ring die to a tiny pad, • A tiny bond pad in IC die, • A bond wire in the air between the tiny pad in IC die and the bonding pad on PCB,• A bonding pad on PCB• A runner on PCB from the bonding pad on PCB to the soldering pad on PCB,• Soldering pad on PCB,• A chip “zero” capacitor,• Soldering pad on PCB,• A runner on PCB between the chip “zero” capacitor and the ground frame on PCB.


5. Characterizing a Chip Resistor by Means of S11 Testing

Figure 28 S11 testing for a chip resistor.

50 Ω


Port 1 Port 2

Chip RDTU


Port 1

E1

50 Ω

One-port Network

RP CP LP

(or)

ZS

Figure 29 Single-port S-parameter measurement of a chip capacitor


1000000

10

100000

10 100 1000 100000

Rspecified, Ω

RP , Ω

1000

100

1

10000

RP = Rspecified , if f < 100 MHz

f < 100 MHzf = 500 MHz f = 1000 MHz

10000

f = 1500 MHzf = 2000 MHz

Figure 30 Plot of in parallel resistance RP vs. specified resistance Rspecified, extrated from testing of MuRata chip resistors.


10

1000010 100 1000 100000Rspecified, Ω

CP , pF

1.0

0.1

f < 100 MHzf = 500 MHz f = 1000 MHz

f = 1500 MHzf = 2000 MHz

CP = 0.65 to 0.90 pF , if 150 Ω < Rspecified <51000 Ω

Figure 31 Plot of in-parallel capacitance CP vs specified resistance Rspecified, extrated from testing of MuRata chip resistors.

1. Relationship Between Voltage and S 21 in a Two-port Network

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