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Process-Variation Tolerant Design Techniques for Multiphase Clock Generation

Manohar Nagaraju+, Wei Wu*, Cameron Charles#

+University of Washington, Seattle, WA, USA#University of Utah, Salt Lake City, UT, USA

*Northwestern Polytechnic University, Xi’an, China

Outline

Background on clock and data recovery (CDR) and motivation

Circuit level and system level optimization Measurement results Conclusion

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Motivation

Increasing I/O bandwidth complicates CDR circuit design, particularly the VCO

Solution: over-sample the incoming data

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Motivation

Use a Delay-Locked Loop (DLL) to recover data at N*clock frequency

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Ref_Clk

Φ1

Φ2

Φ3

Φ4

Rx_Data

Motivation

Problems in multiphase clock generationMismatch in delay among delay blocksOverall frequency controlled by loop but

phase relationships uncontrolled

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Input Data

Ideal Sampling Non-Ideal Sampling

Delay Distribution of inverter pair Vt mismatch of 100mV

Motivation

Sources of mismatchMismatch in VtMismatch in W/L

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Motivation

Sources of mismatchMismatch in VtMismatch in W/LMismatch in load

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c

Clk_ref

VCDL

ccc c

Clk0Clk1Clk2Clk3

To PFD

Delay of stage 1: 686.3psDelay of stage 2: 695.5psDelay of stage 3: 695.5psDelay of stage 4: 654.5ps

Solution

Propose circuit-level design methodology to reduce mismatch

Introduce extra control on the individual phases – digital calibration

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Circuit-level optimization

A transistor sizing scheme to reduce mismatch

Expression for variable of interest (here delay) as a function of process parameter (here Vt)

Differentiate w.r.t process parameter Design circuit to ensure the resulting

expression is small

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Circuit-level optimization

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Ex: A CMOS inverter Fall time:

Following procedure, length should be increased

201)(

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tnddn

tnout

VV

VCt

Circuit-level optimization

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Vcontrol

Vin

M1

M2

M3

M4

M5

M6

M7

M8

VoutVx

Schematic of a single delay cell

Increase W/L

Increase W/LReduce W/L

Increase W/L

Circuit optimization results

Monte-Carlo simulation

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a) Optimized co-efficient of

variation = 3.05%

b) Un-optimized co-efficient of

variation = 6.73%

Limitation

VCDL gain becomes non-linear

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Limitation

VCDL gain becomes non-linear Lock range of DLL reduces

0.5 Tref clk < T VCDL, min < Tref clk

Tref clk < TVCDL max < 1.5 * T ref clk

Process complicated with the number of variables increasing

Delay still varies from 205-250 ps (5.57˚) – quite large for multiphase clocking scheme

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Phase control by digital calibration

Based on equation fring_osc = (1/2NTd)

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Calibration of the VCDL

Difference between ring oscillator frequencies indicates difference in delays

To change delay of delay blockChange Vt - requires DAC

Change current which is the parameter of interest – by changing widths dynamically

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Calibration of the VCDL

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Modify delay cell Resolution = 9.8ps Delay variation

-140ps

Vin

M2

M3

I2I4I

I2I4I

VX

I = smallest current

8I16I32I

32I 8I16I

Die photo

AMI 0.6um CMOS process - 2300um X 900um

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Measurement results

Lock range – 185-240MHz Power: 15.4mA + 46.4mA (calibration) Time required for calibration 8.29us.

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Measurement results

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Delay Block

Ideal Delay (ns)

Delay value (ns)

Error (ns)

Delay Phases

Ideal Sampling time (ns)

Actual Sampling time (ns)

Error in Sampling time (ns)

1 1.1 1.12202 -0.02202 Φ1 –Φ2 1.1 1.12202 -0.02202

2 1.1 1.11808 -0.01808 Φ1 –Φ3 2.2 2.2401 -0.0401

3 1.1 1.04155 0.05845 Φ1 –Φ4 3.3 3.28165 0.01835

4 1.1 1.08841 0.01159 - - - -

Delay Block

Ideal Delay (ns)

Delay value (ns)

Error (ns)

Delay Phases

Ideal Sampling time (ns)

Actual Sampling time (ns)

Error in Sampling time (ns)

1 1.1 1.11344 -0.01344 Φ1 –Φ2 1.1 1.11344 -0.01344

2 1.1 1.09266 0.00734 Φ1 –Φ3 2.2 2.2061 -0.0061

3 1.1 1.08891 0.01109 Φ1 –Φ4 3.3 3.29501 0.00499

4 1.1 1.08334 0.01666 - - - -

Delay values of the four delay blocks before and after calibration at 227MHz

3.28˚

1.09˚

0.4˚

Performance summary

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This work JSSC May ‘06

TCAS IIJuly ‘08

Process 0.6um 0.18um 0.13um

Frequency range 185-240MHz 0.7-2GHz N/A

Calibration method Digital Digital Analog

Phase error before calibration

3.28° @ 227MHz

7.34° @2GHz

N/A

Phase error after calibration

1.09°@227MHz 1.26°@1GHz 0.18°@200MHz

Area of calibration circuit

1.17mm2 0.52mm2 N/A

Power 77mW 81mW 16.4mW

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Proposed a new methodology to design process-invariant circuits

Proposed a digital calibration scheme to reduce mismatches in delay

Maximum phase offset among delay blocks

was reduced to 1.09°

Summary

Thank

You

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