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PC-base Software Routers: High Performance and Application Service Support

Author:

Raffaele Bolla, Roberto Bruschi

Publisher:

PRESTO’08

Presenter:

Hsin-Mao Chen

Date:2010/02/24

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Outline

IntroductionArchitectural BottlenecksMulti-CPU/Core EnhancementsPerformance Evaluation

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Introduction

Linux

Network boards

Packet Reception or Transmission

HW Interrupt

(IRQ)

Kernel

Software IRQs

(SoftIRQs)

Packet ProcessingRAM

TxRing and Rx

Ring

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Introduction

A SoftIRQ executes two main tasks.

1.The de-allocation of already-transmitted packets placed in the TxRing.

2.All the real packet forwarding operations. The task handles the received packets in the RxRing.

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Architectural Bottlenecks

SR architecture based on a single CPU/core.

1.The SR computational capacity.

2.The bandwidth/latency of I/O busses.

SR architecture based on multiprocessor.

Typical performance issues may sap parallelization gain.

1.Data accessing serialization.

2.CPU/core cache coherence.

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Architectural Bottlenecks

Data accessing serialization

The SoftIRQ accesses to each TxRing are serialized by a code locking procedure (LLTX lock). This lock guarantees that each TxRing can be read or modified by only one SoftIRQ at a time.

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Architectural Bottlenecks

CPU/core cache management

Whenever a CPU/core loads a TxRing to its local cache, all of the other processors also cashing it must invalidate their cache copies.

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Mulit-CPU/core Enhancements

HW evolution

Intel® Advanced Smart Cache: It consists of a mechanism that allows level 2 cache-sharing among all the cores in the same processor.

Intel PRO 1000 adapters: It supports multiple Tx- and Rx Ring and multiple HW IRQs per network interface.

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Mulit-CPU/core Enhancements

SW architecture

1.To entirely bind all operations carried out in forwarding a packet to a single CPU.

2.To reduce LLTX lock contention as much as possible.

3.To equally distribute the computational load among all the processors/cores in the system.

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Mulit-CPU/core Enhancements

CPU/core binding to TxRing: Bind each CPU/core to a different TxRing on each output device.

CPU/core binging to RxRing: Bind each RxRings to a different CPU/core.Xeon core: 1 Mpkt/s

Gigabit Ethernet interface: 1.488 Mpkt/s with 64B sized frames

Fast Ethernet interface: 148.8 pkt/s with 64B sized frames

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Mulit-CPU/core Enhancements

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Performance Evaluation

Standard SR architecture

Agilent N2X router

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Performance Evaluation

Standard SR architecture

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Performance Evaluation

Enhanced SR architecture

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Performance Evaluation

Enhanced SR architecture

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Performance Evaluation

Enhanced SR architecture

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Performance Evaluation

Multi-layer service support

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Performance Evaluation

Multi-layer service support