1 Mike Wolfe Applications Engineer Interface Division Taking the Guess Work out of High-speed Data...

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Mike WolfeApplications EngineerInterface Division

Taking the Guess Work out of High-speed Data Communication Links

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© 2008 National Semiconductor Corporation

FPGA Friendly Interface

Easylink Concept : Intelligent Partitioning

FPGA based Digital Heavy Lifting

Off-the-shelf IP Blocks

Optimal Solution

Customer Core Logic

Easylink SerDes

Longer Reach Higher Data-rate Lower System BOM FPGA I/O Friendly

Analog Rich Signal Conditioning

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Easylink Family Simplifies Your System Solution

• Total App Throughput : 125 Mbps to 3.125 Gbps

• Plug-n-Go! – Integrated Signal Conditioners– Jitter cleaning functions on both transmit and receiver– LVDS parallel interface for reduced EMI and increased noise tolerance– Built-in DC-balance encoder/decoder, scrambler/descrambler– Redundant serial outputs on transmit (1:2), inputs on receive (2:1)– FPGA Friendly : I/Os, Timing requirements

• Lowers System BOM and Components– Drives long inexpensive cables. E.g. CAT-5/6– No reference clock needed– No external signal conditioners required. E.g. Cable driver, equalizer– Integrated termination resistors and decoupling capacitors

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Easylink Value Proposition More than a SerDes function…

Easylink Provides End-to-End Solution

Send Data and a clock, WE DO THE REST!

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DS32 Family – Covering Multiple Applications

Easylink Family

32EL0421/0124

32ELX0421/0124

Clock

Rate (MHz, DDR) 125 to 312.5 125 to 312.5

Max

Throughput 3.125 Gbps 3.125 Gbps

Function Ser/Des Ser/Des

Serial Interface

Retimed Output No Yes

Redundant I/Os No YesParallel

Interface

Width 5 5

Signaling LVDS LVDS

Sampling: NOW! NOW!

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• Up to 3.125 Gbps data payload• Drives 15+ m low cost CATx cable, 40” FR-4• No external coding or commas required• Retimed Serial Output – No Accumulated Jitter• Redundant Serial I/O• Built-in Sig Conditioners - De-Emp, DC-Balance, EQ

• Low power/EMI LVDS “parallel” interface• Space-saving LLP-48 package• Full industrial -40 to +85°C temp range• Supports optical applications• Powerwise features

DS32ELX0421/0124 1.25 – 3.125 Gbps Ser/Des with Retimer and Redundant I/Os

Redundant Serial Output

Retimed Serial Output

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Exploring Typical Applications

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Signal Path Configurations

SER DES DES DESDaisy Chained Links :

Link Aggregation :

SER DES

SER DESData valid

signal

Data valid signal

Data valid signal

SER DESPoint-to-Point Link: Cable, Fiber, Backplane – 3.125

Gbps

SER DES DESMedia Conversion : Reach Extension :

E.g. FR-4 E.g. Fiber

SER DESRedundant Links :

E.g. CAT-5e (100-ohm diff)

E.g. Coax (75-ohm)

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Medical ImagingExample System Diagram

EasyLink

EasyLink

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Application System Requirements

Requirements Easylink Feature

Comments

4.32 Gbps data payload

DV Signaling DV enables link aggregation

100ft link distance Integrated Sig Con blocks, DC Balance encoder

Max gain = 28 dB or 12m Cat 6 @ 3.125 Gbps

EMI Scrambler Spreads energy across spectrum

Low System Cost FPGA friendly interface

Easylink enables use of low cost FPGAs and cheaper cables

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Functional Block Diagram

Instrument Input Mgmt

27 / 51 Bits

Spartan 3CLK5 Data

TTL LVDS

CLK

5 Data

Back Channel

CML

LVDS CML

100 ft. Cable

Instrument Input Mgmt

27 / 51 Bits

Spartan 3CLK

5 Data

TTL

CLK

5 Data

Back Channel

Easylink

DS32EL0421

Easylink

DS32EL0124

Easylink

DS32EL0421

Easylink

DS32EL0124

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Signal Path Configuration

Link Aggregation :

SER DES

SER DES100ft

2.7Gbps

2.7Gbps

4-bit LVDS + Data Valid

Signal De-Emphasis

Equalizer

DC Balance + Scrambler


Signal


Signal


Signal

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Machine Vision

Expensive Cables!!

Cheap Cables!!

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Application Requirements

Requirements Easylink Feature CommentsMultiple End Points(recorder, monitor etc.)

Secondary I/Os, Retimed Loop Through Driver

8m link distance Integrated Signal Conditioning blocks, DC Balance encoder


2-5.5 Gbps Data Payload

Wide Operating Range, DV signaling

1.25-3.125 Gbps operating range, stack link to reach high data rates

Reduce System Cost Enables use of CAT cables

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Block Diagram

Sensor/CCD/AFE

Camera

FPGA

4 LVDS

4 LVDS

FPGA

Frame Grabber Card 1

4 LVDS

4 LVDS

Frame Grabber Card 2

Easylink

DS32EL0421

Easylink

DS32ELX0124

Easylink

DS32EL0124

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SER DES DES DESDaisy Chained Links :

SER DESPoint-to-Point Link: CAT Cable

5-bit LVDS5-bit LVDS ScramblerScrambler

Retimed Loop Through Driver

Retimed Loop Through Driver

5-bit LVDS5-bit LVDS

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OTS – Optical Terminal Systems

16x OTS – Transmitter

CLK

DS32EL0421DS32EL0421DS32EL0421DS32EL0421

Fiber Optic Cable

Low

Cost

FPGA

.

.16x

4 DATA (LVDS) Opto

Module

Max Data Throughput 2.5 Gbps

16 video channels

Just one Ser/Des needed for 16x OTS!

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Requirements Easylink Feature CommentsFiber interface Supports AC

coupling, Integrated DC Balance

link distance = <5 in FR-4 to SFP

Integrate Signal Conditioning, Configurable VOD

2.5 Gbps Data Payload


1.25-3.125 Gbps operating range,

Reduce System Cost Enables use of low cost FPGAs

FPGA friendly interface, low I/O count

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Multiplexing System – OTS Example

FPGA

Amp ADCCVBS

Video 1

OpticModule

.

.

.

.

OpticFiber

Amp ADCCVBS

Video 16

.

.

.

.

.

.

.

.

1 to

16

Cam

era

Inp

uts

Approx Serial Bandwidth For OTS Systems

1 CVBS Video Channel = 160 Mbps

16 CVBS Video Channel = 2.56 Gbps

Easylink DS32EL0421

Multiple Slow Speed Sources

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Gbps

DC Balance encoder

DC Balance encoder

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Data Com / Telecom Rack Mount Systems

User ports box 2

User ports box 1

CM

L/LVD

S

Cascade box

FPGA/ASICEasylink TX

Easylink RX

Easylink TX

Easylink RX

Easylink TX

Easylink RX

x # boxes

Stack more boxes

Each user port interface consists 1 TX and 1 RX Links

Cascade box consists of 1 TX and 1 RX Link times # of boxes in stack

Cascade Solution > 10 Gbps bi-directional links > x3 reduction in interconnect

FPGA/ASIC

FPGA/ASIC

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Requirements Easylink Feature CommentsTypical Data Rates: 1.25, 2.5, 3.125, 6.25, 10 Gbps


1.25-3.125 Gbps, DV assists with link aggregation

2-10 m cable, or 8-40 inch FR-4

Integrated Signal Conditioning blocks


Data is packeted and encoded

Raw Link or Data Pipe Mode

Coder bypassed, sends raw data out

Low EMI Integrated Scrambler

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Block Diagram

FPGAFPGA

2 meters

Box-1 Box-2

Easylink

DS32ELX0124

Easylink

DS32EL0124

Easylink

DS32ELX0124

Easylink

DS32ELX0124

24




Gbps

SER DESRedundant Links :

E.g. CAT-5e (100-ohm diff)

E.g. Coax (75-ohm)

Secondary Output

Independent Signal Conditioning BlocksIndependent Signal Conditioning Blocks

ScramblerScrambler

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Easylink Demo

Analog Launch Pad

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ELXEVK01 – Easylink & ALP

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ALP Main Screen

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ALP – BERT tab

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Appendix

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Scrambler Details

• Purpose: To create transitions to prevent “false lock,” spread energy across spectrum

• Scramber is 40 bits long• Chance of receiving the Pathological pattern =

1 / (240)

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Why DC Balance?

• AC coupled transmission lines behave as high pass filters

• Long string of all 1’s or all 0’s are affected by a high pass filter effect, resulting in base line wander

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Cable Length vs. Frequency Summary

Cable Type

Line Rate(Gbps)

DC Balance Data?

Max Length (m)

Infiniband 3.125 Yes 30

Infiniband 3.125 No 20

Cat-5 3.125 Yes 10-12

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Low Cost FPGA

Redundant I/O and Retimed Output

DS32ELX0421Low Cost

FPGA

DS32ELX0124

DS32ELX0124Low Cost

FPGA

Primary Card

Backup Card

Primary Serial Output

Secondary Serial Output

DS32ELX0124

Next Hop Card

FPGA

DS32ELX0124

Next Hop Card

FPGA

Master Controller Card

Retimed Serial Output- No Accumulated Jitter Issues

- No Serializer Required at Each Hop

- Implement Cable Extender

- Useful for Media Conversion

Implement Failover System Designs

ELX Series Only

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Ser/Des Interface Evolution

ControlPLL

Para

llel to S

erial

Serializer

Cables, Backplane, Board Traces

LV

DS

Interfa

ce

Stage-2 “Hard” Serialization

E.g. 4-to-1

Reduced Pins,

Lower Power, EMI,

Higher SpeedFPGA / ASIC

System Logic

LV

DS

Interfa

ce

NARROW Bus

Stage-1 “Soft”

Serialization E.g. 16-to-4

LVDS Interface Simplifies Board DesignReduces Bus Width, Improves Noise Tolerance

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FPGA Friendly Ser/Des Interface

FPGA

DS32EL0421N

CLK

TxIN[0]

TxIN[1]TxIN[2]

TxIN[3]TxIN[4] / DV

TxCLK – 125 to 312.5 MHz (DDR)

Customer Code

LVDS

NSC Sample Code

100Ω Diff Impedance Trace

Reduced Pin Count, Increased Performance

Use as many lanes as application requires!

• Parallel Side Data Interface – LVDS– 4 or 5 data lanes (per channel)– Reduced pin count and board traces– Increased signal integrity, Low EMI– 625 Mbps/LVDS lane @ Max rate– LOS Detect

• Parallel Side Clock– 125 Mhz to 312.5 Mhz (DDR) – High Jitter Tolerance

• Internal LVDS Termination• “Data Valid” Signaling

– Assists upper protocol synchronization

EL, ELX Series Only

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Integrated Signal Conditioners

After the Channel Equalized Output

After De-Emphasis

Reduces System Cost

DC Balancing - Bypassable

De-Emphasis 4 Levels

Output Amplitude

Equalization 4 Levels

20m CATx CableData Input

Data Output

Serializer De-Serializer

Desired levels configurable via pins/registers

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Simplified Clocking

• No Receiver Reference Clock Needed

• High Jitter Tolerance on Serializer Input Clock

• Low Jitter DeSerializer Output Clock : Drive Receiver System

• Best in Class Output Jitter : DJ = 0.07 UI, RJ = 2 psrms

• 20 MHz “Keep Alive” Clock Output – Even with no active link

• Receive Jitter Tolerance to Achieve BER < 10-15

– DJ (ISI) = 0.37 UI– Sinusoidal (PJ) = 0.6 UI– RJ = 0.18 UI 3.125 Gbps

over 40” FR-4

Reference Clock NOT needed

EL, ELX Series Only

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DS32EL(X)0421 SerializerOptimized to Clean FPGA PCLK Jitter

Yellow Line: Input clock to DCMBlue Line: DCM output clock (from FPGA)

Yellow Line: Input clock to LMH0340 (from FPGA)Blue Line: LMH0340 output clock

(FPGA) DCM adds considerable phase noise Low BW of Serializer PCLK PLLfilters (FPGA) DCM noise

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EMI Control on the Parallel Side

• LVDS signaling– Elimination of switching current from

Vcc to Ground– Well-matched 100-ohm(differential)

impedance, reduces EMI from reflections

– Differential signals reduces emitted radiations by canceling the field lines

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EMI Control on the Serial Side

• Transmitter side– Fully differential output driver : Reduces common-mode noise– Programmable output termination : Control reflections– Programmable Vod and De-emphasis : Controls the amount of

energy that is transmitted on the line

• Receive side– Wide dynamic range and wide-common mode– Programmable Equalizer allows the receiver work with

shielded twisted-pair cables (E.g. CAT-7)

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EasyLink Motivation What problem are we solving?

Existing Solutions = Too Much System Overhead!

Solution Extra Header

Data-rate

FPGA Framing Logic

PCIe 24 bytes 2.5G, 5G

8600 LE

Serial RapidIO

24 bytes 1.25, 2.5G

12119 LE

SATA 4 bytes 1.5, 3, 6G

3953 LE

Easylink 0 2.5, 5G*

0

Header = Transaction + Data Link Header

Datarate noted for single channel version only

5G* in development

Datarate includes 8b/10 coding overhead

LE noted is for Cyclone-2 Altera Megacore datasheets

LE = Logic Elements

(Logic Gates)

• Requires Packetization and Interruption of application data

– Step1 :Send Alignment, Sync Characters

– Step2 :Send Application Data

– Step3: STOP Application Data, Go back to Step1!!

• Many External Components Required

– Reference Clock

– Signal Conditioning : Pre-Emphasis, Equalization

– Clock Conditioning : Jitter Cleaning

• Not FPGA Friendly

– 16/32 bit parallel interface – Requires lots of I/O

– Added logic for framing/deframing – Consumes precious logic elements

• E.g. TLK-2501, PMC-8358, Cypress Hotlink

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Cable Diagnostic Features

• Cable Plug/Unplug detect– Signal detect on the Receive– Link detect on the Transmit side

• Redundancy– Dual output drivers– An input 2:1 Mux on the receive side

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Wide operating range 125 Mbps - 3.125 Gbps per diff lane, Supports 40” to 80” of FR-4 (over multiple connectors)

LVDS parallel interface Low EMI, power, noise sensitivity

Programmable voltage swing Reduces power consumption

Programmable Transmit de-emphasis Better signal integrity

Integrated AC coupling and internal termination

Enables direct interface to other devices,Reduces component count

Programmable receive equalization Equalizes difficult channels

No external reference clock Reduce system BOM, board space

No external framing or alignment protocol Ease of use, No logic elements wasted to implement framing protocol (E.g. PCIe, Serial RapidIO requires 10k-12k LEs to implement their state-machines!)

Easylink For Backplanes Feature, Benefit Analysis

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FPGA SerDes SolutionsCost Comparison – Option #1

Parameter FPGA with Integrated SerDes Easylink + Lower Cost FPGA

FPGA > $75 (Stratix-II GX – Low LE, I/O) < $20 (Cyclone III)

Voltage Regulation$5 (requires low noise regulator for

SerDes) $1

Power Decoupling$13 (Requires Tantalum, Low

Impedance Caps) $1 (Ceramic Caps)

Reference Clock $13 $0 (No reference clock required)

Extra Power/Ground Planes 1-2 extra power planes $0

Equalization for 20m CATx type cables $10 $0 (Integrated in Easylink)

Thermal Protection $10 $0

Jitter Sensitivity High Low

Cable Performance Very Limited ( < 2m @ 3.125G) 20m CAT6/7 (@ 3.125 G)

Design Time VERY High Low

Total > $116 < $26

Cyclone-II/III

CycloneStratix-II GX

Stratix-III GX

Reduce system $$$ by migrating to lower cost FPGAs

Volume Pricing (10k) used

Component Pricing Based on Altera User Guide, Stratix-II GX reference design BOM/Schematics

SAVINGS = $90!Easylink Single SerDes Price NOT included

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FPGA SerDes SolutionsCost Comparison – Option #1

Parameter FPGA with Integrated SerDes Easylink + Lower Cost FPGA

FPGA > $50 (Virtex-II Pro– Low LE, I/O) < $20 (Spartan-3E)

Voltage Regulation$5 (requires low noise regulator for

SerDes) $1

Power Decoupling$4 (Low Impedance Caps, Ferrite

beads) $1 (Ceramic Caps)

Reference Clock $9 $0 (No reference clock required)

Extra Power/Ground Planes 1-2 extra power planes $0

Equalization for 20m CATx type cables $10 $0 (Integrated in Easylink)

Thermal Protection $5 $0

Jitter Sensitivity High Low

Cable Performance Very Limited ( < 2m @ 3.125G) 20m CAT6/7 (@ 3.125 G)

Design Time VERY High Low

Total > $74 < $22

Reduce system $$$ by migrating to lower cost FPGAs

Volume Pricing (10k) used

Component Pricing Based on Xilinx User Guide, Volume pricing from digikey

SAVINGS = $52!Easylink Single SerDes Price NOT included

Spartan 3/3L/3E

Spartan IIE/XL

Virtex 5 LXT

Virtex 5 SXT

Virtex II Pro

Assuming one bidirectional channel On FPGA

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FPGA Comparison

FPGA

High or Low Cost

Design complexity = HIGH

Added PCB layers = $X

SerDes requires Low noise

regulators and low impedance

caps = $11

Reference Clock = $8-$13

External Cable Driver = $4-$8

External Cable Equalizer = $6-$12

Thermal Protection = $10

Shared (Clock, Thermal, PCB) = $28

Per Channel = $21

Total = $29/Channel (assuming 4 channels)

FPGA

High or Low Cost

Design complexity = Low

Added PCB layers = Not required

Easylink Ser = $11

Easylink Des = $12

Power supply = $2

Shared = $0

Per Channel = $25

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Target Customers – Wide Playing Field

• Industrial Imaging– Sony– Matrox– Toshiba Teli– Dalsa– Imperx– Hamamatsu– Eltec– Ikegami– Festo– Hitachi– Cognex– Basler– ASML– Tomra

• Medical Imaging– Toshiba– Aloka– Hitachi Medical– Shimadzu– GE Medical– Siemens– Phillips– Esaote– Barco– Canon– Fuji– Mindray– Sonoscape– NDS

• Security Imaging– Bocom– Infinova– Halley– Hongdy– Integra– Axis– Pelco– American Dynamics– Bosch– Panasonic– Toshiba– ONV– NICE

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Target Customers – Cont’d

• Printers– Canon– Fuji Xerox– EFI– Konica Minolta– Ricoh– Kyocera– Sharp– OCE– Xerox Inc– Sagem– Creo– Heidelberger Druck

• Communications– Ericsson– Siemens– NEC– Hitachi– ZTE– Hauwei– Motorola– Datang– Panasonic– Fujitsu– ADC– Alvarion

• Display apps– Barco– Daktronics– Huawei– DRS Systems– Tyco Systems– Scopus– Sagem– Aesys– Odeco– Altoona– Hi-Tech

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Smart SerDes vs. Easylink

LMH0341 DS32EL0124 DS32ELX0124SMPTE compliance YES NO NO

Datarate Discrete Frequencies

DVB-ASI(270Mbps), 270Mbps, 1.4835G, 1.485G, 2.967G, 2.97G

Continuous Frequency Range –

1.25 Gbps to 3.125 Gbps

Continuous Frequency Range –

1.25 Gbps to 3.125 Gbps

Lock time < 16 msec 50-200 msec 50-200 msec

Reclocker YES NO YES

Frequency hot swap

Supports frequency hot swap. Data rate can change from any data rate to any other data rate and the part will adapt without the necessity of a Reset or a Power cycle

Does not support frequency hot swap. If the data rate changes on the fly, then the part requires a Rest or a Power cycle to relock to the new frequency

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How can Easylink reduce system cost?

A. B. C. D. E.

20% 20% 20%20%20%

1010


A. Drives Long Cheap Cables

B. Built-in EqualizerC. No Reference Clock

NeededD. All of the aboveE. None of the above

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What signal conditioning features does Easylink offer?

A. B. C. D. E.

20% 20% 20%20%20%

1010


A. Transmit De-EmphasisB. Transmit Output

Amplitude AdjustmentC. Receive EqualizationD. A and CE. All of the above

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What feature(s) does the ELX device offer that the EL and ES devices do not?

A. B. C. D. E.

20% 20% 20%20%20%

1010


A. Output De-emphasisB. Re-timed Serial

OutputC. Input EqualizationD. No Reference Clock

CDRE. All of the above

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What are the main advantages of LVDS parallel interface over LVCMOS?

A. B. C. D. E.

20% 20% 20%20%20%

1010


A. Lower Crosstalk and EMI

B. Lower PowerC. Lower Noise ImmunityD. A and BE. All of the above

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Easylink devices are only configurable through the SMBus

A. B.

50%50%

1010


A. True

B. False

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When is DC Balancing required?

A. B. C. D.

25% 25%25%25%

1010


A. Low power systems

B. AC Coupled transmission lines

C. High data rate linksD. Never

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With Daisy-Chaining type applications what is the biggest issue that system designers have to deal with?

A. B. C. D.

25% 25%25%25%

1010


A. Accumulated Jitter B. Limited Cable ReachC. FPGA Cost D. Thermal Issues

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What is the minimum requirement on the Reference Clock input for EL device?

A. B. C. D.

25% 25%25%25%

1010


A. 1500 ppmB. 100 ppmC. No Reference

Clock NeededD. 5% of TxClkIn

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Easylink Ser/Des can be configured to operate in which of the following systems?

A. B. C. D.

25% 25%25%25%

1010


A. High speed point-to-point links

B. Daisy Chain applicationsC. Redundant/Fail Over

systemsD. All of the above

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Easylink can be used with which of the following types of interconnect?

A. B. C. D. E.

20% 20% 20%20%20%

1010


A. CAT-5,6,7 cablesB. FiberC. Coax D. FR-4E. All of the above

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1 Mike Wolfe Applications Engineer Interface Division Taking the Guess Work out of High-speed Data...

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Transcript of 1 Mike Wolfe Applications Engineer Interface Division Taking the Guess Work out of High-speed Data...