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Low-power Multimedia Wireless Communication Systems
Naresh R. Shanbhag
Coordinated Science LaboratoryDepartment of Electrical and Computer Engineering
University of Illinois at Urbana-ChampaignURL://uivlsi.csl.uiuc.edu/~vips/
2
Trends and Problems in Integrated Circuits
(Source: Semiconductor Industry Association 1997 Roadmap)
• Problems (due to Systems-on-a-chip in deep submicron)– Time-to-market/Design productivity vs. Design complexity => Solutions:
Design reuse via Intellectual Property; Design exploration; H/S codesign, Reconfiguration
– Reliability: noise, signal integrity, process variations => Solutions: noise analysis, smart place&route, noise-tolerance
– Design efficiency: low-power and high-speed techniques & bounds
Current day Integrated Circuit Integrated Circuit in 2012*
0.2 micron 0.035 micron 3.7M/sq.cm 180M/sq.cm750 MHz 10 GHz250 MHz 1.54 GHz1.8-2.5V 0.5-0.6V70 Watts 175 Watts1.2 Watts 3.2 Watts
FEATURE SIZE
DENSITY
ON-CHIP CLOCK
OFF-CHIP CLOCK
SUPPLY VOLTAGE
POWER (HIGH PERF.)
POWER (MOBILE)
0.5-0.75 micron 0.1-0.15 micronWIRE PITCH
3
(Source: www.ti.com/sc/docs/wireless/97/issues.htm)
Integrated Multimedia Communication Systems
Source(video/speech/
data)
ChannelRFSource
Proc./Coding
ChannelCoding
Modulation
• Additional Problems:– mixed-signal issues: coupling, low-voltage analog, etc.
• Additional Solutions: DSP and communication theory; joint source-channel coding, signal-adapted DSP, multiresolution DSP; well-defined system/algorithm design
4
Standards(VDSL, ATM
Wireless, Video)Specifications
Multimedia Communication System
Design
• Projects:– Wireline system design: ATM-LAN, VDSL, cable modem (Goel, Hegde,
Tschanz)– Wireless system design: (Wang)– Hermitian decoder ASIC (Profs. Blahut and Kotter, Ashbrook, Feng)– Low-power transforms and synthesis: (Profs. Hajj and Najm, Ramprasad,
Hegde)
System Design IC Design
IC Fab&Test
5
Noise-tolerant VLSI
Algorithmic Noise-Tolerance
Circuit
Architecture
Logic
No
ise
Pro
pa
gatio
n
Noise Analysis/Measurements
Noise Models
Architectural Noise-Tolerance
Logic Noise-Tolerance
Noise-Tolerant Circuits
Algorithm
• Projects:– Algorithmic noise-tolerance (Hegde, Wang)– Noise-tolerant circuits (Wang, Ganesh)– Noise-tolerant distributed arithmetic filters (Anders)
6
Deep Submicron (DSM) Noise
• Ground bounce
• IR drop
• Crosstalk
• Charge sharing
• Charge leakage
• Process variations
• Alpha particles
• Electro-magnetic radiation
(b)
VDD
VSS
D Q NIC-GB
M1
Error
Q
D
Noise Problems: aggressive architectural (deep pipelining) and circuit (dynamic, low-voltage) styles.
Noise Sources:
7
Mirror Technique For Dynamic Circuit
Vin1 Vin2
Vout
Vout
NMOSLOGIC
NMOSLOGIC
Vin1
VinN
NMOSLOGIC
Vin1
VinN
Vout
(a) Conventional domino (b) Mirror technique (c) NAND gate design
8
ANTE: A Noise-Tolerance Metric
Cnic1
Cnic2
Error Free
Noise Immunity Curve
• Average Noise Threshold Energy
• Energy Normalized ANTE
noisenoiseTVEANTE 2
ANTE
NANTE
: Energy dissipated per cycle
9
Simulation Results: Full Adder
Mirror technique
Static
Conventional dynamic
Design Specifications:
(1) Power supply: 3.3V(2) Load capacitor: 20fF(3) Clock cycle: 1GHz
Area( 2m)
Energy(pJ)ANTE(nJ)
EnergyNormalized ANTE
Static 574.32.202 3.115 1414Conventional dynamic288.80.889 1.405 1580Mirror tech. 487.21.693 5.203 3073
Technology: 0.35 micron CMOS
10
Noise-Tolerant ASIC
Technology: 0.35m CMOS Pin #: 48
Transistor #: ~ 20K Area: ~ 5mm2
Technique: dynamic, mirror noise-tolerant dynamic
Measured Noise immunity improvement: 34.1% ~ 69.5%, average: 55.2%
11
Soft DSP
DSP BLOCKLATCH LATCH
FROM A/D TO A/D
CLOCK
SUPPLY VOLTAGE
DELAY
Vdd-crit
CLOCK-PERIOD
TRADITIONAL DSP DESIGN• critical-path-delay of the DSP block < sample period.
• reduction in supply voltage to the DSP block is limited by Vdd-crit.
Soft DSP
• reduce Vdd beyond Vdd-crit.
• detect/correct errors in output via Algorithmic Noise-Tolerance. MEET THE SNR/BER CRITERION AT REDUCED ENERGY DISSIPATION.
12
Error Probability in Arithmetic Units
PATH-DELAY DISTRIBUTION OF 8-BIT RIPPLE CARRY ADDER
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
x100
% in
pu
t co
mb
inat
ion
s
1 2 3 4 5 6 7 8
delay in multiples of FA delay
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
probability of errorfa
ctor
by
whi
ch e
nerg
y di
ssip
atio
n re
duce
s
• 48% reduction in energy dissipation possible with prob. of err. = 0.1• distribution with long tail leads to smaller error penalty• errors at the AU level lead to SNR/BER degradation• Algorithmic Noise-Tolerance to enhance performance
13
Algorithmic Noise-Tolerance (ANT)
SOFT DSP Error Control
x(n) (n)erryy(n)(n)
^ y
e(n)
0(n) y when0e(n)
0(n) y when0 e(n)
:
err
err
IDEAL
ANT via LINEAR PREDICTION:
hN
• exploit the correlation in filter output to perform error-control• optimum predictor for error detection - minimize MSE e(n)
e (n) when y (n) = 0err
0 e (n)+ y (n) errp
p
SOFT DSP FILTER
x(n) D D D(n)y
^
(n)eph1 hN-1
(n) y e(n) (n)e errp
14
Frequency Selective Filtering via Soft DSP
35
40
45
50
55
60
65
70
0 5 10 15 20 25
SNR at the filter output
% r
ed
uc
tio
n in
en
erg
y d
iss
ipa
tio
n
difference-based ANT-based
• difference-based scheme :
• 52% power savings with 1dB SNR loss (effective for high correlation).
• prediction-based scheme:
• 44% power savings with 0.7dB SNR loss (overhead: 2-tap predictor)
• effective for low correlation (higher BW).
SNR desired = 20dB
15
Information-Theoretic VLSI Framework
• Information Transfer Rate: R (bits/sec)• Information Transfer Capacity: C (bits/sec)• For reliability : C > R; For energy-efficiency: C R
Algorithm:input stats.,I/O map
Implementationarch., circuit, tech.,DSM noise
R
C
Achievable boundson reliability and efficiency
• Projects:– Lower-bounds on energy-efficiency of noisy digital circuits (Hegde)– Lower-bounds on signal transition activity and coding schemes
(Ramprasad, Prof. Hajj)– Bounds on: throughput and energy-efficiency; adaptive systems (Goel)– Design techniques for ultra efficient VLSI
Soft DSP
16
Lower Bound on Energy Dissipation
• Minimize: Eb = (Pdyn+ Pstat)/R bits/sec
subject to: C R
• operating point: fc = kmVdd/ CL
N. R. Shanbhag, University of Illinois at Urbana-Champaign
C L
Information Transfer Rate : R
N
Transition Activity : t
Operating Speed : f c
Q(Vdd/2
17
Dynamic Power
N. R. Shanbhag, University of Illinois at Urbana-Champaign
Energy dissipation at minimum supply voltageis greater than minimum achievable energy dissipation
18
Controller(ROM,microprocessor,
ASIC)
Reconfigurable
data-path(ASIC, FPGA,
multi-processor)
Signal ProcessingAlgorithm
(SPA)
Input Output
Signal MonitoringAlgorithm
(SMA)
AuxiliarySignals
ControlSignals
Reconfigurable DSP
• Dynamic Algorithm Transforms:
• Projects:– Low-power adaptive filtering, VDSL equalizer ASIC (Goel, Tschanz)– Domain-specific reconfigurable DSP processors (Tschanz)– Reconfigurable DSP for video processing (Minocha)– FPGA board design (Park)– Video over wireless (Profs. Jones and Ramchandran)
min Energy/Throughputsubject to: DSP constraint
19
min Energys.t. J < Jo
DSPmodels
Energymodels
Input state-space S
Configurationspace C
Energy-optimumconfiguration
Dynamic Algorithm Transforms (DAT)
A framework for designing low-power reconfigurable DSP systems
20
Input State-space S
• Set of all possible input states
pt(s2,s2)s1=G s2=B
• s(n) = received signal power• Two-state model• State s1 : Good channel• State s2 : Bad channel• p(si) : steady-state probabilities• pt(si,sj) : transition probabilities
pt(s1,s2)
pt(s1,s1)
pt(s2,s1)p(s1) p(s2)
0.01
0.1
1
10
100
1000
0 0.1 0.2 0.3time
Re
ce
ive
d s
ign
al p
ow
er
Good channel G
Bad channel B
Signal power received at the mobile unitmobile speed = 60 miles/hr
RF signal frequency = 2 GHz
21
Configuration-space C
• Set of all possible configuration vectors the reconfigurable datapath can support
Dx(n)
0
w1
Dx(n-1)
0
w2
Dx(n-N+1)
0
wN
Nth TAP
y(n)
c(n)=[…] : N-bit configuration vector
C: Set of all N-bit tuples (2N vectors)
22
ONU
TWISTED PAIR DISTRIBUTION CABLE
FIBER
System Data-rate Distance
ADSL 1.544 Mb/s 18 kft
ADSL 8.448 Mb/s 9 kft
VDSL 12.96 Mb/s 4.5 kft
VDSL 51.84 Mb/s 1 kft
Very High-speed Digital Subscriber Loop
• Cable length– 100ft to 1kft (worst-
case)
• Far-end crosstalk– 4-11 interferers
• Desired BER=10-7
– SNR=21.5dB
23
51.84 Mb/s VDSL Transmitter
In-phase shaping filter
Q-phase shaping filter
16-CAPEncoder
Scrambler DAC LPF51.84Mb/s
– square-root raised cosine– excess bandwidth=36%– center frequency=12.96 MHz
Real
Imag
16-CAP signal constellation
51.84 MHz
Analog Front End
24
51.84 Mb/s
I-PHASE EQUALIZER
SMA BLOCKA/D
SLICER
Q-PHASE EQUALIZER
SLICER
DECODER
DSCRAMB
W,e(n)
W,e(n)
FBF
+
+TimingRecovery
PGAControl
PGA
DAT-based 51.84 Mb/s VDSL Receiver
– I/Q-phase equalizers: 48 taps each– FBF: 10 complex strength-reduced taps– Powers of two LMS + Blind Equalization
25
-20
020
4060
8010
0
0 0.2 0.4 0.6 0.8 1
Cable length (kft)
En
erg
y S
av
ing
s (
%)
VARIATIONS IN CABLE LENGTH VARIATIONS IN FEXT INTERFERERS-2
00
2040
6080
100
2 4 6 8 10 12
Number of FEXT interferers
En
erg
y S
av
ing
s (
%)
Energy Savings: 51.84 Mb/s VDSL
AVERAGE ENERGY SAVINGS=53%
26
Wireless Environment
MOBILE
MULTIPATH CHANNEL
MULTI-USER
INTERFERENCE
ANTENNA
BASE
STATION
ANTENNA
• Adaptability of system to time-varying propagation and traffic environments
• Adaptation to different spectrum allocations
• Ability to accommodate mixed-cell (pico, micro and macro) architecture
• Ability to handle different services: audio, video, speech,data, multimedia
Flexibility Features of IMT-2000 systems
27
ChannelEncoder
t
PowerAmplifier
Pt
ChannelDecoder
t
RAKE Receiver
crake
OUTER TRANSCEIVERINNER
TRANSCEIVER
SNRDistortion and BER
Reconfigurable Wireless Communication System
SourceEncoder
Rs
SourceDecoder
Rs
Image
Video
Wireless
Wireline
• Energy-optimum configuration via Dynamic Algorithm Transforms and Joint Source-Channel Coding
otot
oi
RcR
DscDts
cEnergy
)(
),(..
)(min arg)(sc iopt
• With Doug Jones and Kannan Ramchandran
28
Source-Channel Variabilities
(Rate-Distortion Curves)
SOURCE VARIABILITIES
(BER Curves)
CHANNEL VARIABILITIES
110
010
000
0 1 2 3
Source Rate (in bits per pixel)
Ave
rag
e D
isto
rtio
n p
er
pix
el
carphone
akiyo
coastguard
00.
51
4.5 5.5 6.5 7.5
Channel SNR (Eb/No)
Pro
ba
bili
ty o
f e
rro
r
t=16
t=24
t=32
29
Simulation Results: QCIF Images and IMT-2000
Test channels
• Energy Savings: maximum 93% (average 59%)• Fraction of Energy due to the digital blocks:
– ranges from 40-10% (for distance: 10-100m)
Channel A (low delay spread) Channel B (medium delay spread)
0
0.0004
0.0008
0.0012
0.0016
0.002
0 20 40 60 80 100
distance (in m)
En
erg
y (i
n J
/pix
el)
akiyo carphone
claire coastguard
container hall_objects
mother_and_daughter silent
0
0.0004
0.0008
0.0012
0.0016
0.002
0 20 40 60 80 100
distance (in m)
En
erg
y (i
n J
/pix
el)
akiyo carphone
claire coastguard
container hall_objects
mother_and_daughter silent
30
Summary
• Evolving next generation (3G) wireless standards: flexibility and
energy-efficiency. • Evolving integrated circuit technology: deep submicron noise, complex
system-on-a-chip (SOC).• DSP via Soft Computations (Soft DSP): energy-efficient,
noise-tolerant circuit design and algorithmic noise-tolerance• Dynamic low-power techniques are required
– inter-application dynamism => domain-specific processors
– intra-application dynamism => run-time reconfiguration
• Dynamic algorithm transforms: input space, configuration space,
DSP models, energy models, joint-optimization of energy
& performance