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IntroductionVLSI Testing

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Overview

• First digital products (mid 1940's)

Complexity: low

MTTF: hours

Cost: high

• Present day products (mid 1980's)

Complexity: high

MTTF: Perhaps centuries?

Cost: low

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Observations

Testing is a cost burden, people buy digital devices to provide computation, control and/or communications.

The percentage of product development dollar allocated to testing continues to increase.

Test problems have changed, but the need for testing continues.

Test emphasis changes over time. As product cost declines, maintainability is less important than it once was.

There is no one single solution to the testing problem.

4

Focus

What makes circuits difficult to test (why do the algorithms fail)?

How can the complexity of the problem be reduced?

How can algorithms be made more effective?

What are the trade-offs between the various existing strategies?

What are the likely future directions?

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DEFINITIONS

• Fault: a physical condition that causes a device, component, or element to fail to perform in required manner.

• Design Fault: a design characteristic of either hardware or software which causes or materially contributes to device malfunction independent of the presence of physical faults.

• Failure: the termination of the ability of a chip to perform its required function.

• Error: functional manifestation of a fault.

• Test OrTest Pattern: a specified primary input stimulus plus the expected

fault-free primary output response.

• Fault Detection: application of test patterns which discover or are designed to discover the existence of faults.

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DEFINITIONS (Continue)

• Fault Isolation: where a fault is known to exist, a test sequence which identifies or it is designed to identify the location of that fault within a specific circuit.

• Fault Coverage: An attribute of a test or test expressed as the percent of faults of the total fault population

which that test procedure will detect.

• Fault Masking: The ability to avoid a fault by concurrently detecting and correcting all faults.

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Failures are caused by defects such as:A. Contamination.

B. Metallization Defects.

C. Implant Defects

D. Wafer Defects

E. Oxide Defects

F. Interconnect Defects

G. Design Defects Such As:• Too narrow conductors; high voltage drops.

• Too high voltage across oxide; hot electron injection.

• Too critical dimensions

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FAILURES OBSERVED BY DIRECT INSPECTION OF 4-BIT MICROPROCESSOR CHIPS*

SHORT BETWEEN METALLIZATIONS 39%

OPEN METALLIZATION 14%

SHORT BETWEEN DIFFUSIONS 14%

OPEN DIFFUSION 6%

SHORT BETWEEN METALLIZATION AND SUBSTRATE 2%

INOBSERVABLE 10%

MISCELLANEOUS 15%

* GALIAY, CROUZET, AND VERGNIAULT, IEEE TOC JUNE 1980.

ALMOST ALL FAILURES ARE DUE TO

SHORTS AND OPENS

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MOS/CMOS has emerged as an important technology

A WELL TESTED INTEGRATED CIRCUIT

Is As IMPORTANT AS

A WELL DESIGNED INTEGRATED CIRCUIT

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COST

A STANDARD AMONG PEOPLE FAMILIAR WITH THE TESTING PROCESS IS:

If the cost for detecting a fault at the chip level is:

$X

Then to detect that same fault at the board level is:

$10X

At the system level:

$100x

At the system level but when it has to be found in the field:

$1000X

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Test Economics

Shipped Product Quality Level

Y-Process yield

T-quality of test (fault coverage)

• Given the desired SPQL, and the process yield, the required test effectiveness, T, is fully determined.

• In logic circuits, T is computed by means of fault simulation.

• Defect level (DL) is often used as the measure of goodness, where:

DL=1 –SPQL

YSPQL T )1(

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MEAN FAULT CYCLE

Fault Occurs

Manifests

System Recovery

Corrected

Isolated

Detected

Manifests

System Recovery

Time

MTTD

MTTR

MTBF

System Available

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SIGNIFICANCE OF FAULT MODELS

• A fault model is a hypothesis representing the fault mechanism in a circuit.

• The reliability of the product is determined by the accuracy and effectiveness of the fault model.

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COMPLEXITY

• If a network contained N nets, any net may be good; s-a-1 or s-a-0. Thus all possible network state combinations would be 3N. Assume a network with 100 nets, then there are 5x1047 different combinations of faults.

• Test generation and fault simulation is approximately proportional to the number of gates to the power of 3.

• For functional testing if a network has N inputs (combinational) then 2N patterns are required for complete functional test. If the network has N inputs and M latches then 2N+M patterns are required.

For VLSI assume

N = 25 and M = 50 then

#Patterns = 275 3.8×1022

Assume test rate of 1 µ sec, then test time over 109 years

T=kN3

ComputerRun time

Constant Number ofgate

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THE TESTING PROBLEM

GIVEN A SET OF FAULLS, OBTAIN TEST VECTORS

Q1: WHICH FAULTS? (FAULT MODELS)

Q2: HOW IS TEST DERIVED? • MANUALLY

• AUTOMATICALLYo ALGORITHMS (ATG)-PODEM, SOFTG

o KNOWLEDGE-BASED - HITEST

Q3: HOW IS TEST QUALITY MEASURED?• FAULT SIMULATION

o CONCURRENT METHOD

o FAULT SAMPLING

• FAULT COVERAGE AND PRODUCT_QUALITY

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WHY MODEL FAULTS?

• I/O FUNCTION TESTS INADEQUATE FOR MANUFACTURING (FUNCTIONALITY vs. COMPONENT & INTERCONNECTION TESTING)

• FAULT MODEL IDENTIFIES TARGET FAULTS

• FAULT MODEL MAKES ANALYSIS POSSIBLE

• EFFECTIVENESS MEASURABLE BY EXPERIMENTS

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SOME FAULT MODELS

SINGLE STUCK FAULTS

• TRANSISTOR OPEN / SHORT FAULTS

• MEMORY FAULTS

• PLA FAULTS (STUCK, CROSS-POINT, BRIDG1NG)

• FUNCTIONAL (PROCESSOR) FAULTS

• DELAY FAULTS

• ANALOG FAULTS

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SINGLE STUCK FAULTS

ASSUMPTIONS:

1. ONLY ONE LINE IS FAULTY.

2. FAULTY LINE PERMANENTLY SET TO 0 OR 1.

3. FAULT CAN BE AT AN INPUT OR OUTPUT OF A GATE.

1

0

0 (1)

1

1

0

0

Ture R

esponse

Faulty R

esponse

STUCK-AT-1

Test Vector

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FAULT EQUIVALENCE

TWO EQUIVALENT FAULTS ARE DETECTED BY EXACTLY THE SAME TESTS

THREE FAULTS SHOWN ARE EQUIVALENT

s-a-0 s-a-1

s-a-1

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EQUIVALENCE FAULT COLLAPSING

s-a-0

s-a-0 s-a-0s-a-1

s-a-1

s-a-1s-a-1s-a-0

N+2 FAULTS IN N-INPUT GATE

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DOMINANCE FAULT COLLAPSING

IF ANY TEST FOR F1 DETECTS F2 BUT CONVERSE IS NOT TRUE, THEN F2 DOMINATES F1.

ONLY N+1 FAULTS IN N-INPUT GATE

F1: s-a-1F2: s-a-1

s-a-1

s-a-1

s-a-0

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The Sensitized Path Method

Procedure:1. Create a Sensitized Path from the fault to the primary output.2. Justify the assignment of values to the outputs of internal gates.

Example:

G4

G7

G5

G6

G1

G2

G3

1

S/0

Z

0

1

11 good0 faulty

Sensitized Path

G4

G7

G5

G6

G1

G2

G3

1

S/0

Z

0

1

11 good0 faulty

Justify the assignment

1

1

X

X

X 0

0 X

X

0

1

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The Sensitized Path Method (Continue)

Problems with the Sensitized Path Method1. Making Choices

2. Reconvergent fan-out Paths

Making Choices

1

2

3

6

X1

X2

X3

X4

X5

Y

ZG3G1

G2G44

5

7

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The Sensitized Path Method (Continue)

Reconvergent Fan-out PathsThe sensitive path method is not guaranteed to find a test for a fault, even where such a test does exist.

Example:

Z

X1

X2X3

X4

S/0

1

G1

G2

G3

G5

G4

G7

G6

G8

0

1

0

0

0

0

0

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1 Inconsistent

• Try to propagate through G5 Inconsistent• Try to propagate through G6 Inconsistent• It appears that there is no test for the fault. However, such a test does exist

{0,0,0,0}

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Redundancy and Undetectability

• Fault 3/1 is undetectable because the gate is redundant.

• Z = X1X2 + X1X2X3 = X1X2

Z

4

5

1

2

3/1

X1

X2

X3

6

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The D-algorithm

Example:

S/0

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The D-algorithm

Example:

S/0

0

1=D

D

0

D1 good

0 faulty

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The D-algorithm

S/0

X1

X2

X3

X4

Z

Example:

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The D-algorithm

S/0

X1

X2

X3

X4

Z

Example:

D

0

D

1

0

×

×

D1 good

0 faulty

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The D-algorithm

S/1Z

X1

X2

X3

Example:

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The D-algorithm

S/1Z

X1

X2

X3

Example:

D

D1

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1

D1 good

0 faulty