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Interconnect and Packaging

Lecture 7: Distortionless Communication

Chung-Kuan ChengUC San Diego

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Distortionless Communication

1. Introduction of distortionless interconnect

2. Architecture of Surfliner

3. Implementation

4. Applications

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I. Interconnect Models

RΔl LΔlCΔl

RΔl LΔl

CΔl …

i(z,t)

RΔl LΔl RΔl LΔl

Voltage drops through serial resistance and inductance

Current reduces through shunt capacitance

Resistance increases due to skin effect

Shunt conductance is caused by loss tangent

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I. Interconnect Models

• Telegrapher’s equation:

),(),(),(

),(),(

),(

tzGVdt

tzdVC

dz

tzdIdt

tzdILtzRI

dz

tzdV

• Propagation Constant:

jCjGLjR ))((

• Wave Propagation:

//,),( 0 tzveVtzV tjzjz

• Characteristic Impedance

)/()( CjGLjRZ

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I. Introduction of Distortionless Interconnect

• Distortion:

Transfer function H(S) != const.

Digital signal contains multiple freqs.

Intersymbol interference

• Usage of limited frequency range

• Pre-emphasis at transmitter HT(S)

Equalization at receiver HR(S)

HT(S)H(S)HR(S) ~= const.

• Surfliner: HSurfliner(S) = const.

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II. Distortion: Frequency Ranges and Equalization

Input Signal Frequency Range Trimming

• Encoding (8B/10B)

• Data Scrambling

• Aliasing

Equalization

HE=a+bZ-1+cZ-2

Z-1 Z-1

a

bc

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II. Equalization

Courtesy of Ed Lee

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III. Distortionless Interconnect

• On-chip Global Interconnect trend

• Concerns: Speed, Power, Cost, Reliability

0

40

80

120

160

200

180 150 130 100 90 80 70 65 57 50Process Technology Node (nm)

Dela

y (p

s)

1mm Global I nterconnect with Scattering(source: I TRS Roadmap 2004)

FO4 I nverter Delay (Estimated by0.36*Ldraw)

1mm distortionless Transmission Line (Speedof Light)

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III. Introduction of distortionless interconnect

• Speed-of-the-light on-chip communication• < 1/5 Delay of Traditional Wires

• Low Power Consumption• < 1/5 Power Consumption

• Robust against process variations• Short Latency• Insensitive to Feature Size

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IV. Architecture of Surfliner

RΔl LΔlGΔl CΔl

RΔl LΔl

GΔl CΔl …

i(z,t)

RΔl LΔl RΔl LΔl

Differential Lossy Transmission Line Surfliner

RΔl LΔlCΔl

RΔl LΔl

CΔl …

i(z,t)

RΔl LΔl RΔl LΔl

Current loss through shunt capacitance

Frequency dependent phase velocity (speed) and attenuation

Add shunt conductance to compensate current loss R/G = L/C

Flat from DC Mode to Giga Hz

Telegraph Cable: O. Heaviside in 1887.

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IV. Architecture of Surfliner

• Set R/G=C/L• Frequency Independent speed and attenuation:

LCjCLRCjGLjRj //))((

• Characteristic impedance: (pure resistive)

CLZ /0 • Phase Velocity (Speed of light in the media)

LCv /1• Attenuation:

lZ

R

elA 0)(

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IV. Architecture: Signal Response

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IV. Architecture: Eye Diagram

• Injected 1.0V voltage falls to 365mv over a 2cm wire

120 stage, 2.1ps jitter

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IV. Architecture: Speed, Power, Variations

• Speed of Light: 5ps/mm or 50ps/cm

• Power: 10mW at >GHz

• Conductance variation = 10%, f=10MHz~10GHz• Phase velocity variation < 1%

• Attenuation variation < 5%

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V. Implementation

• Add shunt conductance between differential wires

• Resistors realized by serpentine unsilicided poly, diffusion resistors, or high resistive metal

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V. Implementation• Configuration of wires

• Characteristic Impedance (at 10GHz) : 39.915 Ohm

• Inductance: 0.22nH/mm Capacitance: 141fF/mm

• Attenuation: 253mv magnitude at receiver’s end (assuming 1V at sender’s end)

• Using Microstrip (free space above the wires): impedance can be improved to 52.8Ohm

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V. Simulation

• Agilent ADS Momentum extract 4-port S-parameters

• HSpice: Transient analysis

• Assume 1023 bit pseudo random bit sequence (PRBS)

• 15GHz clock

• 10% of clock period transition slope for each rising and falling edge

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V. Simulation Results

4 Stages 120 Stages

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V. Simulation Results

Jitter and silicon area usage

#Stages 4 10 20 40 80 120 160

Jitter (ps) 27 9.5 5.4 4.2 3.9 2.1 2.08

Area (um2) 0.52 3.25 13.0 52 208 468 832

Power w/ different width and separation

(w, s) (um) (3,3) (4,4) (5,4) (10,5)

Power (mW) 4.98 3.62 3.02 2.13

Attenuation 0.307 0.415 0.496 0.60

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VI. Applications of Surfliner

1.Clock distributions

2. Data communications: Buses Between CPUs, DSPs, Memory Banks

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VI. Application of Surfliner

3. High Performance Low Power Wafer Packaging

IC IC IC

Distortionless On-Wafer Transmission Lines for Data Communication and Clock Distributions

CoupledCapacitors

Differential Driver Sense-amps