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Transcript of 1 IF Receiver for Wideband Digitally Modulated Signals Direct Instructor: Doctor Ronen Holtzman,...
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IF Receiver for Wideband Digitally Modulated Signals
Direct Instructor: Doctor Ronen Holtzman, Microwave Division, Elisra Electronic Systems Ltd.
Supervising Instructor: Professor Raphael Kastner, Department of Physical Electronics, School of Electrical Engineering, Tel Aviv University
Oren Avraham
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Presentation Outline
Objectives Requirements Block Diagrams Processing Features Research and Reading Subjects Results and Conclusions
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Primary Objectives I. Design a receiver for wideband digitally modulated signals:
Analog processing: full circuit design Digital processing: algorithm principles Software definition (including Gain and NF evaluation for BIT)
II. Perform the required research and literary reading on various aspects of the analog and digital processing to assure minimal degradation in signal quality, among which are the following: Analog to Digital Converters and their proper use in the
integrated system. Calculation of Sampling Clock Aperture Jitter and its effect on
ADC SNR.
III. Realize and test a working PCB using SMT components, which performs the analog processing section.
![Page 4: 1 IF Receiver for Wideband Digitally Modulated Signals Direct Instructor: Doctor Ronen Holtzman, Microwave Division, Elisra Electronic Systems Ltd. Supervising.](https://reader030.fdocuments.in/reader030/viewer/2022032723/56649cff5503460f949d1335/html5/thumbnails/4.jpg)
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System Block Diagram
IF Input
IF Section
(Analog Processing)
FPGAs
(Digital Processing)
Analog to Digital Converter
Optical Digital Output
OpticTransceiver
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Main Requirements Input / Output Frequencies:
70 MHz140 MHz
4 Selectable Bandwidths per Center Frequency SNR degradation (IF Cascade & ADC): 0.1 dB, maximum Maximal Dynamic Range @ 100 KHz Resolution :
2nd Order: 70 dB, minimum3rd Order: 70 dB, minimum
Gain Control Dynamic Range:AGC: 30 dBMGC: 30 dB
Output Power Level: Should be chosen to best utilize the ADC’s Dynamic Range.
![Page 6: 1 IF Receiver for Wideband Digitally Modulated Signals Direct Instructor: Doctor Ronen Holtzman, Microwave Division, Elisra Electronic Systems Ltd. Supervising.](https://reader030.fdocuments.in/reader030/viewer/2022032723/56649cff5503460f949d1335/html5/thumbnails/6.jpg)
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Analog Processing: Block Diagram
IF Input
ByPass
Control
MonitorOutput
IFOutput
OpAmp
D/A
Integrator
μCA/D
DCA
IFDET
μCA/D
Noise Generator
70/5
70/10
70/28
70/40
140/10
140/20
140/56
140/40
140/56
Thermopad
20 dB
AGC/MGC
Anti Aliasing Filter
Pre Selector Filter bank
AGCFeedback
HMC484
HMC253
RF2360
AD8309
LPF 90
20 dB
20 dB
IFDET
AD8309
Power Overload Detection
μCA/D
Comp
Control
Threshold
Thermopad/ATT
VVA
RVA2500
AT-117
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Automatic Gain Control Manual Gain Control Sub-Octave Filtration Anti-Aliasing Filtration Noise Injection for BIT Purposes
Analog Processing: Main Features
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AGC/MGC (1): Circuit
VVAControlVoltage
20 dB CouplerAGC
IF InputVVA
RVA2500
IFDetector
(AD8309)
AGCIF Output
OperationalAmplifier RSSI
C
R
-
+
D/A
PC (Control Software)
μCA/D
MGC/Digital AGC
Analog AGC
μCA/D
Target
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AGC/MGC (2): IF Detector
-40 -35 -30 -25 -20 -15 -10 -5 0 5
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
Log Amp RSSI Versus IF Signal Power at Cascade OutputR
SS
I [V
olt]
Output Power [dBm]
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AGC/MGC (3): VVA
0 2 4 6 8 10 12 140
10
20
30
40
50
60
70VVA Attenuation Versus Control Voltage
Atte
nuat
ion
[dB
]
Control Voltage [Volt]
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Performed by the Pre-Selector Filter Bank Improves the effective IP2 by at least 20 dB Composed of Eight Band Pass Filters:
1. 70/5 MHz2. 70/10 MHz3. 70/28 MHz4. 70/40 MHz5. 140/10 MHz6. 140/20 MHz7. 140/40 MHz8. 140/56 MHz
A Bypass channel is included for scenarios in which an extremely low Group Delay Variation is required.
Sub-Octave Filtration
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Performed by two filters:1. LPF 90 MHz2. BPF 140/56 MHz
Designed for a Sampling Frequency of 196.608 MHz (48th multiple of an E1 rate).
Replica Rejection for worst case scenario:1. LPF 90 MHz: 70 dBc2. BPF 140/56 MHz: 55 dBc
Anti-Aliasing Filtration
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A Noise Generator (ENR=30 dB) is used for Noise Injection ADC Samples are used as observations and two noise power
levels are computed:1. N1 – Natural Thermal Noise at Cascade Input (-174 dBm/Hz)2. N2 – Generator Noise at Cascade Input (-144 dBm/Hz)
Using the following equations the IF cascade’s Gain and Noise Figure are evaluated:
The test scans all signal channels and produces a Pass/Fail report.
Built In Test
1
][
][log10][
1
2
WN
WNENRdBNF
BkTT
WNWNdBG
oh )(
][][log10][ 12
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Digital Processing: Block Diagram
12-bit ADC@ 196.608 MHz
Distributed Arithmetic
FIRs
NCO
↓D
IQ Conversion Downsampling
Anti-sinc Filter
Decimation
X2 FrequencyMultiplier
98.304 MHzReference Clock
1st FPGA
IF CascadeOutput
P/S Optic TX/RXRocketIOInterface
2nd FPGA
ReceiverOutput
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Simplified View of Sampled Spectrum
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 1900
0.2
0.4
0.6
0.8
1
Sampled Spectrum for a 70/40 MHz Analog Input Signal (shown for 0<f<fs)
Frequency [MHz]
Magnitu
de
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 1900
0.2
0.4
0.6
0.8
1
Sampled Spectrum for a 140/56 MHz Analog Input Signal (shown for 0<f<fs)
Frequency [MHz]
Magnitu
de
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Research and Literary Reading Subjects:ADC-Related System Design Considerations
The complete Receiver functions as an Integrated Analog-Digital System.
A thorough understanding of the ADC’s effects on the integrated system’s performance is required.
This is performed by characterizing the ADC in “RF/IF terms” and designing the IF cascade accordingly.
One of the main questions which arise is the following:
What is the optimal power of theanalog signal at the ADC’s input?
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It is a wide spread notion that in order to best utilize the ADC’s Dynamic Range (bits), the analog signal’s power at the ADC’s input should be as high as possible, putting it very close to Full Scale Power (FSP).
This yields very demanding Gain and Linearity requirements of the RF cascade preceding the ADC, and causes an inevitable degradation of signal integrity (higher gain means higher intermodulation products, harmonics, likelihood of compression and so forth).
Furthermore, the risk of ADC clipping (when the analog signal power exceeds its FSP) runs very high.
Input Power to ADC – Introduction (1)
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Our hypothesis is that it is not the analog signal’s power but rather the amplified Thermal Noise of the RF/IF cascade at the ADC’s input which determines the degradation in system noise performance caused by the ADC.
This is based on the fact that ADC noise (Thermal, Quantization and Jitter Induced) can be referred to as white noise.
This white noise is added to the amplified thermal noise (which is white is as well) at the ADC’s input.
Since both noises are white and statistically independent, the result is their power summation.
Therefore, we can calculate the ADC’s Effective Noise Figure.
Input Power to ADC – Introduction (2)
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Input Power to ADC: ADC Effective NF
ADC FSP [dBm]Typically 1 dB below FSP [-1 dBFS]
SNR (Integrated Over Entire Nyquist Bandwidth) [dB]
2log10 samplingf
Thermal Noise Density
)kTB=-174 dBm/Hz(
ADC Effective NF [dB]
ADC Noise Density [dBm/Hz]
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In order to perform the power summation of Thermal Noise and ADC Noise in a more intuitive manner, we use the Over Gain approximation:
Input Power to ADC – OG (1)
Natural Thermal Noise: -174 dBm/Hz
Amplified Thermal
Noise: NRF/IF
ADC Noise: NADC
RF/IF Cascade
GRF/IF
NFRF/IF
ADC
NFADC
Combined
Noise
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The different Noise Power Levels are:
ADCIFRFCombined NNN /
OG Summation
Amplified Thermal Noise: NRF/IF [dBm]
ADC Noise: NADC [dBm]
Combined Noise [dBm]
Over Gain (OG) [dB]
Δ(OG) [dB]
Δ(OG)[dB]
≈ |OG|
20.04
15.1
10.4
7
3
1
0.4
0.1
0.04
≈ 0
ADCADC NFN 174
ADCIFRFIFRFADCIFRF NFNFGNNdBOG ///][
OG[dB]
<-20
-20
-15
-10
-6
0
6
10
15
20
>20
IFRFIFRFIFRF NFGN /// 174
OGN IFRF /
Input Power to ADC – OG (2)
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Therefore, we can predict the ADC-Induced SNR Degradation based on the OG table.
We note that for an OG of more than 15 dB, this degradation is negligible.
From this, we would derive the Gain Requirement of the RF/IF Cascade (for a given NF):
We verified our hypothesis by simulation, as presented in the following slides.
Input Power to ADC – OG (3)OG[dB]
SNR Degradation
[dB]
<-20≈ |OG|
-2020.04
-1515.1
-1010.4
-67
03
61
100.4
150.1
200.04
>20≈ 0
IFRFADCIFRF NFNFG // 15
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High OG (20 dB), -50 dBFS Input Sine Wave:
Input Power to ADC – Simulation (1)
0 10 20 30 40-150
-100
-50
0
Frequency [MHz]
Mag
nitu
de [d
BF
S]
Analog Signal at ADC Input
Analog SignalADC Noise Floor
0 10 20 30 40-150
-100
-50
0
Frequency [MHz]
Mag
nitu
de [d
BF
S]
Digitized Signal at ADC Output
0 5 10 15 20 25 30 35 40 45-150
-100
-50
0
Frequency [MHz]
Mag
nitu
de [d
BF
S]
ADC Simulation (Single Plot)
Analog Signal at ADC InputDigitized Signal at ADC Output
![Page 24: 1 IF Receiver for Wideband Digitally Modulated Signals Direct Instructor: Doctor Ronen Holtzman, Microwave Division, Elisra Electronic Systems Ltd. Supervising.](https://reader030.fdocuments.in/reader030/viewer/2022032723/56649cff5503460f949d1335/html5/thumbnails/24.jpg)
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Low OG (-10 dB), -1 dBFS Input Sine Wave:
Input Power to ADC – Simulation (2)
0 10 20 30 40
-150
-100
-50
0
Frequency [MHz]
Mag
nitu
de [d
BF
S]
Analog Signal at ADC Input
Analog SignalADC Noise Floor
0 10 20 30 40
-150
-100
-50
0
Frequency [MHz]
Mag
nitu
de [d
BF
S]
Digitized Signal at ADC Output
0 5 10 15 20 25 30 35 40 45
-150
-100
-50
0
Frequency [MHz]
Mag
nitu
de [d
BF
S]
ADC Simulation (Single Plot)
Analog Signal at ADC InputDigitized Signal at ADC Output
![Page 25: 1 IF Receiver for Wideband Digitally Modulated Signals Direct Instructor: Doctor Ronen Holtzman, Microwave Division, Elisra Electronic Systems Ltd. Supervising.](https://reader030.fdocuments.in/reader030/viewer/2022032723/56649cff5503460f949d1335/html5/thumbnails/25.jpg)
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High OG (15 dB), -90 dBFS Input Sine Wave:
Input Power to ADC – Simulation (3)
0 10 20 30 40
-150
-100
-50
0
Frequency [MHz]
Mag
nitu
de [d
BF
S]
Analog Signal at ADC Input
Analog SignalADC Noise Floor
0 10 20 30 40
-150
-100
-50
0
Frequency [MHz]
Mag
nitu
de [d
BF
S]
Digitized Signal at ADC Output
0 5 10 15 20 25 30 35 40 45
-150
-100
-50
0
Frequency [MHz]
Mag
nitu
de [d
BF
S]
ADC Simulation (Single Plot)
Analog Signal at ADC InputDigitized Signal at ADC Output
![Page 26: 1 IF Receiver for Wideband Digitally Modulated Signals Direct Instructor: Doctor Ronen Holtzman, Microwave Division, Elisra Electronic Systems Ltd. Supervising.](https://reader030.fdocuments.in/reader030/viewer/2022032723/56649cff5503460f949d1335/html5/thumbnails/26.jpg)
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OG Sweep (-30 dB to +30 dB), showing that our hypothesis coincides with the simulation results:
Input Power to ADC – Simulation (4)
-30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30
0
5
10
15
20
25
30
SN
R D
eg
rad
atio
n [d
B]
Over Gain [dB]
SNR Degradation Caused by the ADC Versus Over Gain
TheoreticSimulation
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IP3 is the 3rd order Intercept Point, which corresponds to the 3rd order Intermodulation Products of a non-linear analog (RF) component.
One of the ADC’s non-linearity parameters is the “Two-Tone Intermodulation Distortion Rejection” (IMDR).
We “translate” the ADC’s IMDR to RF/IF terms (IP3) using the following relation:
ADC: Effective IP3
][][][
][2
1][][3
dBmFSPdBFSPdBmP
dBIMDRdBmPdBmIP
inin
inADC
![Page 28: 1 IF Receiver for Wideband Digitally Modulated Signals Direct Instructor: Doctor Ronen Holtzman, Microwave Division, Elisra Electronic Systems Ltd. Supervising.](https://reader030.fdocuments.in/reader030/viewer/2022032723/56649cff5503460f949d1335/html5/thumbnails/28.jpg)
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2
,2
2
2
2
2
1
3
22log20
N
rmsTh
NrmssignalADC
VfSNR
Effect of Sampling Clock Aperture Jitter on ADC SNR
The Effective SNR of an ADC is comprised of several noise sources:
Analog Signal
Frequency
RMS Aperture Jitter of Sampling Clock
ADC Resolution (Number of bits)
ADC DNL (Differential
Non Linearity)Thermal Noise
in LSBs
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The common approach to calculate the RMS Aperture Jitter of a frequency source (such as a sampling clock) is to integrate its Phase Noise as is, and simply translate the result (received in radians) to temporal terms (seconds):
Calculation of Sampling Clock RMS Aperture Jitter (1)
sf
srms dffL
f 0
2
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Oscillator
(Center)
Frequency
Frequency Offset
From Center FrequencyOscillator Phase Noise
(After BPF)
sf
ssrms df
f
ffL
f 0
2
2sin
2
We apply a more modern approach which incorporates a sine function factor, as follows:
Calculation of Sampling Clock RMS Aperture Jitter (2)
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10-8
10-7
10-6
10-5
10-4
10-3
10-2
10-1
100
-150
-100
-50
0
Normalized Frequency Offset (f/fo)
Att
en
ua
tio
n [
dB
]
sin(/2f/f0)2
The sine factor attenuates the Phase Noise close to the oscillator center frequency, as depicted in the following figure:
Calculation of Sampling Clock RMS Aperture Jitter (3)
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3250 100 150 200
Frequency (MHz)
Filter Response
-80
-60
-40
-20
0
Center Frequency (fs=98.304 MHz)
2fs
At frequencies that are far from the center, the Phase Noise is attenuated by the Clock’s BPF:
Calculation of Sampling Clock RMS Aperture Jitter (4)
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Calculation of Sampling Clock RMS Aperture Jitter (5)
100
101
102
103
104
105
106
107
-160
-140
-120
-100
-80
-60
Phase Noise
Frequency Offset [Hz]
Ma
gn
itud
e [d
Bc/
Hz]
Before BPFAfter BPF
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Results (1): At 70 MHz
ParameterRequirement
Measurement
2nd Amp Enabled2nd Amp Disabled
Noise Figure, maximum [dB]9.55.28.5
Expected SNR Degradation, maximum [dB]
0.1<10-30.085
DR2 @ 100 KHz
BW, minimum [dB]7076.985.25
DR3 @ 100 KHz
BW, minimum [dB]7072.284
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Results (2): At 140 MHz
ParameterRequirement
Measurement
2nd Amp Enabled
2nd Amp Disabled
Noise Figure, maximum [dB]9.55.59
Expected SNR Degradation, maximum [dB]
0.1<10-30.095
DR2 @ 100 KHz
BW, minimum [dB]707785.25
DR3 @ 100 KHz
BW, minimum [dB]707283.65
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Conclusions I. The Subject of ADC Integration with RF/IF Cascades
was explored, reaching the following conclusions: The ADC-Induced SNR Degradation is determined by
the level of thermal noise at the ADC’s input. Even sub-LSB signals can be detected by the ADC. The Over Gain approximation proved to be a good
method to determine the required Gain of the RF/IF cascade and predict the SNR Degradation.
II. The Analog (IF) section of the receiver was designed, built and measured showing electrical performance surpassing the requirements.