1 H ardware D escription L anguages Modeling Complex Systems.
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Transcript of 1 H ardware D escription L anguages Modeling Complex Systems.
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HardwareDescriptionLanguages
Modeling Complex Systems
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Outline (Raising the Abstraction Level)
The Process Statement if-then, if-then-else, if-then-elsif, case, while, forSensitivity listSignals vs. Variables BehaviorConcurrent processes
The Wait statement wait until, wait for, wait on, wait
Attributes
Modeling State Machines
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Raising the Level of Abstraction
R W
Data input
Data Output
Address
Memory Module
add R1, R2, R3
sub R3, R4, R5move R7, R3
...Instruction Set Simulation
CSA statements can easily capture the gate level behavior of digital systems But, higher level digital components have complex behaviors
Input/output behavior is not easy to describe at gate levelModels may utilize state information Incorporate data structures
We need more powerful constructs !!!
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Extending the Event Computation Model
Combinational logic input/output semanticsEvents on inputs causes re-computationRe-computation may lead to events on outputs
Computation of the value and time of output events can be a complex process
Description of a Complex Process
Sig1 <= …..Sig2 <= …...
Input signals Output signals
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library IEEE;use IEEE.std_logic_1164.all;entity mux4 isport (in0, in1, in2, in3: in std_logic_vector(7 downto 0);
sel: in std_logic_vector(1 downto 0); z : out std_logic_vector(7 downto 0));
end entity mux4;
architecture behavioral of mux4 is
process (sel, in0, in1, in2, in3) isvariable zout: std_logic;begin
if (Sel = “00”) then zout := in0;elsif (Sel = “01”) then Zout := in1;elsif (Sel = “10”) then Zout := in2;else Zout:= in3;end if;z <= zout;
end process;
end architecture behavioral;
The Process Statement
Use of variables rather than signals
Variable Assignment
Sensitivity List
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Process Statement Mechanisms
Statements in a process are executed sequentially
A process body is structured much like conventional C functionDeclaration and use of variables if-then, if-then-else, case, for and while constructsA process can contain signal assignment statements
A process executes concurrently with other processes and other CSA statements.
A process takes 0 seconds of simulated time to execute and may schedule events on signals in the future
We can think of a process as a “big” CSA statement !
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Using Concurrent Processes: Full Adder Example
Each of the components of the full adder can be modeled using a process
Processes execute concurrently Processes communicate via signals
Half Adder
Half Adder
In1
In2
c_in
s1
s3
s2
sum
c_out
portModel using processes
Internal signal
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Using Concurrent Processes: Full Adder Example
library IEEE;use IEEE.std_logic_1164.all;
entity full_adder isport (in1, c_in, in2: in std_logic; sum, c_out : out std_logic);end entity full_adder;
architecture beh of full_adder issignal s1, s2, s3: std_logic;begin
HA1: process (in1, in2) isbegins1 <= (In1 xor In2);s3 <= (In1 and In2);end process HA1;
HA2: process(s1,c_in) isbeginsum <= (s1 xor c_in);s2 <= (s1 and c_in);end process HA2;
OR1: process (s2, s3) is-- process describing the -- two-input OR gatebeginc_out <= (s2 or s3);end process OR1;
end architecture beh;
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Using Concurrent Processes: Half Adder Example
library IEEE;use IEEE.std_logic_1164.all;
entity half_adder isport (a, b : in std_logic; sum, carry : out std_logic);end entity half_adder;
architecture behavior of half_adder isbegin
sum_proc: process(a,b) isbegin if (a = b) then sum <= ‘0’; else sum <= (a or b); end if;end process;
carry_proc: process (a,b) isbegin case a is when ‘0’ => carry <= a; when ‘1’ => carry <= b; when others => carry <= ‘X’; end case;end process carry_proc;
end architecture behavior;
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Processes + CSAs: Example
library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;
entity memory isport (address, write_data: in std_logic_vector (7 downto 0); MemWrite, MemRead, clk, reset: in std_logic; read_data: out std_logic_vector (7 downto 0));end entity memory;
architecture behavioral of memory issignal dmem0,dmem1,dmem2,dmem3: std_logic_vector (7 downto 0);beginmem_proc: process (rising_edge(clk)) is-- code process body hereend process mem_proc;-- code read operation CSA hereend architecture behavioral;
MemRead MemWrite
address
write_data
read_data
clk reset
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Process + CSAs: The MemWrite Process
mem_proc: process (clk) isbeginif (rising_edge(clk)) then -- wait until next clock edge if reset = ‘1’ then -- initialize values on reset dmem0 <= x”00”; -- memory locations are initialized to dmem1 <= x”11”; -- some random values dmem2 <= x”22”; dmem3 <= x”33”; elsif MemWrite = ‘1’ then -- if not reset then check for memory write case address (1 downto 0) is when “00” => dmem0 <= write_data; when “01” => dmem1 <= write_data; when “10” => dmem2 <= write_data; when “11” => dmem3 <= write_data; when others => dmem0 <= x“ff”; end case; end if;end if;end process mem_proc;
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Process + CSAs: The MemRead Statement
A process can be viewed as single CSA statementThe external behavior is the same as a CSAProcesses describe more complex event generation
behavior Processes execute concurrently with other CSAs
-- memory read is implemented with a conditional signal assignmentread_data <= dmem0 when address (1 downto 0) = “00” and MemRead = ‘1’ elsedmem1 when address (1 downto 0) = “01” and MemRead = ‘1’ elsedmem2 when address (1 downto 0) = “10” and MemRead = ‘1’ elsedmem3 when address (1 downto 0) = “11” and MemRead = ‘1’ elsex”00”;
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Iteration statements
There are two iterations statements:For loopWhile loop
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The For Loop Statement
for - loopThe index is implicitly declared
• Scope is local to the loop• If a variable or signal with the same name is
used elsewhere in the process or architecture (but not in the same loop) it is treated as a distinct object
for index in 1 to 32 loop...end loop;
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The While Loop Statement
while loopBoolean expression for termination
while j < 32 loop
...
...
j := j+1;
end loop;
NOT SYNTHESIZABLE !!
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More on Processes Behavior …
All processes are executed once at start-up After start-up only dependencies between signal values and
events on these signals determine process execution Signals behave differently from variables !
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Using Signals in a Process
Entity signals are visible in a process Processes can encapsulate variable and signal
assignment statements What is the difference on the model behavior
between dataflow (CSAs) and process models ?
In1
In2
z
s1
s2
s3
s4
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Mis-using Signals in a Process
library IEEE;use IEEE.std_logic_1164.all;entity combo isport (In1, In2 : in std_logic; z: out std_logic);end entity combo;
architecture beh of combo issignal s1, s2, s3, s4: std_logic;begins1 <= not In1;s2 <= not In2;s3 <= not (s1 and In2);s4 <= not (s2 and In1);z <= not (s3 and s4);end architecture beh;
library IEEE;use IEEE.std_logic_1164.all;entity combo isport (In1, In2: in std_logic; z : out std_logic);end entity combo;
architecture beh of combo issignal s1, s2, s3, s4: std_logic;beginsig_in_proc: process (In1, In2) is begins1 <= not In1;s2 <= not In2;s3 <= not (s1 and In2);s4 <= not (s2 and In1);z <= not (s3 and s4);end process sig_in_proc;end architecture beh;
Encapsulate in a process
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Mis-using Signals in a Process (cont.)
IN1
IN2
Z
S1
S2
S3
S4
10 20 30 40 50 60 70
IN1
IN2
Z
S1
S2
S3
S4
10 20 30 40 50 60 70
Using CSA statements Using signal assignment statements within a process
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Signals vs. Variables
library IEEE;use IEEE.std_logic_1164.all;entity combo isport (In1, In2: in std_logic; z : out std_logic);end entity combo;
architecture beh of combo isvariable s1, s2, s3, s4: std_logic;beginsig_in_proc: process (In1, In2) is begins1 := not In1;s2 := not In2;s3 := not (s1 and In2);s4 := not (s2 and In1);z <= not (s3 and s4);end process sig_in_proc;end architecture beh;
Use variables for computingintermediate values
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Signals vs. Variables
-- Process 1 – Correct Coding Styleproc1: process (x, y, z) isvariable var_s1, var_s2: std_logic;beginvar_s1 := x and y;var_s2 := var_s1 xor z;res1 <= var_s1 nand var_s2;end process;
Process 2 – Incorrect proc2: process (x, y, z) isbeginsig_s1 <= x and y;sig_s2 <= sig_s1 xor z;res2 <= sig_s1 nand sig_s2;end process;
variablessignals
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The Wait Statement
Signal Assignments suspend execution until the next event on a signal on the RHS of the assignment statement
This behavior fit in well with the behavior of combinational circuits, in which a change on the input signals may cause a change in the value of the output signal
What about modeling circuits for which the outputs are computed only at specific point in time, independently of event on the inputs ?
We need a more general manner to specify the condition under which the circuit outputs must be recomputed !
This capability is provided by the wait statement
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The Wait Statement
The wait statement explicitly specifies the conditions under which a process may resume execution after being suspendend.
There are four forms of wait statements:wait for time-expressionwait on signalwaitwait until condition
NON SYNTHESIZABLE !!
SYNTHESIZABLE !!
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The Wait Statement: Waveform Generation
reset
phi1
phi2
10 20 30 40 50 60Time (ns)
events specifiedby the resetand clock processes
library IEEE;use IEEE.std_logic_1164.all;entity two_phase isport(phi1, phi2, reset: out std_logic);end entity two_phase;
architecture behavioral of two_phase isbeginrproc: reset <= ‘1’, ‘0’ after 10 ns;
clock_process: process isbeginphi1 <= ‘1’, ‘0’ after 10 ns;phi2 <= ‘0’, ‘1’ after 12 ns, ‘0’ after 18 ns;wait for 20 ns;end process clock_process;
end architecture behavioral;
Note the “perpetual” behavior of processes
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Example of Positive Edge-Triggered DFF using the Wait Statement
library IEEE;use IEEE.std_logic_1164.all;entity dff isport (D, Clk : in std_logic;Q, Qbar : out std_logic);end entity dff;architecture behavioral of dff isbeginoutput: process isbeginwait until (Clk’event and Clk = ‘1’); -- wait for rising edgeQ <= D; -- guideline: use the functionQbar <= not D; -- rising_edge(Clk)end process output;end architecture behavioral;
signifies a value change on signal clk
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Example of DFF with Synchronous inputs using the Wait Statement
library IEEE;use IEEE.std_logic_1164.all;entity synchdff isport (R, S, D, Clk : in std_logic;Q, Qbar : out std_logic);end entity synchdff;architecture behavioral of synchdff isbeginoutput: process isbeginwait until (Clk’event and Clk = ‘1’); -- wait for rising edge if R = ‘1’ then -- check for reset and initialize state Q <= ‘0’; Qbar <= ‘1’; elsif S=‘1’ then -- check for set and initialize Q <= ‘1’; Qbar <= ‘0’; else Q <= D; Qbar <= not(D); end if;end process output;end behavioral;
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Example of DFF with Asynchronous inputs using the Wait Statement
library IEEE;use IEEE.std_logic_1164.all;entity asynchdff isport (R, S, D, Clk : in std_logic; Q, Qbar : out std_logic);end entity asynchdff;
architecture behavioral of asynchdff isbeginoutput: process isbeginwait until (R = '1' or S='1' or (clk'event and clk ='1')); if (R='1') then Q <= '0'; Qbar <= '1';elsif (S='1') then Q <= '1'; Qbar <= '0';else -- wait for rising edge Q <= D; Qbar <= not(D);end if; end process output;end behavioral;
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How to avoid the use of Wait Statements: example of Positive Edge Triggered DFF
library IEEE; use IEEE.std_logic_1164.all;entity dff isport (D, Clk: in std_logic; Q, Qbar: out std_logic);end entity dff;
architecture behavioral of dff isbeginoutput: process (Clk) isbeginif (rising_edge(Clk)) then Q <= D; Qbar <= (not D);end if;end process output;end architecture behavioral;
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How to avoid the use of Wait Statements: example of DFF with Synchronous Inputs
library IEEE; use IEEE.std_logic_1164.all;entity synch_dff isport (R, S, D, Clk: in std_logic; Q, Qbar: out std_logic);end entity synch_dff;
architecture behavioral of synch_dff isbeginoutput: process (Clk) isbeginif (rising_edge(Clk)) then if (R = ‘0’) then Q <= ‘0; Qbar <= ‘1’; elsif S = ‘0’ then Q <= ‘1’; Qbar <= ‘0’; else Q <= D; Qbar <= (not D); end if;end if;end process output;end architecture behavioral;
implied ordering providesasynchronous setreset
execute on event on any signal
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How to avoid the use of Wait Statements: example of DFF with Asynchronous Inputs
library IEEE; use IEEE.std_logic_1164.all;entity asynch_dff isport (R, S, D, Clk: in std_logic; Q, Qbar: out std_logic);end entity asynch_dff;
architecture behavioral of asynch_dff isbeginoutput: process (R, S, Clk) isbeginif (R = ‘0’) then Q <= ‘0; Qbar <= ‘1’;elsif S = ‘0’ then Q <= ‘1’; Qbar <= ‘0’;elsif (rising_edge(Clk)) then Q <= D; Qbar <= (not D);end if;end process output;end architecture behavioral;
implied ordering providesasynchronous setreset
execute on event on any signal
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In Summary: The Wait Statement …
Wait statements provide explicit control over suspension and resumption of processes and can be used to represent both synchronous and asynchronous events
A process can have multiple wait statements
A process cannot have both a wait statement and a sensitivity list (it should have one or the other): Why?
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Wait Statements style vs. Sensitivity List style
Guideline: Do not use wait statements, use the sensitivity list Using wait statements, logic associated with each clock has to be
described in a different process, and synchronous logic has to be separated from combinational logic.
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In Summary: The Process Statement …
A process statement is a concurrent statement, but all statements contained in it are sequential statement (statements that executes serially, one after another).
The use of processes allows to raise the level of abstraction (support advanced language constructs) usable, makes your code more modular, more readable, and allows you to separate combinational logic from sequential logic.
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In Summary: The sensitivity list …
List of all signals that the process is sensitive to. Sensitive means that a change in the value of these signals will cause the process to be invoked.
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For Combinational Logic:the sensitivity list must be complete !!!
process (a)variable a_or_b;begin a_or_b := a or b; z <= a_or_b;end process;
-- since b is not in the-- sensitivity list, when-- a change occurs on b-- the process is not-- invoked, so the value-- of z is not updated-- (still “remembering”
the -- old value of z)
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Combinational Logic:incomplete sensitivity list effect
a
b
z (VHDL)
z (gate level)
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For Combinational Logic:What to put in sensitivity list ?
All signals you do a test on and all signals that are on the right side of an assignment.
In other words all the signals you are “reading” in the value
Don’t read and write a signal at the same time !!!
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Bad coding example: delta time issues !!!
architecture bad of logic is signal a_or_b : std_logic; begin logic_p: process(a,b,c) begin a_or_b <= a or b; z <= a_or_b and c; end process;end bad;
Do not “read” and “write” a signal at the same time !!!
write
read
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How to fix the bad coding example
architecture good of logic is variable a_or_b : std_logic; begin logic_p: process(a,b,c) begin a_or_b := a or b; z <= a_or_b and c; end process;end good;
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Predefined Attributes Value attributes
returns a constant value Function attributes
invokes a function that returns a value Signal attributes
creates a new signal Type Attributes
Supports queries about the type of VHDL objects(Advanced Topic: Let’s procrastinate for now )
Range attributes returns a range
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Value Attributes Return a constant value Examples:
type state_type is (state0, state1, state2, state3);state_type’left = state0state_type’right = state3
Value attribute Value
type_name’left returns the leftmost value of type_name
type_name’right returns the rightmost value of type_name
type_name’high returns the largest value of type_name
type_name’low returns the smallest value of type_name
array_name’length returns the number of elements in array_name
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More examples on value attributes
…
…
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More examples on value attributes (cont.)…
…
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Function Attributes
Function attributes invoke a function call which returns a value Examples:if (Clk’event and Clk = ‘1’)
Function attribute Function
signal_name’event Return a Boolean value signifying a change in value on this signal
signal_name’active Return a Boolean value signifying an assignment made to this signal. This assignment may not be a new value.
signal_name’last_event Return the time since the last event on this signal
signal_name’last_active Return the time since the signal was last active
signal_name’last_value Return the previous value of this signal
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Function Attributes (cont.)
Examples of function array attributesFunction attribute Function
array_name’left returns the left bound of the index range
array_name’right returns the right bound of the index range
array_name’high returns the upper bound of the index range
array_name’low returns the lower bound of the index range
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Range Attributes
for i in value_array’range loop...my_var := value_array(i);...end loop;
• Returns the index range of a constrained array
…
…
…
variable wbus: std_logic_vector(7 downto 0);
…signal xbus: std_logic_vector(wbus’range);
…
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Signal Attributes
• Creates a new “implicit” signal
Signal attribute Implicit Signal
signal_name’delayed(T) Signal delayed by T units of time
signal_name’transaction Signal whose value toggles when signal_name is active
signal_name’quiet(T) True when signal_name has been quiet for T units of time
signal_name’stable(T) True when event has not occurred on signal_name for T units of time
Internal signals are useful modeling tools
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Signal Attributes: Examplearchitecture behavioral of attributes isbegin outdelayed <= data'delayed(5 ns); outtransaction <= data'transaction;end attributes;
These are real (in simulation) signals and can be used elsewhere in the model
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Modeling State Machines
Combinational
logicInputsOutputs
State
Clk
Next state
s0 s1 0/11/0
0/1
1/0
Basic components Combinational component: output function and next state
functionSequential component
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Example: State Machine
library IEEE;use IEEE.std_logic_1164.all;
entity state_machine isport(reset, clk, x : in std_logic;z : out std_logic);end entity state_machine;
architecture rtl of state_machine istype statetype is (state0, state1);signal state, next_state : statetype;begin
comb_process: process (state, x) isbegin-- process description hereend process comb_process;
clk_process: process (clk, reset) isbegin-- process description hereend process clk_process;
end architecture rtl;
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Example: Output and Next State Functions
Combination of the next state and output functions
comb_process: process (state, x) isbegin case state is -- depending upon the current state when state0 => -- set output signals and next state if x = ‘0’ then next_state <= state1; z <= ‘1’; else next_state <= state0; z <= ‘0’; end if; when state1 => if x = ‘1’ then next_state <= state0; z <= ‘0’; else next_state <= state1; z <= ‘1’; end if; when others => -- nothing end case;end process comb_process;
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Example: Clock Process
Use of asynchronous reset to initialize into a known state
clk_process: process (clk, reset) isbeginif reset = ‘1’ then -- check for reset and initialize state state <= statetype’left;elsif (rising_edge(clk)) state <= next_state;end if;end process clk_process;
end architecture rtl;
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Summary
Processes variables and sequential signal statements if-then, if-then-else, if-then-elsif, case, while, for concurrent processes sensitivity list
The Wait statement wait until, wait for, wait on, wait
Attributes
Modeling State machines