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Expanded Modes, Bus, Expanded Modes, Bus, External MemoryExternal Memory

Today:• First Hour: Expanded Modes, Bus, Timing–Section 4.1-4.7.2 of Huang’s Textbook– In-class Activity #1

• Second Hour: Interfacing external memory to 6811• Section 4.7.3 of Huang’s Textbook– In-class Activity #2

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Single chip mode: a mode in which the 68HC11 functions without external address and data buses. • The 68HC11 has 5 I/O ports (A, B, C, D, and E) to use in this mode.

Expanded mode: a mode in which the 68HC11 has the capability to access a 64KB address space. • Port B is used as the upper address signals (A15-A8) • Port C is used as time-multiplexed address/data bus (A7/D7-A0/D0). • Only three I/O ports are available for direct use.

Choosing modes:• MODB, MODA pins (look up PRG!)• (1,0) => single chip; (1,1) => Expanded

6811Operation Modes6811Operation Modes

3

ROM-8KB

RAM-256 bytes

EEPROM-512 bytes

PORTA

PULSE ACCUMULATOR

PERIODIC INTERRUPT

COP WATCHDOG

PAIOC2OC3OC4OC5

OC1

IC1IC2IC3

PA7PA6PA5PA4PA3PA2PA1PA0

PE7PE6PE5PE4PE3PE2PE1PE0

PORTE

VREFH

VREFL

A/DCONVERTER

DA

TA D

IREC

TIO

N

PORTD

SSSCK

MOSIMISO

SPI

TxD

RxDSCI

PD5PD4PD3PD2

PD1

PD0

M68HC11 CPU

ADDRESS DATA BUS

INTERRUPTS

RESET

XIRQ

IRQ(VPPBULK) HANDSHAKE I/O

DATA DIRECTION C

PORT CPORT BPARALLEL

I/O

SINGLECHIP

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

STRA

STRB

A15

A14

A13

A12

A11

A10

A9

A8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

R/W ASEXPAND

OSCILLATORXTAL

EXTAL

E

MODALIR

MODB(VSTBY )

VDD

VSS

MODESELECT

POWER

Expanded ModeExpanded Mode

4

ER/W

AS

AD7-AD0

68HC11

PC7-PC0

A15-A8PB7-PB0

MODB

MODA

Bus

Expanded ModeExpanded Mode11

Other pins not shown

5

A real signal has nonzero rise and fall times

90% VDD

10% VDD

1

0

trise tfall

Timing Conventions RecapTiming Conventions Recap

Single-signal waveform

1

0

1

0

Multiple-signal waveform

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Unknown signals (when they are changing) representation

(a) Single signal

unknown

unknown

(b) multiple signals

Unknown signals

Timing Conventions RecapTiming Conventions Recap

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A floating signal is represented by a level half way between logic high and low.

Signalfloating

(a) Single signal

Signalsfloating

(b) multiple signals

Floating signals

Timing Conventions RecapTiming Conventions Recap

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Crystal & E-clockCrystal & E-clock

E

XTAL

Crystal clock: 8 MHz => One cycle = 125 ns

125 ns

E clock: 2 MHz => One cycle = 500 ns

500 ns

9

E

R/W

A15-A8

A7/D7-A0/D0 LO-ADDR DATA

AS

XTAL

Bus Timing DiagramBus Timing Diagram

HI ADDR

• Observe that AD lines active as address only for 1/2 E cycle• Most external memory devices need address lines active for 1E cycle• AS line to the rescue, combined with external address latch!

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CLK

OEABCDEFGH

QAQBQCQDQEQFQGQH

373

111

347813141718

256912151619

74373 Octal Transparent Latch 74373 Octal Transparent Latch with 3-State Outputswith 3-State Outputs

Stores an 8 bit number

Positive edge triggered

/OE is active LO output enable

Determines when register contents are visible at the

outputs

LE11

LE: Latch Enable. High => latch is transparent to data inputs

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Latching the AddressLatching the Address

ER/W

AS

AD7-AD0

68HC11

PC7-PC0

A15-A8PB7-PB0

MODBMODA

Bus

11

Other pins not shown

D0-D7

Q0-Q7

A0-A7

373LE

Address A0-A7 latched on the

falling edge of AS

OE0

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Latching (contd)Latching (contd)

• Latching allows A7-A0 to be available for the second half of the E-clock cycle at the output of the latch

E

AS

250 ns

125 ns

A0-A7 latched at falling AS

edge

A7/D7-A0/D0 LO-ADDR DATA

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Do Activity #1 NowDo Activity #1 Now

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• Memory mapping external memory => can access external memory using normal instructions and memory addresses.• Similar to I/O memory mapping

Address space assignment- Use only unallocated memory space - Allocated in units of 2n KB (n is an integer)

Allocated space for the 68HC11A8

$0000-$00FF: SRAM$1000-$103F: I/O registers$B600-B7FF: EEPROM$E000-$FFFF: ROM

Memory MappingMemory Mapping

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Memory Mapping ExampleMemory Mapping Example• Consider an external 13-bit memory chip => 8KB• Divide 64 KB space into eight 8KB blocks.

Block number Address range01234567

$0000-$1FFF$2000-$3FFF$4000-$5FFF$6000-$7FFF$8000-$9FFF$A000-$BFFF$C000-$DFFF$E000-$FFFF

Map external memory to: $4000-$5FFF

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Address DecodingAddress Decoding• First four bits of memory map: 0100 or 0101• Partial decoding: A[15-13] = 010

O0O1O2O3O4O5O6O7

E1

E2

E3

A2

A1

A0

74LS138

Address decoder design

A15

A14

A13

External MemoryE

010

Why is E connected

to E3 ?

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Decoding (contd)Decoding (contd)

• 74LS138: • E3: active high enable=> Decoding done when E clock is highI.e at second-half of E-clock cycle

• Goal: • Enable (chip select) external memory with the

output (O2) of decode at this time• I.e. at second-half of E-clock cycle

E

Decoded values available

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• Two chip enable signals: CS1 is active lowCS2 is active high.

• WE: write enable (active low)

• OE: output enable (active low)

NCA12A7A6A5A4A3A2A1A0

I/O1I/O2I/O3V SS

V CC

WECS2A8A9A11OEA10CS1I/O8I/O7I/O6I/O5I/O4

Figure 5.14 Hitachi HM6264A pin assignment

8KB SRAM HM6264A8KB SRAM HM6264A

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Putting it togetherPutting it togetherA2

A1

A0

E3

E2 E1

PB7/A15

PB6/A14

PB5/A13

E

R/WPB4/A12 - PB0/A8

AS

AD7-AD0

LE

D7-D0

O7-O0

OE

I/O8 - I/O1

WE

CS1 CS2

VDD

O2

A12-A0

OE

HM6264A

74F138

68HC11

74F373

74LS00

74LS04

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E

R/W

A15-A8

A7/D7-A0/D0 LO-ADDR DATA

AS

XTAL

Revisit: Bus Timing DiagramRevisit: Bus Timing Diagram

HI ADDR

Second half of E-cycle

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Putting it together (contd)Putting it together (contd)

• During second-half of E-cycle–CS1 asserted (from O2)–E =1 during this time => R/W’ passed to WE’»Recall: (X.1)’ = X’ {NAND gate}» In this case, X = (R/W’)’ {NOT gate}

– Latch output holds A0-A7–AD0-AD7 connected to I/O lines of SRAM»Data sent back to port C if it is a READ»Data sent from port C if it is a WRITE

E

Second half of E-cycle

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Do Activity #2 NowDo Activity #2 NowDue: End of Class Today.RETAIN THE LAST PAGE(S) (#3 onwards)!!

For Next Class:• Read Chapter 4 of Huang• Review all material, identify your problem areas,

and Bring your questions!• Next week’s studio: Catch up with experiments.

Summarize reading of Chapter 4, Chapter 5 (sections 5.1-5.4), and Chapter 6 (6.1 – 6.7)