1 Digital L2 Intro

7/28/2019 1 Digital L2 Intro

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VLSI Design MethodologyVLSI Design Methodology


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OutlinesOutlines

VLSI Design Flow and Structural DesignVLSI Design Flow and Structural Design

PrinciplesPrinciples

VLSI Design Styles

VLSI Desi n Strate ies

Nitin ChaturvediNitin Chaturvedi VLSI Design Methodology 2

Computer-Aided Design Technology for VLSI


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Design DomainsDesign Domains



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Simplified VLSI Design FlowsSimplified VLSI Design Flows

System Specification

Functional(Architecture) Design

Functional Verification

Circuit Design

Circuit Verification

BehavioralBehavioralRepresentationRepresentation

CircuitCircuitRepresentationRepresentation


Logic Design

Logic Verification

Physical Design

Physical Verification

Front EndFront End Back EndBack EndSynthesis PhaseSynthesis Phase Layout PhaseLayout Phase

LogicLogic(Gate(Gate--Level)Level)

RepresentationRepresentation

LayoutLayoutRepresentationRepresentation


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Design Abstraction levelDesign Abstraction level



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Four Levels of Design RepresentationFour Levels of Design Representation

BehavioralBehavioralRepresentationRepresentation

Logic (GateLogic (Gate--Level)Level)Re resentationRe resentation

Functional Blocks, FSMFunctional Blocks, FSM

Logic Blocks, GatesLogic Blocks, Gates


CircuitCircuit(Transistor(Transistor--Level)Level)RepresentationRepresentation

LayoutLayoutRepresentationRepresentation

Transistor SchematicsTransistor Schematics

Physical DevicesPhysical Devices


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Structure Design PrinciplesStructure Design Principles

HierarchyHierarchy:

Divide and conquerDivide and conquer technique involves dividing a module

into sub-modules and then repeating this operation on the sub-modules until the complexity of the smaller parts becomes

manageable.


uu:

The hierarchical decomposition of a large system should result

in not onlysimplesimple, but alsosimilarsimilar blocks, as much as

possible.

Regularity usually reduces the number of different modules

that need to be designed and verified, at all levels of

abstraction.


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Example of RegularityExample of Regularity


These circuits are built using inverters and triThese circuits are built using inverters and tri--state buffers only.state buffers only.


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Structured Design Principles (Cont.)Structured Design Principles (Cont.)

ModularityModularity:

The various functional blocks which make up the larger

system must have wellwell--defined functionsdefined functions and interfacesinterfaces.. Modularity allows each block to be designed independently;

All blocks can be combined with ease at the end of the


.

LocalityLocality:

Internal details remain at the local level.

The concept of locality also ensures that connections aremostly between neighboring modules,avoiding longavoiding long--distancedistance

connectionsconnections as much as possible.


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Example (Cont.): LevelExample (Cont.): Level 11

1616--bit Adderbit Adder

Complete LayoutComplete Layout


44--bit Adder with Manchester carrybit Adder with Manchester carry


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Carry/propagate circuitCarry/propagate circuit Output buffer/latchOutput buffer/latch


44--bit Adder with Manchester Carry Layoutbit Adder with Manchester Carry Layout

Manchester Carry circuitManchester Carry circuit


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Carry/propagateCarry/propagate

circuit layoutcircuit layout


Manchester carryManchester carry


Output buffer/latchOutput buffer/latch



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OutlinesOutlines

VLSI Design Flow and Structural Design

Principles

VLSI Design StylesVLSI Design Styles



Computer-Aided Design Technology for VLSI


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VLSI Design StylesVLSI Design Styles



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FullFull--Custom DesignCustom Design

Full-custom blocks are carefully crafted in thephysical level to obtain the highest possible

performance.



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FullFull--Custom Design Key IssuesCustom Design Key Issues

The key to Full-custom design is to exploit thefine-grained regularity and modularity in the

physical level. Manual full-custom design can be very

challen in and time consumin , es eciall if


the low level regularity is not well defined. Development cost are too high!

Design reuse is becoming popular to reduce design

cycle time and development cost.IP blocksIP blocks

Full-custom design is used only in the criticalblocks.


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FullFull--Custom DRAM ExampleCustom DRAM Example



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CellCell--Based DesignBased Design

Lego Style Design

All of the commonly used logic cells are

developed, characterized, and stored in astandard cell library.


such as inverters, NAND, NOR, each in severalversions to provide a range of performance.

The inverter gate can have standard size, double size, andquadruple size.

Most popular because of CAD tools availabilityand capability.


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CellCell--Based Design Key IssuesBased Design Key Issues

Inclusion/Exclusion of a gate variation dependson the objectives of the library.

Standard Library, Low Power Library, etc.

Most challenging task is to how to place the


in a way that meet stringent design goals.

Most advanced CAD tools have place-and-route tools.

In a complex, demanding design, standard-cellbased design approach may be used as a firstpass, then full-custom design where necessary.


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Example of Standard CellsExample of Standard Cells

Power RailPower Rail


Each cell layout is designed with a fixed height so that a numberEach cell layout is designed with a fixed height so that a numberof cells can be snapped together sideof cells can be snapped together side--byby--side to form rows.side to form rows.

Ground RailGround Rail


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Example of Stand Cells (Cont.)Example of Stand Cells (Cont.)

Standard CellStandard Cell


Routing ChannelRouting Channel


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CellCell--Based Design ExampleBased Design Example



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Masked Gate Array (MGA) DesignMasked Gate Array (MGA) Design

Only transistorsOnly transistors

No contacts and metal layersNo contacts and metal layers


One pattern mask forOne pattern mask for

Mass productionMass production


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MGA Design Key IssuesMGA Design Key Issues

Uncommitted (Unused) transistors or gates are

wasted.

Performance measured as Chip Utilization Factor ~used chip area/total chip area.


ncomm tte ce s can e sacr ces to mproveintercell routing capability

Modern GAs use multiple metal layers for

channel routing

Smaller area, higher density, and routability


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Example of MGA DesignExample of MGA Design



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FPGA DesignFPGA Design

An FPGA chip provides thousands of logicgates, organized into logic blocks, with

programmable interconnects. To implement a custom hardware, a user can use

hi h-level hardware ro rammin e. ., HDL .


Program logic table for each logic block.

Program interconnect switch matrices

Program I/O blocks

Programs last as long as the chip is powered-on


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Field Programmable Gate Array (FPGA)Field Programmable Gate Array (FPGA)


Architecture of Xilinx FPGAsArchitecture of Xilinx FPGAs


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FPGA (Cont.)FPGA (Cont.)


Simplified block diagram of a CLB by XilinxSimplified block diagram of a CLB by Xilinx


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XCXC40004000E Configurable Logic BlocksE Configurable Logic Blocks

D Q

SD

EC

S/R

Control

F'

G'

H'

DIN

GFunc.Gen.

G4G3G2G1

C4C1 C2 C3

YQ

H1 DIN S/R EC

2 Four-input function

generators (Look Up

Tables)- 16x1 RAM or

Logic function

RD

D Q

SD

RD

EC

S/R

Control

1

1

F'

G'

H'

DIN

F'

G'H'

H'

HFunc.Gen.

FFunc.Gen.

F4F3F2F1

K

Y

XQ

X

2 Registers- Each can be

configured as Flip

Flop or Latch

- Independent

clock polarity- Synchronous and

asynchronous

Set/Reset


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Look Up TablesLook Up Tables

Combinatorial Logic is stored in 16x1 SRAM Look Up Tables

(LUTs) in a CLB

Example:

A B C D Z

0 0 0 0 0

Look Up Table

Combinatorial Logic

AB

4-bit address


Capacity is limited by number ofinputs, not complexity

Choose to use each function

generator as 4 input logic (LUT) or as

high speed sync.dual port RAM

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 1

0 1 0 1 1

. . .1 1 0 0 0

1 1 0 1 0

1 1 1 0 0

1 1 1 1 1

CD

Z

GFunc.Gen.

G4G3G2G1

WE


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FPGA (Cont.)FPGA (Cont.)


Switch matrices and interconnection routing between CLBSwitch matrices and interconnection routing between CLB


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FPGA Design Key IssuesFPGA Design Key Issues

Chip utilization of an FPGA depends on

GranularityGranularity of the logic block - Size of logic block

Routing capabilityRouting capability - Size of switch matrices

The largest advantage of FPGA-based design is


The time required from the start of the design

process until a functional chip is available

Typical price of FPGA chips is usually higher

than other alternatives of the same design, butfor small-volume production and for fastprototyping


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HDLHDL--Based DesignBased Design

19801980ssHardware Description Languages (HDL) wereconceived to facilitate the information exchange

between design groups.

19901990ss


introduction of logic synthesizers that can translatethe description in HDL into a synthesized gate-levelnet-list of the design.

20002000ssModern synthesis algorithms can optimize a digitaldesign and explore different alternatives to identifythe design that best meets the requirements.


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HDLHDL--Based Design MethodologyBased Design Methodology



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Synthesis flowSynthesis flow

High-Level

Synthesis

Logic

Synthesis


Physical

Design

Fabrication and

Packaging


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VLSI Design StrategiesVLSI Design Strategies

Phenomenal growth rate in VLSI leads to a verycomplex and lengthy development of ICs.

Design complexity increases almost exponentiallyexponentiallywith the number of transistors to be integrated.

Efficient or anization of all efforts is essential to


the survival of a company. Teamwork

Better tools

Innovatives and creativities.

Better StrategiesBetter Strategies


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Product LifeProduct Life--CycleCycle


Products have a shorter lifeProducts have a shorter life--cyclecycle


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Comparison of Design StrategiesComparison of Design Strategies

Freedom of Choices.Freedom of Choices.

Custom DesignCustom Design



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Comparison (Cont.)Comparison (Cont.)

Cell DesignCell Design


FPGA DesignFPGA Design


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SystemSystem--OnOn--Chip (SOC) DesignChip (SOC) Design

Integrating all or most of the components of a

hybrid system on a single substrate (silicon or

MCM), rather than building a conventionalprinted circuit board.


onsequences:

More compact system realization

Less expensive!

Higher speed / performance Better reliability


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Example of SOC DesignExample of SOC Design


Digital Video ProcessorDigital Video Processor


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Example of SOC Design (Cont.)Example of SOC Design (Cont.)


Each functional block can be reused block, IP (IntelectualEach functional block can be reused block, IP (IntelectualProperty) block, or customProperty) block, or custom--designed block.designed block.


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OutlinesOutlines

VLSI Design Flow and Structural Design

Principles

VLSI Design Styles



ComputerComputer--Aided Design Technology for VLSIAided Design Technology for VLSI

CC Aid d i h lAid d i h l


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ComputerComputer--Aided Design TechnologyAided Design Technology

CAD tools become more and moreindispensable for timely development of ICs.

Remember! CAD tools are good helpers forCAD tools are good helpers fortimetime--consuming and computation intensiveconsuming and computation intensive

echanistic arts o the desi nechanistic arts o the desi n not the creativenot the creative


and inventive parts!and inventive parts! CAD technology divides into three categories:

Synthesis Tools (Synopsys)Synthesis Tools (Synopsys)

Layout Tools (Cadence)Layout Tools (Cadence)

Simulation and Verification ToolsSimulation and Verification Tools

S h i T lS h i T l


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Synthesis ToolsSynthesis Tools

HighHigh--Level SynthesisLevel Synthesis tools automate the designphase in the top level of the design hierarchy:

Based onHardware-Description Languages (HDL) VHDLVHDL, VerilogVerilog, etc.

Determining the types and quantities of modules to


be included in the design using accurate estimate oflower level design features (area and delay).

Logic Synthesis and optimizationLogic Synthesis and optimization tools can then

be used to customize the design to particularneeds, such as area minimization, low power,etc.

L T lL T l


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Layout ToolsLayout Tools

Circuit OptimizationCircuit Optimization tools deal with the designin the transistor schematic levels:

Transistor sizing for delay minimization

Reliability issues: process variations, noise.


uu

the design, i.e., how circuits are actually built onthe IC:

Standard Layout CAD tools areFloorplanning,

Place-and-route, and Module generation

Sophisticated Layout CAD tools are goal driven andinclude some degree of optimization functions

Si l ti d V ifi ti T lSi l ti d V ifi ti T l


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Simulation and Verification ToolsSimulation and Verification Tools

Time spent on debugging and correcting a

design has been increasing exponentiallyexponentially as

each generation passed. Higher penalty is paid if a design flaw is detected

later in the desi n rocess.


Simulation and verification are the most mature areain VLSI CAD

Goal of all simulation tools is to determine if thedesign meets the required specifications at a

particular design stage.

Si l ti T l (C t )Si l ti T l (C t )


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Simulation Tools (Cont.)Simulation Tools (Cont.)

Simulation tools used at various stages of the

design process are

Behavior simulationBehavior simulation tools

Logic Level simulationLogic Level simulation tools


omp ement og c synt es s an opt m zat on too s.

CircuitCircuit--level simulationlevel simulation tools

SPICE or derivatives such as HSPICE, PSPICE, etc.

Design Rule CheckingDesign Rule Checking tools Layout rule checking,Electrical Rule CheckingElectrical Rule Checking (ERC),

reliability rule checking.


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LayoutLayout


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LayoutLayout

Standard Cell Module


Complete Design

Chip

Placement and RoutingPlacement and Routing


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Placement and RoutingPlacement and Routing

Routing in

FPGA

Detailed Placement and

Routing


Chip FabricationChip Fabrication


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Chip FabricationChip Fabrication

GDS II


World wide ICWorld wide IC FoundaryFoundary CentresCentres


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World wide ICWorld wide IC FoundaryFoundary CentresCentres


International Technology Road MapInternational Technology Road Map


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International Technology Road MapInternational Technology Road Map


World wide Semiconductor vendorsWorld wide Semiconductor vendors


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World wide Semiconductor vendorsWorld wide Semiconductor vendors



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ConclusionsConclusions


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ConclusionsConclusions

Different levels of Abstractions

VLSI Design Flow

Design Methodologies

es gn y es


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