1 Department of Computer Science Overview 3190 Merrill Engineering Building, Salt Lake City, Utah...

1Department of Computer Science

Overview

3190 Merrill Engineering Building,Salt Lake City, Utah 84112

(801)-581-8224 (voice)(801)-581-5843 (fax)

[email protected] (e-mail) http://www.cs.utah.edu/

Departmentof

Computer Science


Faculty Overview

0

5

10

15

20

25

86 87 88 89 90 91 92 93 94 95 96 97State Funded Faculty FTE


Faculty Overview

Current 3 Visitors 5 Research 2 Teaching 19 Regular

0

5

10

15

20

25

3019

86

1987

1988

1989

1990

1991

1992

1993

1994

1995

1996

1997


Undergraduate Student Overview

~300 Computer Engineering & CS Students– ~90 students admitted each year

40 High School Students in Summer Program

CE Graduates CS Graduates

0

20

40

60

80

100

1991 1992 1993 1994 1995 1996 1997

# of Graduates(year of commencement)


Graduate Student Overview

~100 Graduate Students– split evenly MS / PhD

MS Graduates PhD Graduates

0

5

10

15

20

1991 1992 1993 1994 1995 1996 1997

# of Graduates(year of commencement)


Research Volume

Sources: DARPA, NSF, NIH, HP, etc. NSF Science and Technology Center in

Computer Graphics & Visualization– Brown, Cal Tech, Cornell, UNC - Chapel Hill

$ Millions

$0.0

$1.0

$2.0

$3.0

$4.0

$5.0

$6.0

$7.0

$8.0

91 92 93 94 95 96 97


MajorResearch

Areas

ArchitectureCAGD &CAM

VLSI & Async

Robotics & Computer Vision

Systems & Languages

NLP & Information Retrieval

Calvin: "I like to verb words." Hobbes: "What?"

Computational Science & Engineering

PE


Faculty in Industry

Dave Evans, Ivan Sutherland

Martin Griss, Tony Hearn

Chuck Seitz, Martin Newell

Department Flavor Large-scale Projects Tech Transfer

Alumni

Alan Ashton, Jim Blinn, Ed Catmull

Jim Clark, Frank Crow, Henry Fuchs

Henri Gouraud, Jim Kajiya, Alan Kay

Bui Tuong-Phong, John Warnock

Theory to PracticeTeam Projects

IntervalResearchCorp


Scientific Computing and Imaging Research Group

Chris Johnson (CS, Math, Physics, BE)Chuck Hansen (CS)

Sponsored by NSF (PFF, NYI, ARI), NIH, DOE, Whitaker Foundation, Siemens, Medtronic, State of Utah

The SCI research group has ongoing research projects in many areas ofscientific computing: geometric modeling, numerical analysis, parallel

computing, and scientific visualization. They are involved in bothdesigning efficient and accurate tools for scientific computing, and in

utilizing these tools for scientific applications.


Visualization of the Electrical Activity of the Heart Uses non-invasive

imaging techniques Computes and

visualizes voltages and current flow

Large-scale calculations and research into effective visualization

Working on optimization of internal defibrillators


Inverse EEG Simulations

Current techniques model brain and head as concentric spheres

Localization of electrical sources within the brain

Surgical treatment of epilepsy

Utilizes patient’s MRI scan to build accurate computer model


Computational Steering Problem: cycle time for

the scientific computing process is very long

Solution: “closing the loop” in the computation/visualization process

Controlling long running programs during execution

Feedback of intermediate results

Geometricmodels

ComputingVisual-ization


Vision/Robotics Research GroupThomas C. Henderson

John M. Hollerbach

William B. Thompson

Sponsored by ARPA and NSF

Research on problems in computer vision, sensing for manufacturing, and robotics


Current Projects Reverse Engineering of Mechanical Parts

– Create full-function CAD models for physical parts using position sensing

– Important for maintaining legacy hardware when spare part inventories are exhausted


Virtual Prototyping of AssembliesElaine Cohen, John Hollerbach, William Thompson

Providing a haptic interface to a CAD system for designing mechanical assemblies

Lets the designer “reach in” to interact with the parts before any physical prototypes have been fabricated


Dextrous Manipulation Calibration and

control of high degree-of-freedom autonomous and tele-operated manipulators

Haptic interfaces


Other Topics Sensor Modeling

– Better analysis of sensors used in robotics systems

– Tools for building virtual sensors into simulation environments

Visual Motion– Analysis of visual motion to determine environmental

structure and detect moving objects

Virtual Environments– Novel approaches to immersing users into simulated

worlds

Mobile Robotics– Sonar, IR-based, or Vision-based Navigation

– Object Recognition for Mobile Robots

Department of Computer Science

The Hamlet Project

Joseph L. Zachary

With support from NSF,

Dept. of Energy,

& Motorola, Inc.


What We Do

Deliver Web-based course material

– Unix, Fortran, C, Scientific Programming

– Several hundred students per quarter

– 5000 students since 1991

Develop server and browser enhancements

– Scripting HTML

– Hamlet

Innovate online instructional techniques


1991 - 1995 Progress

Relied on shared file system Served multiple classes Lessons written in extremely

limited hypertext Tracked student progress

Automated demonstrations

TA call queue

Administrative utilities

Relies on the Web Serves multiple classes Customized lessons written

in SHTML Server-side SHTML scripts

track student progress Demonstrations via Hamlet

external viewer TA call queue via server-

side scripts Administrative utilities via

server-side scripts

1991: The Tutor 1995: Netscape


Technology is Enabling Interactivity

Java opens great scope for browser-side innovation

Maple and Mathematica exist as C libraries

MBONE communications can supply “tele-TA”

Always remember: the author is more important

than the authoring system


The Flux Project Goal: high confidence systems

– Information security

– Resource management: memory, cpu, network bandwidth, ...

– High assurance, i.e. software correctness Approach

– Operating Systems research: local and distributed

– Compilers, languages, and formal methods

– Offshoot: OSKit - reusable low-level software components

• Widely used, including commercial; network appliances, Java/PC Potential Broad Impact

– Secure Java-based Web browsers

– Distributed collaboration

– Flexible & real-time instruments and embedded systems

– Anything needing high security: medical info, E-commerce, …

– Anything needing correct software: avionics, medical devices, …

Jay LepreauJohn CarterGary Lindstrom


JavaWilson Hsieh

Problem: Java does not allow for fine-grained resource management

– How do you revoke resources (such as memory)?

– How do you write programs where resources can be revoked?

Benefits: more control over untrusted software

Research: Language and runtime changes, OS support for resource management


Component Software ProjectRobert Kesslerwith N. Dykman, C. Mueller-Planitz, M. Salem, L. Williams

Currently sponsored by HP– Current domain: distributed measurement

systems

Problem:Problem: Building robust, distributed enterprise-scale measurement applications has high value, but is intrinsically difficult

Goal:Goal: Create environment where distributed measurement applications are significantly

faster to build and evolve

Strategy:Strategy: Customizable, component-based developmentframeworks and supporting tools.


Visual distributed program development and simulation framework Components - nested, hierarchical names, zooming, properties, ...

Ports - input or output ports, dynamically addable, properties, default values

Wires - point-to-point and bus Execution engine - static dataflow Drag and drop - to and from palette, start scripts, ... Visual faceplates - provide problem-specific look Threads - multiple threads, visualization ActiveX, COM - interfaces to environment, components,

external servers ActiveXScripting - VBScript, JavaScript, PERL Extensible - Loadable DLLs for types, components


CWAVE Features


Vision: ‘Sea’ of Active Objects

Smaller Vantera nodes

Larger computation and controller hosts

Large computation and server hosts


DEMO: Energy Management

0

5

10

15

20

25

30

35

40

45

1 2 3 4 5 6 7

Actual

Plan

0

5

10

15

20

25

Actual

Plan

DetailsHistoryNew SiteShed Load

Wed 6 June 97 June 97HPTotal

Hourly Peak PowerDaily Energy Used

Negotiate

Deregulated utilities issue real-time, fine-grained bills, rate tables, overload alerts. Companies must monitor and controlenergy usage and costs more precisely.

HSite managers monitor rate tables, contracts and energy usage, issue load balancing and load shedding directives.

SmartNodes and transducers on power panelsand major devices monitor and control usage

Utah Site

Palo Alto Site

CL 240v 3w IH2S IA30

KILOWATTHOURS


KILOWATTHOURS


KILOWATTHOURS


KILOWATTHOURS

kWHkW

, kW

h

kWh

kWh

kWh, $k

Power, rates, bills, alerts


KILOWATTHOURS

kW, kWh

kWh

Power, rates, alerts

Utilities: A key application domain


HP

LSD HP LABS

Building 1Building 3Building 4

Measurement Hierarchy

AgentAgentandand

meter meter palettepalette

Power

PowerPower

Power

Power

Power

H

Sub panel 2

Main PanelMotor 3

Process line 5

SubPanel

Agent and Analysis Components


CWave - Agent Scripts


CWave - Metering


CS Human Genome ProjectMotivation Gary Lindstrom

The Human Genome Project– An international effort to sequence the entire

genome• Identifying 3 billion nucleotides and 100,000 genes

– The aggregate amount of data is not huge • Entire sequence is approximately 750 Mb

However, the underlying concepts are complex– Objects with intricate attributes

– Complicated n-ary relationships between objects

– Stretches limit of the relational model


More Motivation

An appropriate data model is elusive– Must support current and unknown future queries

– Many levels of abstraction must be handled

– Much information deals with transient lab technologies

– Understanding of existing data is constantly evolving

Resulting problem: an ever changing schema– Indeed, the right data model is a scientific quest itself

– Plumbing all the relationships is ultimate goal of the HGP

Data is messy– Incomplete, inconsistent, erroneous, misinterpreted, …


Utah Genome Center Approach Identify the fundamental concepts of the domain

– Use them to define the concepts (types) of interest– Instances include: gene, probe, pedigree etc.– Generalized Objects, Relations, and Processes

(Gorp) Provide meta-data support

– By designing the database using fundamentals, broad flexibility can be obtained

Added payoff: reflective computing – Type information accessible to application programs – Enables fully general (polymorphic) support code


Computer Science Challenges Disciplined integrity maintenance

– What does integrity mean in this model?

– How can / should it be enforced?

Concurrency control– What should be consistency and sharing policies?

Data integration– Data movement from / to community databases

Performance– Many joins are required for most queries at present

Adopting modern DBMS technology– Especially object-oriented DBMS’s


Predictive Modeling

A continuing project with research directed at computer graphics, geometric and physically

based modeling, and improving the overall design process from initial, conceptual design to final

process planning and manufacturing

Elaine Cohen, Samuel Drake

Richard Riesenfeld, Peter Shirley

Sponsored by the NSF, DARPA


Goals

Create models that predict reality in an objective way

From art-to-part

Desired “behavior”(spec)

Modelcreation/editing

Interpretation

Realobject

Model

SyntheticTesting

PhysicalTesting


Consequences of Reaching Goals (Design-Manufacture)

– Slash product cycle time with electronic prototyping

– Integrating entire process leads to improved end product quality

– Make small lot production more economically feasible

– Create environments that support distributed (world-wide) design, analysis, and manufacturing collaborations


Research Issues

Representations Time Critical Geometric Computation Interaction Virtual Environments Design Systems Software Engineering Manufacturing


Projects

NSF Science and Technology Center for Computer Graphics and Scientific Visualization

Multiphase Integrated eNgineering Design (MIND)

Virtual Prototyping of Assemblies


Consortium:– University of Utah

– Brown University

– California Institute of Technology

– Cornell University

– University of North Carolina

Utah Faculty– Rich Riesenfeld, Co-Director

– Elaine Cohen, Co-PI

– Peter Shirley, Sam Drake, Charles Hansen, Chris Johnson


Research Shared Across Sites– User interfaces (C&R)

– Telecollaboration(C&R)

– (Collaborative) Virtual Environments(C&R)

– Rapid Distributed Design and Fabrication (C,D,&R)

– Statistical Approaches to Rendering(S)

– Wavelets in Medical Modeling (J)

24 hour televideo communication– 5-way advanced graphics course taught year long


MIND & STC:Predictive Modeling for Shape

For geometric models including assemblies and mechanisms, how do you:

– Decompose into subassemblies

– Represent

– Specify

– Manipulate

– Visualize

– Capture Intent


MIND: Predictive Modeling for Engineering

All of those for Shape +

Manufacture– Process planning

– Target: traditional manufacturing processes (milling, turning, CMM, EDM), and innovative (SFF)

Material– Heterogeneous materials

– Embedded objects


Example: Madefast

Goal: Create a missile seeker assembly (physical hardware, optics, circuitry) using nationwide resources

Extensive use of WWW

Towards Dependable Computing


Towards Dependable Computing through Formal Methods

the Utah Verifier group

Ganesh Gopalakrishnan (11th yr on fac.)

Ratan Nalumasu (PhD, last yr - hopefully :-)

Ravi Hosabettu (PhD, 2nd yr.)

Rajnish Ghughal (MS, 1st yr.)

Michael Jones (PhD, 1st yr.)

Abdel Mokkedem (Visiting Asst. Prof.)

Paliath Narendran (Visiting Associate Prof.)



Must digital design be hinged on “trial and error”?

The Problem

Digital systems are getting very complex!– involve complex processors, software, …

– used in critical applications (cars, aerospace, banking, medical equipment, smart cards, …)

Design practices are falling behind!– designers work based on imprecise specs.

– debugging tools increasingly miss critical errors

– greed dilutes quality standards

“Errors” occur in different forms– “show-stoppers” (FDIV, FIST, AMD K-6, PowerPC)

– lost productivity due to poorly designed standards (PCI bus, VHDL/Verilog…)



Why current approaches don’t work well

Humans “no longer in the loop” (Philosophers .vs. embedded “spaghetti code”)

A new “ballgame” (complexity / time-to-market ) Quest for performance introduces situations that

call for new semantics (with very low re-use)– “net-effect” of operations hard to state

• e.g., concurrent microcode routines that update 22 registers in one step

– “Race” between reads and writes

• e.g., the use of abstract Memory models to define the hardware / software boundary



Formal Methods

Nothing more than “rigorous common-sense”! Provide a definition for what it means to

– “test a system” (test a well-specified model)

– “a test” (a mathematical property)

– “synthesis” (model refinement)

Enables tools to be built around above notions– modeling languages

– testing tools (aka “formal verification tools”)

– synthesis tools

A little rigor can go a long way!



Formal Verification de-mystified...

- Things break when you least expect (Murphy’s law)

- Bugs tend to hide in “corners” of the execution space

- How to highlight the corners?



the Model-Checking answer

- Scale-down symmetric data-states

- Model other data-states through non-determinism

- Retain key control states

- Analyze scaled-down system exhaustively

- Highlight corner cases using properties as filters



process p{ do :: (x == 0) :: true :: ... od }process q{ do :: y==0 :: z==0 od }

... ...

c2 ! x+1

A Generic Example

<pq,0,0,0>

<p1q,1,0,0>

...

...

... ...

...

- Create State-graph

- Check for Safety and Liveness

properties on-the-fly



the Theorem Proving answer

- Facilitate rigorous specs. and specification validation

- Facilitate building high-level models (“infinite-state”)

- Prove general properties via automated symbolic logic

- Corners revealed during “case analysis” during proof



A Generic Example

thm to be proved

subgoals created by proof-rule(e.g. “induction” or “rewrite”)

g1 g2

A thm prover forces a systematic walk-through thru allcases, revealing “corner cases”



Aims of our FM Research Develop FM tools to support design activities Demo in the context of realistic systems We use a Driving Design (Avalanche MP)

Where FM has been / will be used:

– Requirements capture and verification

– Modeling and verifying bus and DSM protocols

– Detailed design of the Widget

CPU MEM

WIDGET Myrinet

HP PA 8000

DSM &Msg passingcontroller



Our Project: Utah Verifier



Goals of UV

Develop tools tailored for each level of abstraction

Apply to real examples

We identify three such tools

– Design requirements-Base (DB)

• requirements capture & validation

• theorem-proving support

– Protocol Verifier (PV) to support protocol verification and synthesis

– Cycle-level Verifier (CV) to verify cycle-level properties, and HDL models embodying them

PV CV

DB



A New Partial-Order Reduction Algorithm for Concurrent System Verification

Ratan Nalumasu

Ganesh Gopalakrishnan

CHDL’97

Result #1



Basic Idea (highly simplified)

P: c!1 ; c!2 ; c!3||Q: c?x ; c?y ; c?z

P

Q

Avoid exploring all possible interleavings!



Results

States Time (s)Mig (spin) 113,628 13.6

Mig (PV) 9,185 1.7

Inv (spin) > 620,446 DNF

Inv (PV) 135,404 21.2Missed bugFound bug

0

5,000

10,000

15,000

20,000

SC2 SC3 SC4 Pftp Snpy

SPIN

PV

Statesdnf x10



Protocol Refinement

Ratan Nalumasu

Ganesh Gopalakrishnan

(Submitted to FORTE’97)



Motivations

Coherence Protocols written “in the usual way”

are difficult to understand and debug

– Ad-hoc handling of resources

– No guarantees (explicit or implied) of behavioral properties (e.g. scalability)

“Unexpected” message reception

– Handled by transient states and nacks that are

introduced in a very ad-hoc manner



Problems due to “unexpected msgs”

Req Ack

Another Req? ? ?Usually don’t know what to say…...saying nothing causes deadlock!



Solution: Refine protocol written at a much higher level

Uses synchronous communication

– No need for transient states Debug high-level spec thoroughly

– e.g.: formal analysis of progress properties Apply proven transformations

– Efficient low-level protocols are obtained

– Resources allocated during transformation



Overview of Synthesis Method

I ECacheCtrlr

F EDir Ctrlr

I E

F E

Req (N)ack



Advantages

HL Specs are vastly more efficient to verify

Results in “hand-quality” protocols

Transient states added as necessary

No infinite-buffering assumption



Ease of Debugging

Protocol N states / time(low level)

states / time(high level)

Mig 2 23,164 / 2.8 54 / 0.14 235 / 0.48 965 / 0.5

Inv 2 193,389 / 19.23 546 / 0.64 18,686 / 18.4



Work in progress

Exploration of Multi-way Decision Graphs (RaviH)

Construction of Formal Model for the Runway Bus

(Rajnish and Ravi)

Protocol Synthesis tool (Ratan)

Use of Protocol Synthesis ideas for Async Ckt

Synthesis (Hans)

Modeling the Avalanche “Widget” (all of us)



On Teaching FM

Five students; one with prior exposure to SPIN and Promela; all were “systems types”

Modeled large portions of Fluke Kernel

– partly trans. into Promela using reasoning

– partly hand-translated mechanically

Modeled thread cancellation (5000 lines C)

Discovered two bugs in thread cancellation

Useful “copper model” for future work

Paper in Hot-OS’97



Conclusions

The Utah Verifier group is developing an integrated set of Formal Verification tools

They will be demonstrated on realistic in-house designs (e.g. the Avalanche, Fluke, …)

Expected Results:

– rigorous design methods

– rigorous verification methods

– Better

• Thinking aids, Communication tools, and Documentation tools for project-wide use



What’s Wrong with Status quo?

The inability to design correctly (rather than the inability to “fabricate” in VLSI) will stifle advances

– companies unsure how to debug high-end systems

– unsure when to stop testing and ship the product

– “blind simulation” (rooms full of workstations and emulators) - a popular measure - is very wasteful, and provides little confidence of good coverage

– standards designed with little regards to established wisdom waste expert designer time!

Real advances must come from deeper understanding and correctness by construction



Approaches to Formal Verification

All approaches are based on some branch of mathematical logic:

– Boolean Logic

– First-order Logic

– Temporal Logics

– Higher-order Logics

Good decision procedures (with tool-support) are available for large fragments of all these

Two “extreme approaches” are usually pointed out:

– model-checking

– theorem-proving


The Utah Verifier ProjectGanesh Gopalakrishnan (Darpa ITO)

Tools for developing hardware and reactive software, for example:

– bus-based hardware systems

– coherence protocols

– software to realize concurrent protocols Technical approach

– create models for hardware (in HDLs) or software (in concurrent programming notations)

– formal verification for correctness properties (deadlocks, correct response) are supported

– achieves design capture and design validation for early debugging, leading to improved product quality and reduced design time

Protocol Verifier (PV) and Cycle Verifier (CV) integrated with Design requirements Base & verifier for system-level properties

PV CV

DB


Asynchronous Computer Architecture

Erik Brunvand, Ganesh Gopalakrishnan, Chris MyersSponsored by the NSF, State Center of Excellence

How asynchronous circuit techniques impact the design of a general purpose computer and the development of CAD tools for the design of asynchronous integrated circuits


Asynchronous CAD Tools

ACK– A framework for the complete design from high-

level descriptions to integrated circuit layout

– Leveraging commercial synchronous CAD tools (Cadence, Cascade, Synopsys, and ViewLogic)

ATACS– High-speed asynchronous controller design

– Uses timing in asynchronous circuits to increase performance


Fred - A self-timed, decoupled, pipelined computer architecture based on micropipelines

Completely self-timed, no clocks anywhere Organized as a set of independent concurrent

hardware processes Support for multiple functional units, out-of-

order instruction issue and completion Decoupled control flow (branch) and memory

operations Innovative “functionally precise” exception

model


Fred Block Diagram: Solid lines are primary data paths, dashed lines are control

paths. All data and control paths may be pipelined.

DispatchUnit

RegisterFile

Scoreboard

Distributor

Branch Unit

Control Unit

Logic Unit

Arithmetic Unit

Memory Unit

Inst

ruct

ion

M

emo

ry

Inst

ruct

ion

s

Data Memory

Execute Unit

Results

Results

Results

Results

R1

Qu

eue

Ad

dre

ss

Wri

teD

ata

Rea

dD

ata

Set/Clear

ReadOperand Request Queue

Operand Queue

Do

ne

Qu

eue

Clear

Pre

fetc

h A

dd

ress

Bra

nch

Qu

eue

Exc

epti

on

Bra

nch

Qu

eue


VLSI Research

Kent F. Smith

Cosponsored by ARPA, NSA, FBI


Commercial VLSI Design Tools Used at U of U

Cadence - composite layout, DRC, ERC, LVS

Cascade - place & route, static timing, libraries for

many vendors

Synopsis - VHDL, Verilog

Viewlogic - schematic capture, gate level simulation

Hspice - analysis with transistors, capacitors


U of U Developed VLSIDesign Tools and Chip Mfg.

PPL/ACME - Physical Schematic Capture

Complete system for small chips - 10,000 gates

Libraries, physical layout, unit delay simulation, CIF

output

MOSIS compatible - chip cost under $500

CMOS (2, 1.2 and 0.6 m), GaAs (mesfet and HBTs)


Current VLSI Projectsat the U of U

ARPA #1 - Large (> 1M transistors) sub-

micron ASICs for multiprocessor control

ARPA #2 - High speed GaAs circuits - 10 GHz

clock rates with HBTs

NSA - ASIC CMOS chips

FBI - Active noise cancellation - filters, A/D

converters, digital signal processing, analog-

digital circuits


Example of Analog/DigitalASIC Design

Pressure Transducer - One chip contains analog conditioning circuits and the digital circuits for control and bus communication

Diaphragm covering evacuated cavity is attached to the chip - pressure changes cause flexing of lid

Pressure changes result in changes in the capacitance between the diaphragm and the analog integrated sensor circuit

Capacitance changes are measured with analog/digital circuitry and transmitted via a digital bus.CMOS chip

4 mm

digital analog


Avalanche

Scaleable Parallel ProcessorProject

Al Davis, Erik Brunvand, John Carter, & Mark Swanson

Sponsored by ARPA, Hewlett Packard,

Myricom, & SPAWAR


Avalanche Mission:Scaleable Computing

Massively parallel processors still too expensive

Workstation clusters offer scaleable cost, but too slow

Widening gap between CPU and DRAM performance

0

50

100

150

200

250

300

350

400

450

500

1987 1989 1991 1993 1995

Pe

rfo

rman

ce

CPU

DRAM

Workstation Clusters

$10,000 $200,000 $3,000,000


Avalanche CommunicationMinimize Latency!

Communication Software:– Multiple programming models - Message Passing and DSM.

– Optimize the protocol path (minimize data copying).

– Sender-Based Protocols allow near link bandwidth and latency.

– Adaptive DSM protocols - invalidate, migratory, and update.

Communication Hardware:– Leverage commercial workstation - CPU, Bus, Memory, etc.

– Integrate communication fabric with memory hierarchy.

– Coherent second level cache to reduce miss latency.

– Adaptive DSM models - CC-NUMA and S-COMA.


Avalanche OverviewPlug our “Widget” into COTS HW.

ProcessingElement

Avalanche“Widget”

AvalancheTopology

PEPESharedBuffer

(SRAM)

NetworkInterface

CacheController

BookkeepingCache

DirectoryController

Prot. Proc.Engine

BusInterfaceProcProc

DRAMDRAM

I/OI/O

WidgetWidget

Proc

CacheCache

Sys

tem

Bu

s


Adaptive Memory Systems

John Carter, Al Davis, John Carter, Al Davis,

Erik Brunvand, Mark Erik Brunvand, Mark SwansonSwanson

Computer Systems Laboratory


Technology Motivation The Memory Gap Continues to Widen

– 60%/Year Processor Performance Improvement

– 7%/Year DRAM Performance Improvement

Processor and DRAM business momentum high– forcing a change to achieve better performance is unlikely

Internal CPU parallelism is escalating– 4 issue processors now - 8 issue already announced

Yet the bottleneck is in the memory system– Sadly Von Neumann’s 1945 prediction remains true

– CPU performance improvements are only partially seen by the applications

• Caches are beginning to fail badly

• Memory bus contention is a key source of stalls

• A new approach is essential


Evidence = Sites/Perl Study (1996) Alpha 8400 (21164 CPU), 300 MHz, 4-issue Running

– Microsoft SQLserver Database

– Windows-NT Operating System Performance

– 12% of peak memory bandwidth achieved

– CPI = 2.0 rather than 0.25!

• AN 8X SLOW DOWN! (pointer chasing prefetching not possible) Implication

– Commercial database codes account for 95% of industry revenue

– High performance database processing is a critical DoD need

– BOTTOM LINE: CACHES FAIL ON DATABASE CODES

– The problem is the memory system

• optimized for linear dense usage - NOT TRUE FOR DATABASES

(Demand = 300 MHz x 16B = 4.8 GB/Sec)


The Adaptive Memory Concept

Densely remappedsparse data

Data w/good reuseremapped

to use mostof cache

...

Dense data withpoor locality

Sparse data withpoor locality

Dense data withgood localityConventional memory

systems: High conflictrate, poor bus utilization

Unused data

Conflicts!

Adaptive memory system :Remapping Low conflictrate, good bus utilization


Sys

tem

Mem

ory

Bu

s

Cache

AMCAMCASICASIC

AMCAMCASICASIC

Proc

DR

AM

Bu

s

DRAM

(64

Dat

a B

its)

(64

Dat

a B

its)

Adaptive Memory Controller CPU, Cache, and DRAM structures do not need to change!!


Natural Language Processing and Information Retrieval

Ellen Riloff and Lee Hollaar

Sponsored by the NSF

Current Projects include:

Information Extraction, Automated Dictionary Construction for Information Extraction, and Text Categorization


Information Extraction

Information extraction involves extracting predefined types of information from text.

Example: extracting companies, products, and locations associated with joint ventures.

Japan Storage Battery Co. announced it has teamed up with a leading French battery maker, Saft S.A,, to set up a joint venture in Japan to market small batteries.

Mitsui and Co., a major Japanese trading house, said Tuesday it will form a joint venture in Canada next March to produce ethylene glycol (EG) with a subsidiary of Union Carbide Corp. of the United States.


Automated Dictionary Construction for Information Extraction

The AutoSlog dictionary construction system generates patterns for information extraction automatically.

Japan Storage Battery Co. announced it has teamed up with a leading French battery maker, Saft S.A., to set up a joint venture in Japan to market small batteries.

<x> has teamed up <x> is a partner companyhas teamed up with <y> <y> is a partner companyventure in <z> <z> is location of ventureto market <p> <p> is product of venture


Automated Dictionary Construction Using AutoSlog

source texts answer keysToyota, Nissan

EXTRACTION PATTERNS:

<x> teamed up teamed up with <y>

AutoSlog

"Toyota teamed up with Nissan ..."

Sentence Analyzer

S: Toyota VP: teamed up PP: with Nissan ...


Text CategorizationText categorization involves assigning category labels

to texts. Applications include text filtering and text routing.

Natural language processing can make important linguistic distinctions that keywords alone cannot.

Expression % in relevant textsventure between <x> 100%venture with <x> 96%joint + venture (keywords) 89%joint + ventures (keywords) 67%

to manufacture <x> 87%<x> was manufactured 53%

<x> will construct 100%was constructed by <x> 64%


The Relevancy Signatures Algorithm for Text Categorization

TRAINING

relevancy signatures

Sentence Analyzer

preclassified texts

CATEGORIZATION

relevancy signaturessignatures

category

Sentence Analyzer

new text


Summary

Information extraction techniques are useful for many real-world applications and are more tractable than in-depth understanding methods

Using our automated dictionary construction system, AutoSlog, information extraction systems can be built quickly for new applications

Information extraction can be used to achieve high-precision text categorization

Natural language processing can distinguish between similar linguistic expressions that may behave very differently in a given application

1 Department of Computer Science Overview 3190 Merrill Engineering Building, Salt Lake City, Utah...

Documents

Transcript of 1 Department of Computer Science Overview 3190 Merrill Engineering Building, Salt Lake City, Utah...