1 Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University,...

2

EA KIT240-7 (Electronic Assembly)

Available: EA KIT 240-7. Control panel with fonts, graphic commands and macros.Electronic Assembly, 2002: http://www.lcd-module.de

240

128

Pixels

RS232

begins majority of commands (ASCII code 1B16)the code of command (ASCII code 5716)

Draws a straightline from the lastend point to the

point withcoordinates (x1,y1)

last end point

x1 y1

3

rs_control

provides the selected baud rate

4

subtype word10 is std_logic_vector (8 downto 1);type serial_pac is array (0 to 8) of word10;constant line_RS : serial_pac := (x"1B", --delete displayx"44", --delete displayx"4C", --delete displayx"1B", --draw line (ESC)x"47", --draw line (code of this operation)x"30", -- x1 left pointx"15", -- y1 upper pointx"E6", -- x2 right point x"72"); -- y2 bottom point

the first commandthe second command

000110112

5

subtype word10 is std_logic_vector (8 downto 1);type serial_pac is array (0 to 8) of word10;constant line_RS : serial_pac := ( x"1B",

x"44",x"4C",x"1B",x"47",x"30",x"15",x"E6",x"72");

“00011011”

sta

rt b

it

sto

p bi

t

8 data bits

1 2 3 4 5 6 7 8

lclk

if rising_edge(lclk) then

RS232out <= line_RS(ind)(tmp);

RS232inRS232out

80 8 1

Begins any instruction

x"1B"

0001101100011011

6

case tmp is when 0 => my_out <= '0'; tmp := tmp + 1; when 1 to 8 => my_out <= line_RS(ind)(tmp); tmp := tmp + 1; when 9 => my_out <= '1'; tmp := tmp + 1; when 10 => tmp := 0; ind := ind + 1; when others => tmp := 0;end case;

RS232inRS232out

8 databits

start bit

stop bitcase tmp is when 0 => my_out <= '0'; tmp := tmp + 1; when 1 to 8 => my_out <= line_RS(ind)(tmp); tmp := tmp + 1; when 9 => my_out <= '1'; tmp := tmp + 1; when 10 to 1500 => tmp := tmp + 1; my_out <= '1'; when 1501 => tmp := 0; ind := ind + 1; when others => tmp := 0;end case;

RS232out <= my_out;

because LCD panel works slow

7

RS232inRS232out

process(clk, rst)variable tmp, ind: integer;beginif rst= '1' then tmp:=0; ind :=0; elsif falling_edge(clk) then if rs232in = '0' then ind := 1; end if; if (tmp >= 1) then

if (tmp <= 8) then LCD_symbol(tmp-1) <= rs232in; end if;

end if; if ind = 1 then tmp := tmp + 1; end if; if (tmp >= 9) and (rs232in = '1') then tmp := 0; ind := 0; end if;end if;result <= LCD_symbol;end process;

8 data bitswaiting

for start bit

receivingdata bits

waiting for stop bit

received_ASCII

8

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use ieee.numeric_std.all;

entity RS_control is Port ( clk : in std_logic;

rst : in std_logic;rin : in std_logic_vector(7 downto 0);result : out std_logic_vector(7 downto 0);rs232in : in std_logic;rs232out : out std_logic);

end RS_control;

baud rate for the consideredexample is 115 200

reset

received_ASCII

result from touch panel

9

architecture Behavioral of RS_control issubtype word10 is std_logic_vector (8 downto 1);type serial_pac is array (0 to 8) of word10;constant line_RS : serial_pac := (x"1B", --delete displayx"44", --delete displayx"4C", --delete displayx"1B", --draw line (ESC)x"47", --draw line (code of this operation)x"30", -- x1 left pointx"15", -- y1 upper pointx"E6", -- x2 right point x"72"); -- y2 bottom point

signal LCD_symbol : std_logic_vector (7 downto 0);signal my_out : std_logic;

10

beginprocess(clk, rst)variable tmp: integer;variable ind : integer;beginif rst= '1' then tmp:=0; ind := 0; my_out <= '1'; elsif rising_edge(clk) then if ind <= 8 then case tmp is

when 0 => my_out <= '0'; tmp := tmp + 1;when 1 to 8 => my_out <= line_RS(ind)(tmp); tmp := tmp + 1;when 9 => my_out <= '1'; tmp := tmp + 1;when 10 to 1500 => tmp := tmp + 1; my_out <= '1';when 1501 => tmp := 0; ind := ind + 1;when others => tmp := 0;

end case; end if;end if;RS232out <= my_out;end process;

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process(clk, rst)variable tmp: integer;variable ind: integer;beginif rst= '1' then

tmp:=0; ind :=0;elsif falling_edge(clk) then

if rs232in = '0' then ind := 1;end if;if (tmp >= 1) then


end if;if ind = 1 then tmp := tmp + 1;end if;if (tmp >= 9) and (rs232in = '1') then

tmp := 0; ind := 0;end if;

end if;result <= LCD_symbol;end process;end Behavioral;

12

architecture Behavioral of RS_control issubtype test8 is std_logic_vector (7 downto 0);type test is array (7 downto 0) of test8;signal my_test : test;

subtype word10 is std_logic_vector (8 downto 1);type serial_pac is array (0 to 8) of word10;constant line_RS : serial_pac := (“00011011", --delete display“01000100", --delete display“01001100", --delete display“00011011", --draw line (ESC)“01000111", --draw line (code of this operation)“00110000", -- x1 left point“00010101", -- y1 upper point“11100110", -- x2 right point “01110010"); -- y2 bottom point

signal LCD_symbol : std_logic_vector (7 downto 0);signal my_out : std_logic;-- . . . . . . . . . . . . . . . . . . . . . . . . . . .

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1 2

3

4

14

0110110001

0110110001

start bit

0 1 1 0 1 1 0 0 0 1

8 data bits

1 Bstop bit

subtype word10 is std_logic_vector (8 downto 1);type serial_pac is array (0 to 8) of word10;constant line_RS : serial_pac := (“00011011", --delete display“01000100", --delete display“01001100", --delete display-- ………………………………

16

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity RS_divider is Port ( clk48 : in std_logic;

rst : in std_logic; clockRS : out std_logic);

end RS_divider;architecture Behavioral of RS_divider issignal lclk : std_logic;beginprocess(clk48, rst)variable temp: integer;begin

if rst= '1' thentemp:=0; lclk <= '0';

elsif rising_edge(clk48) then temp := temp + 1; if temp = 208 then lclk <= '1'; elsif temp > 417 or temp < 0 then lclk <= '0'; temp:=0; end if;end if;

end process;clockRS <= lclk;end Behavioral;

48 MHZ

baud rate115 200

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Crossing was doneinside the board

4 3

6 2

7 RTS

5 CTS

RS232/J3(10 pins)

RS232/9 pins

grouund 5

10ground

User constraintsNET "rs232out" LOC = "c12";NET "rs232in" LOC = "b13";

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Mode 1(automatically)

Mode 2(dependently

on switch)

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library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use ieee.numeric_std.all;entity RS_control is -- see slide 8 Port ( clk : in std_logic;


end RS_control;architecture Behavioral of RS_control issignal LCD_symbol : std_logic_vector (7 downto 0);signal my_out : std_logic;signal lclk : std_logic_vector(19 downto 0);

subtype word10 is std_logic_vector (8 downto 1);type serial_pac is array (0 to 21) of word10;

Less significant bit,which allows to changethe size of the rectangle

internal signal to

store th

e result internal signal tostore an output for

RS232

low frequency clock

word10 allows to changethe number of bits in

the vectors if required

Subtype is the same typeas its base type. Assignmentbetween subtype and basetype objects can be made

without conversion

serial_pac contains 22 words (ASCII codes),which will be sent through RS232

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constant line_RS : serial_pac := (x"1B", --delete displayx"44", --delete displayx"4C", --delete displayx"1B", --define a rectangle (ESC) | if rin = “0…0"x"42", --define a rectangle (code of this operation)x"52", -- extend to rightx"01", -- number given to this rectanglex"2A", -- x1x"2A", -- y1x"7A", -- x2x"4A", -- y2x"04", -- start value (0...254)x"84", -- end value (0...254)x"04", -- number of patternx"1B", -- draw the defined above rectangle (ESC)x"42", -- draw the defined above rectangle (code)x"01", -- numberx"5A", -- new value in between start and end

x"1B", -- draw the defined above rectangle (ESC) | if rin /= “00000000"x"42", -- draw the defined above rectangle (code)x"01", -- numberx"3F"); -- new value in between start and endT

hes

e 22

AS

CII

cod

es w

ill b

e se

nt

seq

uen

tial

ly t

o R

S23

2 b

egin

nin

gfr

om t

he

top

cod

e (1

B16

) an

d e

nd

ing

by

the

bot

tom

cod

e (3

F16

) LCD command clear display

LCD command thatdefines (but does not

draw) a bar(a rectangle).

All the details aregiven in

http://www.lcd-module.de

LCD command thatdraws the defined above

rectangle

21

beginprocess(clk,rst)begin

if rst = '1' then lclk <= (others => '0');elsif falling_edge(clk) then lclk <= lclk+1;end if;

end process;process(clk, rst)variable tmp: integer;variable ind, ind1 : integer;beginif rst= '1' then tmp:=0; ind:=0; ind1:=0; my_out<='1'; elsif rising_edge(clk) then if lclk(lclk'left) = '1' then -- rin = “00000000" then – use this italic line for the mode 2 if ind <= 17 then

case tmp iswhen 0 => my_out <= '0'; tmp:=tmp+1;when 1 to 8 => my_out <= line_RS(ind)(tmp); tmp:=tmp+1;when 9 => my_out <= '1'; tmp:=tmp+1;when 10 to 1500 =>tmp:=tmp+1; my_out<='1';when 1501 => tmp:= 0; ind:=ind+1; ind1:=0;when others => tmp := 0;

end case; end if;

This process provides low frequency forchanging sizes of the rectangles on the LCDin visual mode. This process can be removed

for the second mode

This block is executed for the firstrectangle with larger size

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else if ind1 <= 21 thencase tmp is

when 0 => my_out <= '0'; tmp := tmp + 1;when 1 to 8 => my_out <= line_RS(ind1)(tmp); tmp := tmp + 1;when 9 => my_out <= '1'; tmp := tmp + 1;when 10 to 1500 => tmp := tmp + 1; my_out <= '1';when 1501 => tmp := 0; ind1 := ind1 + 1; ind := 0;when others => tmp := 0;

end case; end if; end if;end if;RS232out <= my_out;end process;

This block is executed for the secondrectangle with smaller size

23







end if;result <= LCD_symbol;end process;end Behavioral;

This process receives data from LCD,which can be generated when you touchthe panel. This block will be needed for

the next example (example 3)See slide 7

24

A B C D

ADDORTTEST

1 touch A

ORTADD

TEST

received_ASCII A

2 touch B

received_ASCII B

3 touch A

TEST

ADDORT

received_ASCII A

4 touch C received_ASCII CORTADD

TEST

5 touch D

received_ASCII D

touch B toreset a

previousmenu option

25

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;use ieee.numeric_std.all;

entity RS_control is Port ( clk : in std_logic;


end RS_control;

architecture Behavioral of RS_control is

subtype word10 is std_logic_vector (8 downto 1);type serial_pac is array (0 to 72) of word10;

signal LCD_symbol : std_logic_vector (7 downto 0);signal my_out : std_logic;

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constant line_RS : serial_pac := (x"1B", --0x"46", --1x"05", --2x"02", --3x"01", --4

x"1B", --5x"51", --6x"43", --7x"00", --8

x"1B", -- 9std_logic_vector(to_unsigned(character'pos('D'), 8)), -- 10std_logic_vector(to_unsigned(character'pos('L'), 8)), -- 11

x"1B", --19 --12 -- command IDx"54", --20 --13 -- initiation of touch commandx"48", --21 --14 -- horizontal labelingx"01", --22 --15 -- upper left touch fieldx"0C", --23 --16 -- lower right touch fieldx"41", --24 --17 -- return code of the letter Ax"02", --25 --18 -- drawing of key with framex"41", --26 --19 -- drawing of letter A in the framex"00", --27 --20 -- end of this command

x"1B", --21x"54", --22x"48", --23x"04", --24x"0F", --25x"42", --26x"02", --27x"42", --28x"00", --29

sets font

switches the cursor off

clears the display(compare with the slide 20)

similarcommand

0C16=1210

received_ASCII A

A B

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x"1B", --30x"54", --31x"48", --32x"07", --33 x"12", --34x"43", --35x"02", --36x"43", --37x"00", --38

x"1B", --39x"54", --40x"48", --41x"0A", --42 x"14", --43x"44", --44x"02", --45x"44", --46x"00", --47

similarcommand

A B C D

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x"1B", -- command IDx"4E", -- display menu x"48", -- horizontal menux"60", -- x for upper left cornerx"30", -- y for upper left cornerx"01", -- currently inverted itemstd_logic_vector(to_unsigned(character'pos('A'), 8)),std_logic_vector(to_unsigned(character'pos('D'), 8)),std_logic_vector(to_unsigned(character'pos('D'), 8)),x"7C", -- separatorstd_logic_vector(to_unsigned(character'pos('O'), 8)),std_logic_vector(to_unsigned(character'pos('R'), 8)),std_logic_vector(to_unsigned(character'pos('T'), 8)),x"7C", -- separatorstd_logic_vector(to_unsigned(character'pos('T'), 8)),std_logic_vector(to_unsigned(character'pos('E'), 8)),std_logic_vector(to_unsigned(character'pos('S'), 8)),std_logic_vector(to_unsigned(character'pos('T'), 8)),x"00", -- separator

x"1B", -- command IDx"4E", -- the next menu item is invertedx"4E", -- the next menu item is invertedx"1B", -- command IDx"4E", -- the previous menu item is invertedx"50"); -- the previous menu item is inverted

A B C DADDORTTEST

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beginprocess(clk, rst)variable tmp: integer;variable ind, ind1, ind2 : integer;beginif rst= '1' then tmp:=0; ind := 0; ind1 := 67; ind2 := 70; RS232out <= '1'; elsif rising_edge(clk) then

if ind <= 66 thencase tmp is

when 0 => my_out <= '0'; tmp := tmp + 1;when 1 to 8 => my_out <= line_RS(ind)(tmp); tmp := tmp + 1;when 9 => my_out <= '1'; tmp := tmp + 1;when 10 to 1500 => tmp := tmp + 1; my_out <= '1';when 1501 => tmp := 0; ind := ind + 1;when others => tmp := 0;

end case;

end if;if ind1 <= 69 then if LCD_symbol = x"41" then

case tmp iswhen 0 => my_out <= '0'; tmp := tmp + 1;when 1 to 8 => my_out <= line_RS(ind1)(tmp); tmp := tmp + 1;when 9 => my_out <= '1'; tmp := tmp + 1;when 10 to 1500 => tmp := tmp + 1; my_out <= '1';when 1501 => tmp := 0; ind1 := ind1 + 1;when others => tmp := 0;

end case;

end if; end if;

the values of these variables will bechanged below in the process

dependently on the code of a symbolreceived from touch panel of the LCD

thus, different control subsequenceswill be activated

30

if ind2 <= 72 thenif LCD_symbol = x"43" then

case tmp is when 0 => my_out <= '0'; tmp := tmp + 1; when 1 to 8 => my_out <= line_RS(ind2)(tmp); tmp := tmp + 1; when 9 => my_out <= '1'; tmp := tmp + 1; when 10 to 1500 => tmp := tmp + 1; my_out <= '1'; when 1501 => tmp := 0; ind2 := ind2 + 1; when others => tmp := 0;end case;

end if; end if;

if LCD_symbol = x"42" then ind1 := 67; ind2 := 70; end if;

end if;RS232out <= my_out;end process;

if LCD_symbol = x"42" then ind1 := 67; ind2 := 70; end if;

31







end if;result <= LCD_symbol;end process;

end Behavioral;

This process receives data from LCD,which can be generated when you touch

the panel. See slide 7

A B C D

1 Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University,...

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Transcript of 1 Copyright (c) 2003 by Valery Sklyarov and Iouliia Skliarova: DETUA, IEETA, Aveiro University,...