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Controllers-system for APS – CubeSat

nano-satellite

Instructor: Daniel Alkalay

Students: Moshe Emmer & Meir Harar

Technion – Israel Institute of TechnologyDepartment of Electrical EngineeringHigh Speed Digital Systems Lab

Presentation - Final

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Agenda

• Project Goals – Second semester• Architecture/Interface• Implementation - Demo• FSL• FSM – watch dog• Summary

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Project Goals• APS – Cubesat is a multidisciplinary project .

It involves AE and EE disciplines.

• Main task is to build a distributed system-on-chip architecture, using heterogeneous processing units.

• Each processor performs a different task.

• A proprietary serial communication protocol is implemented between the processors.

• Scope is on architecture abstract level.

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CubeSat - Architecture / FINAL GOAL

SA I/F& Bat C/D-Control

Battery

Attitude System Sensors & actuators

Magneto-meter

מד שמש

Rate Gyro

מגנטו-טורקרים

Engines

Sensors

Actuators

Accurate Positioning

System

שעון אטומי

APS & TLMTransCeiver

PowerDistribution

Over-current control

TLMTT+C

Attitude Control

On-BoardControllers

uBlaze+ pBlaze+

State-Machines

Power

Control

Telemetry

S&A

I/F

Payload

TLM

TLM

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System implementation - DEMO

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Hardware

Microblaze_0

BRAM_0I-LMB Cntrl D-LMB Cntrl

UARTRS -232

OPB

I-LMB

D-LMB

… …

DIP_Switches_8Bit

Led_7SEGMENT

Push_Buttons_3Bit

LEDs_8Bit

OPB

Tested and studied, not included in design

Tested and studied - included in design

L.M.B – Local Memory Bus

Peripherals – OPB IP’s

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MicroBlaze – Soft processor for FPGA

MicroBlaze Core Block Diagram

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UART Lite

• A module that attaches to the OPB.• One transmit and one receive channel (full duplex).• 16-character transmit FIFO and 16-character receive FIFO.• Configurable baud rate.• Parameters:

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FSL (Fast Simplex Link) Bus

Microblaze_0 Microblaze_1

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• Up to 8 master and slave FSL interfaces are available on the MicroBlaze soft processor.

• Supports both synchronous and asynchronous FIFO modes – allows the master and slave side of the FSL to clock at different rates.

• Provides an external control bit for annotating data being transmitted – can be used by the slave side interface for multiple purposes. For example, use the bit to indicate the start or end of the transmission of a frame.

We used this bus to transfer data between three soft processors implemented on the same chip

Technical Features

FSL_aMaster_a Slave_b

Master_bSlave_aFSL_b

Microblaze_0 Microblaze_1

FSL (Fast Simplex Link) Bus

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System implementation - DEMO

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FSM – watch dog

• extend system’s physical robustness•Especially important in a SPACE environment Creating an independent closed-loop algorithm, which verifies system’s

Demands

BEGIN      CASE current_state IS         WHEN reset =>             IF ((mic_0 AND mic_1 AND mic_2) = '1') THEN                next_state <= s1;            ELSE               next_state <= s2;             END IF;

         WHEN s1 <=            

IF (NOT ( mic_0 OR mic_1 OR mic_2 ) = '1') THEN

               next_state <= reset;            ELSE

               next_state <= s2;             END IF;

         WHEN s2 =>             next_state <= s2;         WHEN OTHERS =>

            next_state <= reset;      END CASE;

   END PROCESS nextstate_proc;

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System implementation - DEMO

• An implementation of 3 independent controllers (3x MicroBlaze) will be demonstrated.

• Each processor executes a different task (arithmetic task): Division, Subtraction and Addition.

• Demonstrating data transfer between three processors.One of them is connected to Hyper-Terminal (through UART).

• A special macro function was created in order to support multi- packets transfer between the processors (aerospace wise).

• A system-wide watch-dog test, using FSM, was implemented to monitor the ‘health’ of the processors.

MSB – Print Screen from EDK

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Summary

• Design must first start in the architecture abstract level, especially when using FPGA technology

• In a system of various tasks, each can be implemented by an independent controller, while all will be communicating according to a protocol, defined by the designers

• On 1 Virtex-4, FPGA chip, one can implement many independent processing units; such as MicroBlazes, PicoBlazes, FSMs and

other hardware modules. All can carry out different tasks and exchange data using a Fast, simple method – FSL bus

• It is also possible to break one mission into N different processes, using N different cores and raising performance by N*100 %

(upper bound value!)

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Summary

• FSL is a FIFO, 1-way bus that can smoothly answer any communication needs of the processing units. It can be activated either under a non-blocking or a blocking regime. Each, of course has its own advantages and disadvantages. blocking is the simple way, giving fast and un-complex design

• Think of the endless opportunities! With a FPGA chip and a good understanding of the architecture one can gain boost in performance of a process by using parallel cores!

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Summary

A system using MicroBlaze and FSL links tocommunicate between them has been developed, andwith the experiments tested it can be concluded thatthe FSL links are an ideal choice for exchanging databetween processors due to their high speed datatransfer rates

Analysing the synthesis results, it is clear that whatlimits the number of processors in a multiprocessordesign on FPGA is the amount of BlockRAMavailable, not the total size of the FPGA.

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SummaryCompletely Meshed

A completely meshed networkis a network in which each node is connected to everyother node in the network. It is a good way to reducethe traveling time of packets over a network, becausedata goes directly from sender to receiver, but itsmain disadvantage is that the number of links growsextremely quickly when the number of nodes isincreased. A completely meshed network topologywith MBlaze and FSL links will only be possible forjust 9 MBlazes, because of the limitation of 8 FSLlinks for each MicroBlaze processor.

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SummaryRing Network A ring network is a network in whicheach node in the network is connected to thefollowing and the preceding node in the network,forming a ring. Data is passed from node to nodeuntil it reaches the destination node. With MBlazeand FSL links there will not be a size limit for thenetwork, because each MBlaze would just use 2 FSLlinks. The main problem of this topology is that datatransfers from two nodes that are far from each otherare very time consuming.