1 Compacting Test Vector Sets via Strategic Use of Implications Kundan Nepal Electrical Engineering...

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Compacting Test Vector Sets via Strategic Use of

Implications

Kundan Nepal

Electrical Engineering

Bucknell UniversityLewisburg, PA

Nuno Alves, Jennifer Dworak, and Iris

Bahar

Division of Engineering Brown

University Providence, RI

ICCAD 2009 - Section 2A: Advances in Test Efficiency - November 2, 2009

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Goal and Motivation• Goal: Reduce the number of test vectors while maintaining the same test coverage

• Why important?

• Test time is expensive

• Smaller feature sizes devices increased logic amount increased test data volume

• Increased complexity of defects and process variations require more circuit testing

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Related techniques

• ATPG

• Static and dynamic compaction techniques

• Design for testability

• Built In Self Test (BIST)

• Scan chains (with on-chip decompression)

• Test Points

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Our previous work

•Use of logic implication checkers, inserted in hardware, as a means of compacting n-detect test sets

•“Using implications for online error detection,” in ITC08

•“Detecting errors using multi-cycle invariance information,” in DATE09

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Invariant relationships in circuits

n1

n2n3

n4n5

n6n7

n8

1

0

n5=1 n8=0

00

0

X

X

0 0

X

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Error detection with implications

n5=1 & n8=1 will generate an error in

checker logic

n1

n2n3

n4n5

n6n7

n8

ERROR

n5=1 n8=0

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Implication Violations Can Detect Errors

Appropriate checker logic can detect multiple errors with a single implication.

n1

n2n3

n4n5

n6n7

n8

ERROR

= Stuck@1 faultn5=1 n8=0

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Implications for Online Error Detection

•Our algorithm automatically identifies implications in circuits

•Implication selection can be constrained by hardware overhead or delay

•For several circuits, we can detect almost 90% of all errors that propagate to a primary output

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Implications for test vector compaction

•Why are test vector sets large?

•Certain faults in a circuit are hard to detect

•A circuit with many hard to detect faults requires lots of test vectors

•How can implications help?

•Implications may make faults easier to observe, therefore pattern count can be reduced

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Why Do We Want to Detect Faults Multiple Times?•Faults targeted during test are not perfect models of “real world” defects.

• Each “real world” defect may have its own requirements for detection.

•However certain observation requirements overlap.

•By observing a site multiple times, you have multiple opportunities to meet additional requirements for detecting real defects.

To detect the OR bridge with a test for A s-a-1, B

must equal 1.

OR bridge:

Observation could be satisfied by observation of A s-a-1

Excitation requires satisfying an additional constraint

A

S

B

F

P

Q

A OR B bridge

0/1

A s-a-1

11/1

0/0

0/1

0/0

0/1

0

10/0

Defects & Faults May Not Match

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To detect the OR bridge with a test for A s-a-1, B

must equal 0.

If we observe a site multiple times with different test patterns we increase our chances of fortuitously exciting whatever un-modeled defect may be present.

A

S

B

F

P

Q

A OR B bridge

0/1

A s-a-1

11/1

0/0

0/1

0/0

0/1

0

01/1

Defects & Faults May Not Match

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Implications generate additional fault observations

•Circuit rd73 (MCNC91), has 700 faults and 7 inputs

•We report the fault observations after all 128 vectors were simulated

Number of faults that were detected

circuit Once Twice > Fiverd73 164 96 361

rd73 + 1% implications

153 87 384

rd73 + 5% implications

137 69 433

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•So far,

•We’ve introduced implications

•Shown that implications can make faults easier to detect

•Now,

• Can we not only use implications for on-line error detection, but also to reduce test vector size?

Selecting implications for test

Algorithm Setup

•Goal: Find the implications that yield the largest reduction of patterns

circuit

ATPG Run

15-detect vectors

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•Calculate Implications: Using circuit simulation and SAT-based verification, discover all implications in the circuit

Discover implications

Creating Fault

DictionariesATPG Run

15-detect vectors

circuit

Compress implications

•Compress Implications: Remove dominated and low quality implications

Create Fault Dictionaries

(f×p matrices)

•For each implication, create an individual fault dictionary with the 15-detect vectors

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Implication Selection

ATPG Run

15-detect vectors

circuit


•For each fault dictionary, implication selection algorithm determines which vectors may be safely deleted while keeping 15 detects•Add the best performing implication to the original circuit and repeat the process

Implication Implication selection alg.selection alg.

Selected implications


(f×p matrices)

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Selection Algorithm: An Example

•2-Detect patterns: Fault propagate at least twice

• Red square indicates a fault that was propagated to a primary output (PO)

Fau

lt

Pattern

Original Circuit

1 2 3 4 5

1

2

3

4

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•Circuit with implication has more propagated faults

•Pattern 4 is no longer required for 2-detections. With implication #1 only 4 vectors are required.

1 2 3 4 5

1

2

3

4

Fau

lt

Pattern

Circuit with Implication #1

Fau

lt

Pattern

Original Circuit

1 2 3 4 5

1

2

3

4

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•For each implication, the algorithm continues to calculate the minimum number of 2-detect vectors

Fau

lt

Pattern

Fau

lt

Pattern

Original Circuit

1 2 3 4 5

1

2

3

4

1 2 3 4 5

1

2

3

4

1 2 3 4 5

1

2

3

4

1 2 3 4 5

1

2

3

4

1 2 3 4 5

1

2

3

4

1 2 3 4 5

1

2

3

4

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•Once we find the best implication, which gives the best 2-detect vector count reduction, we add it to the original circuit

•We then restart the process

Fau

lt

Pattern

Circuit with Implication #1

Fau

lt

Pattern

Original CircuitCircuit + 1 Implication

1 2 3 4 5

1

2

3

4

1 2 3 4 5

1

2

3

4

1 2 3 5

1

2

3

4

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Experimental Setting

ATPG Run

15-detect vectors

circuit


•Stuck-at fault model

•Benchmarks from ISCAS85 and MCNC91

•ATPG tool: Mentor Graphics FastScan

•Synthesis Tool: Mentor Graphics Leonardo Spectrum

Implication Implication selection alg.selection alg.

Selected implications


(f×p matrices)

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Vector count reduction

HW overhead Average Reduction1% 8%5% 17%

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Online error detection and pattern reduction for different HW overheads

The implication checker can have a dual purpose

Circuit

Test Patterns% Undetected error [ITC08]

Orig. 10% 20% 10% 20%C432 537 492 8.4% 462 14.0% 7.2% 4.5%C499 793 793 0.0% 793 0.0% 16.9% 13.7%C880 320 297 7.2% 297 7.2% 22.6% 19.1%C1908 1699 1581 6.9% 1581 6.9% 14.3% 13.1%

b12 375 363 3.2% 362 3.5% 12.3% 9.7%clip 755 736 2.5% 712 5.7% 11.0% 10.2%

misex2 1220 1216 0.3% 1216 0.3% 12.8% 9.5%rd73 1057 1007 4.7% 947 10.4% 7.2% 6.3%

Z5xp1 679 661 2.7% 624 8.1% 14.5% 11.5%Z9sym 1115 1016 8.9% 1010 9.4% 5.6% 5.2%

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Conclusions•Logic implications can be used for online error detection and test

•Implications optimized to reduce average pattern count:

•8% Reduction (1% HW)

•17% Reduction (5% HW)

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Future Work

•Create more sophisticated implication selection algorithms

•Develop algorithms that optimize implication selection for online error detection and test together

•Use of cross-cycle implications

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Compacting Test Vector Sets via Strategic Use of

Implications

Nuno Alves (speaker) - [email protected]

Kundan Nepal - [email protected]

Jennifer Dworak - [email protected]

Iris Bahar - [email protected]

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Implications and delay

circuitOld

Delay (ns)

New Delay (ns)

Delay change(

ns)C432 3.21 3.25 0.04

C499 2.49 2.51 0.02

C880 2.15 2.22 0.07

C1908 3.29 3.44 0.15

b12 0.53 0.53 0

clip 0.89 0.89 0

misex2 0.69 0.69 0

rd73 0.97 1.02 0.05

Z5xp1 1.05 1.08 0.03

Z9sym 1.02 1.04 0.02

• Circuits with added implications corresponding to 5% HW overhead

•TSMC 180nm Model

• Preserved Critical path

• Delay was increased an average of 2%

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