1 Circuit Switching in the Core OpenArch April 5 th 2003 Nick McKeown Professor of Electrical...

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1 Circuit Switching in the Core OpenArch April 5 th 2003 Nick McKeown Professor of Electrical Engineering and Computer Science, Stanford University [email protected] www.stanford.edu/~nickm
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Transcript of 1 Circuit Switching in the Core OpenArch April 5 th 2003 Nick McKeown Professor of Electrical...

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High PerformanceSwitching and RoutingTelecom Center Workshop: Sept 4, 1997.

Circuit Switching in the CoreOpenArch

April 5th 2003

Nick McKeownProfessor of Electrical Engineering and Computer Science, Stanford University

[email protected]/~nickm

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Circuit switching today

Modems, DSL

SONET/SDHDWDM

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Trend 1 Disparity of router capacity and traffic Disparity of router capacity and line rate Reduction in cycles per packet

Conclusion: Routers will get simpler

Trend 2 Backbone networks have low utilization Utilization will decrease Statistical multiplexing is less important than it was

Observation: Circuit switches are simpler

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Recent trends

1

10

100

1,000

10,000

100,000

1,000,000

1980 1983 1986 1989 1992 1995 1998 2001

Nor

mal

ized

Gro

wth

sin

ce 1

980

Moore’s Law2x / 18 months

Router Capacity2.2x / 18months

Line Capacity2x / 7 months

User Traffic2x / 12months

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Recent trends

1

10

100

1,000

10,000

100,000

1,000,000

1980 1983 1986 1989 1992 1995 1998 2001

Nor

mal

ized

Gro

wth

sin

ce 1

980

DRAM Random Access Time1.1x / 18months

Moore’s Law2x / 18 months

Router Capacity2.2x / 18months

Line Capacity2x / 7 months

User Traffic2x / 12months

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Future trendsIf traffic doubles every year

0

250

500

750

1000

2002 2004 2006 2008 2010 2012

1

Cost and complexity of five times as

many central offices is prohibitive

GAP OF 5x!!Trafficx2 / yr

Router Capacityx2.2 / 18mo

Moore’s Lawx2 / 18mo

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Capacity limited by power

0

1

2

3

4

5

6

1990 1993 1996 1999 2002

Power

(kW

)

approx...

Power consumption will exceed network operator limits

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Packet processing gets harder

time

Inst

ruct

ion

s p

er

arr

ivin

g b

yte

What we’d like: (more features)QoS, Multicast, Security, …

What will happen

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Packet processing gets harder

0

100

200

300

400

500

600

700

1996 1997 1998 1999 2000 2001

Clock cycles per minimum length packet since 1996

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Why the Internet usedpacket switching

Efficient use of expensive links: “Circuit switching is rarely used for data networks, ...

because of very inefficient use of the links” – Bertsekas & Gallager ‘92

Resilience to failure of links & routers: ”For high reliability, ... [the Internet] was to be a

datagram subnet, so if some lines and [routers] were destroyed, messages could be ... rerouted” – Tanenbaum ‘96

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Bandwidth efficiency

Reality: Internet avg. link utilization: 5-20% [Coffman &

Odlyzko’02] There is a glut of BW in the core [WSJ’00]

Result: Packets more efficient, but BW is no longer

a scarce resource

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Reliability

Argument: because of the state, rerouting a circuit is more costly than with packets

Reality: Internet availability:

1220 min/year down time [Labovitz’99] Phone availability:

5 min/year down time [Kuhn’97]

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Reliability

Reality (cont.): IP recovers in about 3 min (median), sometimes it

takes over 15 min [Labovitz’01] SONET required to recover in less than 50 ms

Result: No evidence packet switching is more robust

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Low complexity

Argument: No per-flow state => packet switching is simpler

Reality: PS: 8M lines of code in core router

[Cisco’s IOS ‘00] CS: 18M lines of code in telephone switch [AT&T/Lucent

5ESS ‘96] CS: 3M lines of code in transport switch [’01]

Result: Packet switching does not seem inherently less complex

than circuit switching

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Router linecard

PhysicalLayer

Framing&

Maintenance

PacketProcessing

Buffer Mgmt&

Scheduling

Buffer Mgmt&

Scheduling

Buffer & StateMemory

Buffer & StateMemory

OC192c linecard

30M gates 2.5Gbits of memory 1m2

$25k cost, $120k price.

LookupTables

Optics

SchedulerScheduler

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Functions in a packet switch

Interconnect scheduling

Route lookup

TTL proces

sing

Buffering

Buffering

QoS schedu

ling

Control plane

Ingress linecard Egress linecardInterconnect

Framing

Framing

Data path

Control path

Scheduling path

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Functions in a circuit switch

Interconnect scheduling

Control plane

Interconnect

Framing

Framing

Ingress linecar

d

Egress linecard

Data path

Control path

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Low complexity

Argument: IP does not have the signaling of circuits switches => Routers go faster

Reality: IP does almost same operations on every packet as a

circuit switch on the circuit establishment CS has no work to do once circuit is established

Result: The fastest commercially-available circuit switches [Ciena

’01, Lucent ‘01] have 5x the capacity of the fastest routers [Cisco ’01, Juniper ’02]

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Circuit switches…

Do not process packets, Do not buffer packets, Consume less power (typically 75% less per

Gb/s), Fit more capacity in one rack (typically 4-8x), Are, in practice, simpler, more reliable and

more resilient, Cost less (typically 75% less per Gb/s), Can be built using optics, Are already in widespread use at the core of

the Internet.Prediction: Internet will evolve to become edge routers interconnected by rich mesh of WDM circuit switches.