1 Chapter 1 and 2 Computer System and Operating System Overview –The Evolution of Operating...
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Transcript of 1 Chapter 1 and 2 Computer System and Operating System Overview –The Evolution of Operating...
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Chapter 1 and 2Computer System and Operating System
Overview– The Evolution of Operating Systems– OS Objectives and Functions– Instruction Execution– Interrupts– The Memory Hierarchy– Cache Memory– I/O Communication Techniques
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Evolution of Operating Systems
• It may be easier to understand the key requirements of an OS by considering the evolution of Operating Systems
• Stages include– Serial Processing– Simple Batch Systems– Multiprogrammed Batch Systems– Time Sharing Systems
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Serial Processing(late 1940s to mid-1950s)
• No operating system
• Machines run from a console with display lights,
toggle switches, input device, and printer
• Problems include:
– Scheduling using a hardcopy sign-up sheet
– Setup time• loading complier and source program into memory
• saving the object program
• loading and linking object program and common functions
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Simple Batch System(mid-1950s)
• Early computers were extremely expensive– Important to maximize processor utilization
• Monitor– Software that controls the sequence of events– Batch jobs together– Program returns control to monitor when
finished
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Monitor’s perspective
• Monitor controls the sequence of events
• Resident Monitor is software always in memory
• Monitor reads in job and gives control
• Job returns control to monitor
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Multiprogrammed Batch Systems
• CPU is often idle – Even with automatic job sequencing.– I/O devices are slow compared to processor
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Uniprogramming
• Processor must wait for I/O instruction to complete before preceding
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Multiprogramming
• When one job needs to wait for I/O, the processor can switch to the other job
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Multiprogramming
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Time Sharing Systems(early 1960s)
• Using multiprogramming to handle multiple interactive jobs
• Processor’s time is shared among multiple users
• Multiple users simultaneously access the system through terminals
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Batch Multiprogramming vs. Time Sharing
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Early Example: CTSS
• Compatible Time-Sharing System (CTSS) – Developed at MIT as project MAC
• Time Slicing:– When control was passed to a user– User program and data loaded– Clock generates interrupts about every 0.2
sec– At each interrupt OS gained control and could
assign processor to another user
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CTSS Operation
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Roadmap
– The Evolution of Operating Systems
– OS Objectives and Functions– Instruction Execution– Interrupts– The Memory Hierarchy– Cache Memory– I/O Communication Techniques
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Operating System
• A program that controls the execution of application programs
• An interface between applications and hardware
• Main objectives of an OS:– Convenience– Efficiency– Ability to evolve
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Layers and Views
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OS as Service Provider
• Program development– e.g., editors and debuggers
• Program execution• Access I/O devices• Controlled access to files• System access for shared systems• Error detection and response
– e.g., memory error, device failure, division by zero
• Accounting for resources and performance monitoring
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OS as Resource Manager
• A computer is a set of resources for the movement, storage, and processing of data.
• The OS is responsible for managing these resources.
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OS as Resource Manager
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Roadmap
– The Evolution of Operating Systems– OS Objectives and Functions
– Instruction Execution– Interrupts– The Memory Hierarchy– Cache Memory– I/O Communication Techniques
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Instruction Execution
• A program consists of a set of instructions stored in memory
• Two steps– Processor reads (fetches) instructions from
memory– Processor executes each instruction
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Example of Program Execution
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Roadmap
– The Evolution of Operating Systems– OS Objectives and Functions– Instruction Execution
– Interrupts– The Memory Hierarchy– Cache Memory– I/O Communication Techniques
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Interrupts
• Interrupt the normal sequencing of the processor
• Provided to improve processor utilization– Most I/O devices are slower than the
processor– Processor must pause to wait for device
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Flow of Control without Interrupts
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Interrupts and the Instruction Cycle
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Transfer of Control via Interrupts
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Instruction Cycle with Interrupts
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I/O Wait
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Simple Interrupt Processing
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Changes in Memory and Registers for an Interrupt
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Multiprogramming
• Processor has more than one program to execute
• The sequence the programs are executed depend on their relative priority and whether they are waiting for I/O
• After an interrupt handler completes, control may not return to the program that was executing at the time of the interrupt
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Roadmap
– The Evolution of Operating Systems– OS Objectives and Functions– Instruction Execution– Interrupts
– The Memory Hierarchy– Cache Memory– I/O Communication Techniques
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Memory Hierarchy
• Major constraints in memory– Amount– Speed– Expense
• Faster access time, greater cost per bit
• Greater capacity, smaller cost per bit
• Greater capacity, slower access speed
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The Memory Hierarchy
• Going down the hierarchy– Decreasing cost per bit– Increasing capacity– Increasing access time– Decreasing frequency of
access to the memory by the processor
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Secondary Memory
• Auxiliary memory
• External
• Nonvolatile
• Used to store program and data files
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Roadmap
– The Evolution of Operating Systems– OS Objectives and Functions– Instruction Execution– Interrupts– The Memory Hierarchy
– Cache Memory– I/O Communication Techniques
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Cache Memory
• Processor must access memory at least once per instruction cycle– Processor speed faster than memory access
speed
• Exploit the principle of locality with a small fast memory– Data which is required soon is often close to
the current data. If data is referenced, then it’s neighbour might be needed soon.
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Cache Principles
• Contains copy of a portion of main memory
• Processor first checks cache– If not found, block of memory read into cache
• Because of locality of reference, likely future memory references are in that block
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Cache/Main-Memory Structure
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Cache Read Operation
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Cache Design Issues
• Main categories are:– Cache size– Block size– Mapping function– Replacement algorithm– Write policy
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Size issues
• Cache size– Small caches have significant impact on
performance
• Block size– The unit of data exchanged between cache
and main memory– Larger block size means more hits – But too large reduces chance of reuse.
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Mapping function
• Determines which cache location the block will occupy
• Two constraints:– When one block read in, another may need
replaced– Complexity of mapping function increases
circuitry costs for searching.
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Replacement Algorithm
• Chooses which block to replace when a new block is to be loaded into the cache.
• Ideally replacing a block that isn’t likely to be needed again– Impossible to guarantee
• Effective strategy is to replace a block that has been used less than others– Least Recently Used (LRU)
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Write policy
• Dictates when the memory write operation takes place
• Can occur every time the block is updated
• Can occur when the block is replaced– Minimize write operations– Leave main memory in an obsolete state
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Roadmap
– The Evolution of Operating Systems– OS Objectives and Functions– Instruction Execution– Interrupts– The Memory Hierarchy– Cache Memory
– I/O Communication Techniques
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I/O Techniques
• When the processor encounters an instruction relating to I/O, – it executes that instruction by issuing a
command to the appropriate I/O module.
• Three techniques are possible for I/O operations:– Programmed I/O– Interrupt-driven I/O– Direct memory access (DMA)
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Programmed I/O
• The I/O module performs the requested action – then sets the appropriate bits in the I/O status
register – but takes no further action to alert the
processor.
• As there are no interrupts, the processor must determine when the instruction is complete
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Programmed I/O Example
• Data read in a word at a time– Processor remains in status-
checking loop while reading
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Interrupt-Driven I/O
• Processor issues an I/O command to a module – and then goes on to do some other useful
work.
• The I/O module will then interrupt the processor to request service when it is ready to exchange data with the processor.
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Interrupt-Driven I/O
• Eliminates needless waiting– But everything passes
through processor.
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Direct Memory Access
• Performed by a separate module on the system
• When needing to read/write, processor issues a command to DMA module with:– Whether a read or write is requested – The address of the I/O device involved– The starting location in memory to read/write– The number of words to be read/written
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Direct Memory Access
• I/O operation delegated to DMA module
• Processor only involved when beginning and ending transfer.
• Much more efficient.