1 Boolean Algebra and Logic Gates EE 240 – Logic Design Chapter 2 Sohaib Majzoub.
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Transcript of 1 Boolean Algebra and Logic Gates EE 240 – Logic Design Chapter 2 Sohaib Majzoub.
1
Boolean Algebra and Logic GatesBoolean Algebra and Logic Gates
EE 240 – Logic Design
Chapter 2
Sohaib Majzoub
2
Logic Functions: Logic Functions: Boolean AlgebraBoolean Algebra
INVERTER
X X’
X X’0 11 0
If X=0 then X’=1If X=1 then X’=0
OR
AB
C=A+B
A B C0 0 00 1 11 0 11 1 1
If A=1 OR B=1 then C=1 otherwise C=0
AB
C=A·B
A B C0 0 00 1 01 0 01 1 1
If A=1 AND B=1 then C=1 otherwise C=0
AND
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Axioms of Boolean AlgebraAxioms of Boolean Algebra
If X ≠ 0 then X = 1 If X ≠ 1 then X = 0
If X = 0 then X’ = 1 If X = 1 then X’ = 0
0 . 0 = 0 1 + 1 = 1
1 . 1 = 1 0 + 0 = 0
0 . 1 = 1 . 0 = 0 0 + 1 = 1 + 0 = 1
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Boolean expressions and logic circuitsBoolean expressions and logic circuits
Any Boolean expression can be implemented as a combination of AND, OR, and NOT
X = [A’.(C+D)]’+B.E
CD
C+D[A’.(C+D)]’ [A’.(C+D)]’+B.E
BE
B.E
A’.(C+D)
A’A
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Basic TheoremsBasic Theorems
X+0 = X
X0
C=XX 0 C0 0 01 0 1
X+1 = 1
X1
C=1X 1 C0 1 11 1 1
X0
C=0
X·0 = 0
X 0 C0 0 01 0 0
X1
C=X
X·1 = X
X 1 C0 1 01 1 1
Identity Law
Null Element
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Basic Theorems:Basic Theorems:Idempotent LawsIdempotent Laws
X+X = X
XX
C=XX X C0 0 01 1 1
XX
C=X
X·X = X
X X C0 0 01 1 1
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Basic Theorems:Basic Theorems: Involution Law Involution Law
X
(X’)’=X
BC=X
X B C0 1 01 0 1
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Basic Theorems:Basic Theorems:Laws of ComplementarityLaws of Complementarity
X+X’ = 1
XX’
C=1X X’ C 0 1 1 1 0 1
XX’
C=0
X·X’ = 0
X X’ C0 1 01 0 0
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Expression Simplification using the Expression Simplification using the Basic TheoremsBasic Theorems
X can be an arbitrarily complex expression.
Simplify the following boolean expressions as much as you can using the basic theorems.
(A.B’ + D).E + 1 =(A.B’ + D).(A.B’ + D)’ =(A.B + C.D) + (C.D + A) + (A.B + C.D)’ =
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Associative LawAssociative Law
(X+Y)+Z = X+(Y+Z)
X Y Z X+Y (X+Y)+Z Y+Z X+(Y+Z)0 0 0 0 0 0 00 0 1 0 1 1 10 1 0 1 1 1 10 1 1 1 1 1 11 0 0 1 1 0 11 0 1 1 1 1 11 1 0 1 1 1 11 1 1 1 1 1 1
XY
ZC
YZ
XC
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Associative LawAssociative Law
(XY)Z = X(YZ)
X Y Z XY (XY)Z YZ X(YZ) 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 1 1 1
XY
ZC
YZ
XC
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First Distributive LawFirst Distributive Law
X(Y+Z) = XY+XZ
X Y Z Y+Z X(Y+Z) XY XZ XY+XZ 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1
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Second Distributive LawSecond Distributive Law
X+YZ = (X+Y)(X+Z)
X Y Z YZ X+YZ X+Y X+Z (X+Y)(X+Z) 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
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Second Distributive LawSecond Distributive Law(A different proof)(A different proof)
(X + Y)(X + Z) = X(X + Z) + Y(X + Z) (using the first distributive law)
= XX + XZ + YX + YZ (using the first distributive law)
= X + XZ + YX + YZ (using the idempotent law)
= X·1 + XZ + YX + YZ (using the operation with 1 law)
= X(1 + Z + Y) + YZ (using the first distributive law)
= X·1 + YZ (using the operation with 1 law)
= X + YZ (using the operation with 1 law)
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Distributive LawDistributive Law(Another formula)(Another formula)
X.Y + Z.W = (X+Z).(X+W).(Y+Z).(Y+W)
X.Y + Z.W.V =(X+Z).(X+W).(X+V).(Y+Z).(Y+W).(Y+V)
Proof?
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More TheoremsMore Theorems
XY + XY’ = XXY + XY’ = X(Y + Y’) = X·1 = X
X + XY = XX(1 + Y) = X·1 = X
(X + Y)(X + Y’) = X(X + Y)(X + Y’) = XX + XY’ + YX + YY’ = X + X(Y’ + Y) + 0 = X + X·1 = X
X(X + Y) = XX(X + Y) = XX + XY = X·1 + XY = X(1 + Y) = X·1 = X
Combining Theorem
Covering or Absorption Theorem
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The Consensus TheoremThe Consensus Theorem
XY + X’Z + YZ = XY + X’Z
= XY + X’Z + (X + X’)YZ
= XY + X’Z + XYZ + X’YZ
= XY + XYZ + X’Z + X’YZ
= XY(1 + Z) + X’Z(1 + Y)
= XY·1 + X’Z·1
XY + X’Z + YZ = XY + X’Z + 1·YZ
= XY + X’Z
(X+Y)(X’+Z)(Y+Z) = (X+Y)(X’+Z)
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First DeMorganFirst DeMorgan’’s s LawLaw
The complement of the sum is equal the product of the complements.
(X+Y)’ = X’Y’
XY
Z
X Y X+Y (X+Y)’ X’ Y’ X’Y’ 0 0 0 1 1 1 1 0 1 1 0 1 0 0 1 0 1 0 0 1 0 1 1 1 0 0 0 0
Z
Y
X
XY Z X
YZ
Four Different Equivalents of NOR Gate
19
Second DeMorganSecond DeMorgan’’s s LawLaw
The complement of the product is equal the sum of the complements.
(XY)’ = X’ + Y’
ZXY
X Y XY (XY)’ X’ Y’ X’ + Y’0 0 0 1 1 1 10 1 0 1 1 0 11 0 0 1 0 1 11 1 1 0 0 0 0
Z
Y
X
Four Different Equivalents of NAND Gate X
Y Z XY
Z
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Generalized DeMorganGeneralized DeMorgan’’s Lawss Laws
De Morgan’s laws generalize to n variables:
(X1 + X2 + X3 + ··· + Xn)’ = X1’X2’X3’ ··· Xn’
(X1X2X3 ··· Xn)’ = X1’ + X2’ + X3’ + ··· + Xn’
21
DeMorganDeMorgan’’s Law (example)s Law (example)
Express the complement f’(w,x,y,z) of the following expression in a simplified form.
f(w,x,y,z) = wx(y’z + yz’)
f’(w,x,y,z) = w’ + x’ + (y’z +yz’)’
= w’ + x’ + (y’z)’(yz’)’
= w’ + x’ + (y + z’)(y’ + z)
= w’ + x’ + yy’ + yz + z’y’ + z’z
= w’ + x’ + 0 + yz + z’y’ + 0
= w’ + x’ + yz + y’z’
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Principle of DualityPrinciple of Duality
• Any theorem or identity in switching algebra remains true if and + are swapped.
• The dual of a boolean function F is called FD
• It apply to all theorems that we worked with so far
• FD(X1,X2,…,Xn,+,.,’) = F(X1,X2,…,Xn,.,+,’)
• Parentheses has to be added to clarify precedence rules before the conversion
23Principle of DualityPrinciple of Duality
• Example: DeMorgan’s Laws – the second law is the dual of the first law
(X+Y)’ = X’Y’ (X Y)’ = X’ + Y’
• Another Example: Covering Theorem
X + X Y = X
The dual is: X X + Y = X
X + Y = X WRONG!!! Why?
Use parentheses to avoid problems X+(X.Y) then X.(X+Y)
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Positive and Negative LogicPositive and Negative Logic
Positive Logic: the higher voltage (+V) represents 1 and the lower voltage (0V) represents 0
Negative Logic: the higher voltage (+V) represents 0 and the lower voltage (0V) represents 1
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Positive and Negative Logic (example)Positive and Negative Logic (example)
LogicGate
e2
e3
e1
eo
The same physical circuit implements different logicfunctions. The function implemented depends on the logic used to interpret the inputs and outputs.
e1 e2 e3 eo
0V 0V 0V 0V0V 0V +V 0V0V +V 0V 0V0V +V +V 0V+V 0V 0V 0V+V 0V +V 0V+V +V 0V 0V+V +V +V +V
+
Electric Voltages
e1 e2 e3 eo
0 0 0 00 0 1 00 1 0 00 1 1 01 0 0 01 0 1 01 1 0 01 1 1 1
+
Positive Logic
e1 e2 e3 eo
1 1 1 11 1 0 11 0 1 11 0 0 10 1 1 10 1 0 10 0 1 10 0 0 0
+
Negative Logic
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NAND: A Functionally Complete Logic GateNAND: A Functionally Complete Logic Gate
A C=(A·A)’ = A’
A B C 0 0 1 0 1 1 1 0 1 1 1 0
NAND
We can create all three gates (AND, OR, NOT) from NAND
AB
C=(A·B)’
NAND as an Inverter
NAND as an ANDAB
(A·B)’
C= (A’.B’)’ = A+BNAND as an ORB
A’
B’
A
C= ((A.B)’)‘= A.B
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Is NOR Functionally Complete?Is NOR Functionally Complete?
• Prove it yourself!
AB C = (A+B)’
A B C 0 0 1 0 1 0 1 0 0 1 1 0
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Exclusive OR, X-OR, or XORExclusive OR, X-OR, or XOR
X Y = XY’ + X’YX Y C0 0 00 1 11 0 11 1 0
If X=1 OR Y=1, butnot both of them, then C=1
XY
C
X 0 =
X 1 =
X X =
X X’ =
Commutative Law:X Y = Y X
Associative Law:(X Y) Z= X ( Y Z) = X Y Z
Distributive Law:X(Y Z) = XY XZ
X
X’
0
1
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Exclusive-OR (cont.)Exclusive-OR (cont.)
Complement Law:(X Y)’ = X Y’ = X’ Y
X Y X’ Y’ XY (XY)’ XY’ X’Y0 0 1 1 0 1 1 10 1 1 0 1 0 0 01 0 0 1 1 0 0 01 1 0 0 0 1 1 1
Algebraic Proof:(X Y)’ = (XY’ + X’Y)’
= (XY’)’(X’Y)’= (X’ + Y)(X + Y’)= X’X + X’Y’ + XY + YY’= 0 + X’Y’ + XY + 0
= X’ Y= X’Y’ + XY= XY + X’Y’ = X Y’
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Equivalence GateEquivalence Gate
(X Y) = XY + X’Y’X Y C0 0 10 1 01 0 01 1 1
If X=Y then C=1,otherwise C=0
(X Y) = (X Y)’
XY
C
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Switch Networks and Switch DesignSwitch Networks and Switch Design
• Basic Ideal Switch: simplest structure in a computing system is a switch
• Path exists between INPUT and OUTPUT if Switch is CLOSED or ON
• Path does not exist between INPUT and OUTPUT if SWITCH is OPEN or OFF
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Switches in SeriesSwitches in Series
Truth Table
S1 S2 Path?
AND Configuration
33
Switches in ParallelSwitches in Parallel
Truth Table
S1 S2 Path?
OR Configuration
34
CMOS SwitchesCMOS Switches
• The idea is to use the series and parallel switch configurations to route signals in a desired fashion.
• Unfortunately, it is difficult to implement an ideal switch as given.
• Complementary Metal Oxide Semiconductor (CMOS) devices give us some interesting components.
(INPUT)
(OUTPUT) (INPUT)
(OUTPUT)
35
CMOS Transfer CharacteristicsCMOS Transfer Characteristics
nMOS when CLOSED• Transmits logic level 0 well• Transmits logic level 1 poorly
pMOS when CLOSED• Transmits logic level 1 well• Transmits logic level 0 poorly
36
CMOS Transmission GateCMOS Transmission Gate
37
CMOS Transmission GateCMOS Transmission Gate
38High Impedance High Impedance ZZ
• With switches, we can consider three states for an output:– Logic-0– Logic-1– High Impedance Z
• Path exists for Logic-0 and Logic-1 when the switch is CLOSED.
• High impedance is a state where the switch is OPEN.
39High Impedance High Impedance ZZ
• Another way of thinking of switches is as follows:– Path exists for Logic-0 and Logic-1 when the switch is
CLOSED, meaning that the impedance/resistance is small enough to allow ample flow of current.
– High impedance is a state where the switch is OPEN, meaning that the impedance/resistance is very large allowing nearly no current flow.
40
Inverter (NOT) NetworkInverter (NOT) Network
Pull-Up
Pull-Down
Pull-Up Pull-Down
A B
01
A B
01
1Z 0
Z
A B
01 0
1
Truth Table
Inverter (NOT) Gate
B = A’ = A A B
41
NAND NetworkNAND Network
Pull-Up Pull-Down
A B C
0 0
Truth Table
0 1
1 0
1 1
A B C
0 0
0 1
1 0
1 1
A B C
0 0
0 1
1 0
1 1
NAND (NOT AND) Gate
C = (A.B)’ = (AB)’ = ABAB
C
42
NOR NetworkNOR Network
Pull-Up Pull-Down
A B C
0 0 1
Truth Table
0 1 Z
1 0 Z
1 1 Z
A B C
0 0 Z
0 1 0
1 0 0
1 1 0
A B C
0 0 1
0 1 0
1 0 0
1 1 0
NOR (NOT OR) Gate
C = (A+B)’ = (A+B)’ = A+BA
BC
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AND NetworkAND Network
C
NAND Inverter
Truth Table
A B C
0 0 0
0 1 0
1 0 0
1 1 1
AND Gate
C = A.B = ABAB
C
44
OR NetworkOR NetworkNOR Inverter
C
Truth Table
A B C
0 0 0
0 1 1
1 0 1
1 1 1
OR Gate
C = A+BA
BC
45XOR NetworkXOR Network
Truth Table
A B C
0 0 0
0 1 1
1 0 1
1 1 0
XOR (Exclusive OR) Gate
C = A B = AB’ + A’B
A
BC
46XNOR (Equivalence) NetworkXNOR (Equivalence) Network
C
Truth Table
A B C
0 0 1
0 1 0
1 0 0
1 1 1
XNOR or Equivalence Gate
C = A B = AB + A’B’
A
BC
A
BC