09_DesignAutomation

8/12/2019 09_DesignAutomation

1/52

Lecture 10

Design Automation

ENGR 3430 Digital VLSI

Mark L. Chang

Spring 07


2/52

181

A Textbook on Design Automation

Sherwani, N. A.

Algorithms for VLSI Physical Design Automation

Many of the figures here come from the book, and:

Scott Hauck, University of Washington

Kia Bazargan, University of Minnesota


3/52

182

Full Custom

We get exactly what we want.


4/52

183

Standard Cell

Predefined gates with

standard form factor


5/52

184

Gate Arrays


6/52

185

Programmable Array of Logic


7/52

186

Field-Programmable Gate Arrays


8/52

187

Physical Design

CAD = Computer Aided Design

Todays circuits are too

complex to do all full custom

CAD is split into two parts:

Synthesis

translating high-level design

into a circuit

Physical Design

translating the circuit into a

layout

Partitioning

Floorplanning

Placement

Global Routing

Detailed Routing

Compaction


9/52

188

History of CAD


10/52

189

Partitioning

Circuits can exceed a chips capacity

Or, want to reclaim some hierarchy in

the design

Partitioning

Floorplanning

Placement

Global Routing

Detailed Routing

Compaction


11/52

190

Floorplanning

Assign portions of the circuit

to physical regions on the chip

Want to reduce routing delay

and area of designPartitioning

Floorplanning

Placement

Global Routing

Detailed Routing

Compaction


12/52

191

Placement

Pick physical location of each gate

Optimize for delay and area

Partitioning

Floorplanning

Placement

Global Routing

Detailed Routing

Compaction


13/52

192

Global Routing

Determine loose route for each net

Assign a routing region to each net

Partitioning

Floorplanning

Placement

Global Routing

Detailed Routing

Compaction


14/52

193

Detailed Routing

Find actual geometric layout of each

net within the assigned routing region

Partitioning

Floorplanning

Placement

Global Routing

Detailed Routing

Compaction


15/52

194

Compaction

Give it that last squeeze

Squish out any free space due

to non-optimality in all

previous algorithms

Partitioning

Floorplanning

Placement

Global Routing

Detailed Routing

Compaction


16/52

195

Why Partition?

Decomposition of a complex system into smaller

subsystems

Done hierarchically

Partitioning done until each subsystem has manageable size

Each subsystem can be designed independently Interconnections between partitions minimized

Less hassle interfacing the subsystems

Communication between subsystems usually costly

Partitioning may be necessary at alllevels of design

System, Board, Chip, Circuit


17/52

196

Partitioning Algorithms


18/52

197

Kernighan-Lin

Group Migration

or bisectioning

algorithm

Input graph is partitioned

into two equal parts Until the cutsize stops improving

Swap pairs of vertices that improve cutsize

Lock them down

If no improvement possible, exchange pairs that increase

cutsize the least


19/52

198

Floorplanning

Why?

Early stage of physical design

Determines the location of large blocks

detailed placement easier (divide and conquer!)

Estimates of area, delay, power important design decisions

Impact on subsequent design steps (e.g., routing, heat

dissipation analysis and optimization)

How?

Many different algorithms


20/52

199

Floorplan Classes

Slicing (recursively defined)

A floorplan that can be partitioned

into two slicing floorplans with a

horizontal or vertical cut line

Non-Slicing

Superset of slicing floorplans Contains the wheel shape too

1234567

167 2345

234 5167

43

6 27 34

1 3

4

5

2

67

Slicing

floorplan

Corresp.Slicing

tree

Non-Slicingfloorplan


21/52

200

Example

Hierarchical floorplan of order 5

Templates

Floorplan and tree

L5 R5

3

8 5

7

34

6

87

1

2

5

R5

1 6 2

4


22/52

201

Generic Hierarchical Algorithm

Form a tree with defined fanout restriction

For each node (bottom up) select best grouping

Minimize area, reduce routing delay (estimated)

Cluster nodes based on connectivity

Or, top-down, recursively partition logic Limit number of nodes in a partition

Form partitions on min-cut lines

Floor planning not always used for standard cell Fixed cell sizes mean floor planning is just placement But still used to break up the problem


23/52

202

Placement

Why?

Placement is the heart of physical design

Determines routing to the first order

Bad placement means bad everything else

What? Pick relative location of each gate

Reduce area and wiring delay

How?

Standard-sized cells placed in rows

Estimate routing needs


24/52

203

Placement Goals


25/52

204

Placement Algorithms

Top Down

Partitioning-based placement

Recursive bi-partioning or quadrisection

Iterative improvement

Simulated annealing Force-directed

Constructive

Start with a few cells in the center

Place highly connected cells around them


26/52

205

Force-Directed

Model

Wires as springs

Solve set of linear equations to find initial placement

Seek to minimize forces on each node

Increase spring constant for critical nodes Must avoid overlapping cells, or collapsing to a point

Use repelling force between unconnected cells

Do not allow moves that result in an overlap

Use repelling forces from areas of congestion


27/52

206

Force-Directed

Model (details):

Cell distances: either

OR:

Forces:

Objective: find x,y coordinates for all cells such that total

force exerted on each cell is zero.

|||| jiijjiij yyyxxx !="!="

22 )()( jijiij yyxxd !+!="

)()(11

ij

n

j

ij

i

yij

n

j

ij

i

x ykFxkF "#!="#!= $$==


28/52

207

Annealing

Cooling hot metals to form good crystalline structures

Start at high temperatures atoms move about randomly

Cool metal, leaving enough time for atoms to attract into

crystal lattice


29/52

208

Simulated Annealing

Move nodes (gate position assignments) randomly

Initial high temperature allow bad moves to happen

Lower temperature accept fewer bad moves

Slowly cool placement to allow good structure to form


30/52

209

Placement Cost Function

Most use Manhattan routing (NSEW, no diagonals)

A

A

A

B

B

C

C

C

Wirelength estimate = 0.5 * (perimeter of bounding box)


31/52

210



A

A

A

B

B

C

C

C



32/52

211



A

A

A

B

B

C

C

C



33/52

212



A

A

A

B

B

C

C

C



34/52

213



A

A

A

B

B

C

C

C


5

7

8

11 14

10


35/52

214



A

A

A

B

B

C

C

C


5

7

8

11 14

10

1912

24


36/52

215

SA Cost Function

Simulated Annealing requires a cost function that

captures quality of placement

Smaller cost means better placement

Multiple concerns captured in one metric

Simple example

Might add

Row imbalance penalty

Overlap penalty

Row length

Area estimation

delaypathcriticalciperimetersemicplacementcostnetsi

__*)()(21

+! "=#


37/52

216

Acceptance Criteria

After we obtain a new placement:

delta = cost(oldPlacement) cost(newPlacement)

if( delta >= 0 )

accept

else if ( random < edelta/temperature ) // 0


38/52

217

Acceptance Criteria

random < edelta/temperature

Higher temperatures lots of bad moves accepted

Lower temperatures fewer bad moves tolerated


39/52

218

Cooling Schedule

Initial temperature is very high

Most bad moves accepted

Temperature slowly goes to 0, attempting many moves

at each temperature

Run several iterations at temperature=0 Only accept good moves

Greedily quench the system


40/52

219

Simulated Annealing Algorithm


41/52

220

Practical Issues for SA

Cost function

Cost function must be carefully developed (fractal & smooth)

Cost function evaluation must be fast

Balancing quality and runtime requires lotsof testing

Move function Efficient random node selection

Maybe use area windowing

Cooling schedule

Moves per temp, starting temp, cooling rate, freezing point?

Takes lotsof testing


42/52

221

Global Routing

Determine loose route for each net

Assign a routing region to each net

Partitioning

Floorplanning

Placement

Global Routing

Detailed Routing

Compaction


43/52

222

Global Routing

Objectives

Minimize total channel

height

Assign feedthroughs

Minimize maximum wirelength

Minimize maximum path length


44/52

223

Problem Formulation

Utilize a grid abstraction so we can apply graph theory

Coarse vs. fine grained

Vertices: routing regions. Edges: existence of route

Optional weighting of edges

t1 t2 t3t4

t1 t2 t3t4

1 1 1

1 1 1

2 2 1 1

t1 t3t4

t2


45/52

224

Global Routing Algorithms

Sequential: one net at a time

Concurrent: all nets considered simultaneously


46/52

225

Maze Routing


47/52

226

Maze Routing

Pros

Simple

Easy to implement

Guaranteed to find an optimal solution

Can incorporate complex cost functions (along edges)

Cons

Not great for multiple-terminal nets

Large memory requirements if not programmed carefully


48/52


49/52

228

A* (A-Star) Maze Routing


50/52

229

Multi-Terminal Maze Routing


51/52

230

Minimum Spanning Tree


52/52

231

Minimum Steiner Tree

09_DesignAutomation

Documents

Transcript of 09_DesignAutomation