09/02/2012
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09/02/2012 1 Delay Chip Prototype & SPI interface Joan Mauricio La Salle (URL) 15/02/2013
description
Delay Chip Prototype & SPI interface. Joan Mauricio La Salle (URL) 15/02/2013. 09/02/2012. 1. Delay Chip Overview. Reset Block. rst. nRst. coarse. Mux. clkINT . VCDL+Mux. clkT&H . clkRef. Phase Comp + Charge Pump. nRst. Config. Status. SPI Slave. - PowerPoint PPT Presentation
Transcript of 09/02/2012
09/02/2012 1
Delay Chip Prototype & SPI interface
Joan Mauricio
La Salle (URL)
15/02/2013
15/02/2013 2
Delay Chip Overview
SPI Slave
ResetBlock
Mux
VCDL+Mux
Phase Comp +
Charge PumpConfig Status
VCDL+MuxConfig
rst nRstcoarse
coarse vControl
clkRef
clkINT<3:0>
clkT&H<3:0>
clkADC<3:0>
vControl<3:0>
Analog Config
Digital Config
LVDS Clock
CMOS Clock
Slow Control
!en, clk din, dout
nRst
nRst
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Delay Chip Features
– SPI Slave interfaces with the SPI Master and generates:– Register Select.– Read / !Write.
– Serial Registers:– 16 Bits RW (Config. Registers).– 8 Bits RO (Status Registers).
– 4 DLL Channels:– 1 Phase Comparator + Charge Pump per Channel.– 2 Config. + 1 Status Register per Channel.– 3 independent LVDS Clk outputs per Channel. 24 pads!!!
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Slow Control – SPI Slave
– SPI Modes:– We are currently implementing Mode 1.
Mode CPOL CPHA
0 0 0
1 0 1
2 1 0
3 1 1
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Slow Control – SPI Slave State Machine
– SEU tolerant State Machine:– Hamming distance between Idle and critical states is 2.
Idle state spiEn = ‘0’
If 1-bit SEU occurs:
E100, E100, E111 E101
Pump Rst
Addr Dec
Reg Selection
Not in Idle state afeter
reset!!!!
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Slow Control – SPI Slave Features
– SPI Mode 1.
– No ‘dead’ cycles between Addresses and Data.
– Up to 64 Selectable Registers (32 Config. + 32 Status): Only 8 Config. + 4 Status used in this chip.
– SDI / SDO Bypass for troubleshooting purposes.
– Charge Pumps can be reset via software.
– SEU tolerant.
– Area = 340x73 um2 .
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Slow Control – SPI Addresses
ADDR ICECAL Ch Width Description
0x00 0 16 INT / T&H Clk Conf.
0x01 0 16 ADC Clk Conf.
0x02 1 16 INT / T&H Clk Conf.
0x03 1 16 ADC Clk Conf.
···
0x10 2 16 INT / T&H Clk Conf.
0x11 2 16 ADC Clk Conf.
0x12 3 16 INT / T&H Clk Conf.
0x13 3 16 ADC Clk Conf.
···
0x40 Any - Charge Pump Reset
···
0xA0 0 8 Status Reg.
0xA1 1 8 Status Reg.
0xB0 2 8 Status Reg.
0xB1 3 8 Status Reg.
···
0xFF - - SDI / SDO Bypass
R/!W Pump Rst Status/!Conf RSEL4 RSEL3 RSEL2 RSEL1 RSEL0
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Slow Control – Configuration Registers (16b)
– RW Registers.
– No state machine is required.
– 16 Bits.
– Signals:– Preset (Hardware)– Register Select– R/!W– Serial Clock– Serial Data Input– Serial Data Output (tristated)
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Slow Control – Status Registers (8b)
– RO status bits (no memory).
– No state machine is required.
– 8 Bits.
– Signals:– Register Select– Serial Clock– Serial Data Output (tristated)
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Slow Control – Conf. Reg. Write Simulation
110 1 000 1
100000 1 00000000 1
1 0 0 1 1 0 1 0 0 0 1 1 0 0 0 1
– Write = 0x9A31.
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Slow Control – Conf. Reg. Read Simulation
100000 1 00000000 1
1 0 0 1 1 0 1 0 0 0 1 1 0 0 0 1
1 0 0 1 1 0 1 0 0 0 1 1 0 0 0 1
– Read = 0x9A31.
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Slow Control – Status Reg. Read Simulation
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
1 1 0 1 0 0 0 1
– Read = 0xD1.
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Delay Chip Prototype
– Next Run @ 13/03/2013 – Europractice.
– New test board (Analog Mezzanine) is being designed.
– Some changes needed in the FEB FPGA:–SPI Master capability (opencores.org).–Interface between CAT and SPI block.–4 Pins needed (5 if the board has two SPI Slaves).
