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Documentation of a digital system provides the necessary information for

building, testing, operating , and maintaining the system.

Generally, documentation include: A Specification that describes what the

circuit is supposed to do.

A block diagram showing the inputs, outputs, the main building blocks or modules of the system and how they are connected.

A schematic diagram showing all the components, their types, and all interconnections.

A timing diagram showing the logic signals as a function of time.

A structured logic device description showing the operation of the structure

A Circuit description explaining of the operation of the logic circuit.

Documentation

Standards

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Basic Rules of Block Diagram

A block diagram must show the most

important system elements and how

they work together.

Each block diagram should not be more

than 1 page.

Large systems may require additional

block diagrams of individual

subsystems. A subsystem is another

block that has a whole system in it.

Important control signals and buses in

the block diagram should have names.

Flow of control and data should be

clearly indicated.

The schematic diagram inside the block

need not to be shown.

Documentation

Standards

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Block Diagram

shows all inputs and outputs, the

building blocks, their function names,

and the data flow paths or the logic

signals.

Related logic signals are combined

together and drawn with a double or

heavy line, known as a bus

Example: Min/Max Circuit

Documentation

Standards

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Documentation

Standards

Schematic Diagram

Things to follow in doing schematic

diagrams:

Details of component inputs, outputs, and interconnections

Reference designators

Pin numbers

Gate symbols

Signal names and active levels

Bubble-to-Bubble Logic Design

Layouts

Logic diagram: An informal drawing

without this level of details.

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Documentation

Standards

Example of Schematic Diagram

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Documentation

Standards

Active Levels

Each signal name should have an

active-level associated with it, normally

it is a + or symbol that denotes high or low.

A signal is active-high if it performs the

named action or denotes the named

condition when its HIGH or 1. A signal is active-low if it performs the named

action or denotes the named condition

when its LOW or 0.

Different naming conventions for active

levels are available.

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Documentation

Standards

Signal Names

Signal name is a descriptive

alphanumeric label for each

input/output signal.

In real system, well-chosen names

convey information to readers.

A signal name indicates

An action that is controlled like ENABLE, REQUEST, GO, PAUSE

A condition that it detects such as READY_L, ERROR,

Data that it carries, such as INBUS[31..0], ADDR[150]

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Documentation

Standards

Active Levels Naming Conventions

Active low signal has a suffix of _L as

part of the variable name.

Example:

ERROR is an active high which

means there is an error when the

signal is HIGH ( logic 1).

READY_L is an active low which

means the data is ready when the

signal is LOW ( logic 0).

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Documentation

Standards

Example of Naming Conventions

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Documentation

Standards

Active Levels for Pins The outline of a logic symbol, means that the

given logic function is occurring inside that

outline.

In logic gates and logic structures the inversion bubble indicates the active level of the signal

Examples:- 2-to- 4 Decoder

- EN_L is active low

- A and B are active high

- Y0_L, Y1_L, Y2_L,Y3_L are active low

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Documentation

Standards

Signal Name, Logic Expression, Logic Equation

A signal name uses any variable name

in alphanumeric label.

A logic expression combines signal

names using switching algebra

operators such as AND,OR, and NOT

A logic equation is an assignment of a

logic expression to a signal name. It

describe one signals function in terms of other signals.

For example: READY_L, READY are

signal names. READY is a logic expression.

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Documentation

Standards

Bubble-to-Bubble Logic Design Rules

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Documentation

Standards

Drawing Layouts

Inputs to the left/top, outputs to the

right/bottom.

Signals flow from left to right (or top to

bottom).

Signal paths should be connected.

Broken signal paths should be flagged

to indicate the source or destination

and direction.

Crossing lines/Connected lines (T-type

connection)

Multiple pages schematics:

Flat Structure

Hierarchical Structure

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Documentation

Standards

Hierarchical Schematic Structure

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Documentation

Standards

Drawing Layout: Flat Schematic Structure

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Documentation

Standards

Rules to avoid common errors in signal convention:

Use exactly the same name for same

signal. Use different names for different

signals. (especially cross pages)

Use appropriate active levels for signal

names

Use T convention for connected lines.

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Documentation

Standards

Buses

Buses should be named : DATA[0:7],

CONTROL

A bus name may use brackets and a colon to

denote a range

Buses are drawn with thicker lines than

ordinary signals.

Individual signals are put into or pulled out

of the bus by connecting an ordinary signal

line to the bus and writing the signal name.

(A special connection dot is often used.)

A signal extracted from a bus should be

named

Inter-page signal/Bus Flags:

Uni-direction

Bi-direction

Example of buses:

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Programmable Logic

Devices

Why PLDs?

Fact:

It is most economical to produce an IC in large volumes

But:

Many situations require only small volumes of ICs

Many situations require changes to be done in the field, e.g. Firmware of a

product under development

A programmable logic device can be:

Produced in large volumes

Programmed to implement many different low-volume designs

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Programmable Logic

Devices

An integrated circuit with internal logic gates and/or connections that can be

changed by a programming process

Examples of PLD:

PROM

Programmable Logic Array (PLA)

Programmable Array Logic (PAL) device

Complex Programmable Logic Device (CPLD)

Field-Programmable Gate Array (FPGA)

A PLDs function is not fixed

Can be programmed to perform

different functions

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Programmable Logic

Devices

PLD Hardware Programming Technologies

In the Factory - Cannot be

erased/reprogrammed by user

Mask programming (changing the VLSI mask) during manufacturing

Programmable only once

Fuse

Anti-fuse

Reprogrammable (Erased &

Programmed many times)

Volatile - Programming lost if chip power lost

Single-bit storage element

Non-Volatile - Programming survives power loss

UV Erasable

Electrically Erasable

Flash (as in Flash Memory)

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Programmable Logic

Devices

Used symbol in PLD

Most PLD technologies have gates with

very high fan-in

Fuse map: graphic representation of

the selected connections

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Decoder

Truth Table of 2-to-4 Decoder

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Decoder

Accepts a value and decodes it

Output corresponds to value of n

inputs

A decoder is consists of:

Inputs (n)

Outputs (2n , numbered from 0 2n -

1)

Selectors / Enable (active high or active

low)

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Decoder

2-to-4 Decoder

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Decoder

Truth Table of 3-to-8 Decoder

A2A1A0D0D1D2D3D4D5D6D7

0 0 0 1

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 1

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Decoder

Combinational Circuit Design with Decoders

A decoder provides an output of 2n

minterms (sum of products) with n

input variables

Any Boolean function can be expressed

as a sum of minterms at the output

A decoder and external OR gates can be

used to implement any combinational

function.

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Decoder

3-to-8 Decoder

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Encoders

Perform the inverse operation of a decoder

2n (or less) input lines and n output

lines

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Encoders

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Encoders

Can be implemented with 3 OR gates

A0 = D1 + D3 + D5 + D7;

A1 = D2 + D3 + D6 + D7;

A2 = D4 + D5 + D6 + D7;

If more than 2 inputs are active we need

to use

priority encoder (priority for inputs)

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Encoders

Encoders with OR Gates

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Encoders

Priority Encoder

Accepts multiple input values instead

of just having one input that is high,

and encodes them

Works when more than one input is active

Consists of:

Inputs (2n)

Outputs

when more than one input is active, sets output to correspond to

highest input

Selectors / Enable can still be active high or active low

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Encoders

Decoder Encoder

2^n-to-n encoder

Input code : 1-out-of-2^n.

Output code : Binary Code

n-to-2^n

Input code : Binary Code

Output code :1-out-of-2^n.

Binary decoders/encoders

Encoder vs. Decoders

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Multiplexer

Multiplexer: 2-to-1

S = 0 selects I0

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Multiplexer

A multiplexer switches (or routes) data from 2N inputs to one output, where N

is the number of select (or control)

inputs.

A multiplexer (mux) is a digital switch with multiple inputs and one output. It

is also considered as a circuit that is

many to one. It selects what input

signal goes sequentially to the output

link.

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Multiplexer

Multiplexer: 2-to-1 with Enable

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Multiplexer

Multiplexer: 4-to-1

Y = (I0.s

1's

0') + (I

1.s

1's

0) + (I

2.s

1s

0') + (I

3.s

1s

0)

Two select signals

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Multiplexer

MUX: Designing Logic Circuits

Each row in a Truth Table of a

multiplexer corresponds to a minterm

with N-inputs

Each minterm can be mapped to a

multiplexer input, so there will also be

N minterns

For each row in the Truth Table, where

the output of the function is one (F = 1),

Set the corresponding input of the

multiplexer to 1

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Multiplexer

Multiplexer 4-to-1

0

w 0

w 1

0

1

w 2

w 3

0

1

f 0

1

s 1

s

Select signal for

first level of decoders

Select signal for

second level of decoders

2-to-1 Muxes

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Multiplexer

MUX: Designing Logic Circuits Efficiently

Each row in a Truth Table corresponds

to a minterm

N-input Truth Table

A product term of N-1 variables can be

mapped to each of the multiplexer

inputs

(N-1)-input Multiplexer

For the rows in the Truth Table,

Group N-1 highest order inputs into pairs

Define the output of each pair using the Nth input

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Multiplexer

MUX: Designing a Logic Circuit

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Demultiplexer

It is a circuit that switches (r routes data from one input to 2N outputs,

where N is the number of select

inputs.

It performs the opposite function of a multiplexer.

It is also considered as a circuit that has many one to many outputs.

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Multiplexer

MUX: Designing a Logic Circuit

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Demultiplexer

Demultiplexer: 1-to-4

I

s1

s0

O0

O1

O2

O3

0

1

2

3

S1S0O

0

O

1

O

2

O

3

0 0 I 0 0 0

0 1 0 I 0 0

1 0 0 0 I 0

1 1 0 0 0 I

O0

= S1'.S

0'.I

O1

= S1.S

0'.I

O2

= S1'.S

0.I

O3

= S1.S

0.I

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Exclusive OR and

Exclusive NOR Gates

XOR :

XNOR :

Truth Table :

XOR

X Y XOR XNOR

0 0 0 1

0 1 1 0

1 0 1 0

1 1 0 1

XOR

X

Y

F

X

Y

F

'' YXYXYX

'')'( YXYXYX

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Exclusive OR and

Exclusive NOR Gates

XOR Application: Parity Circuit

Odd Parity Circuit : The output is 1 if

odd number of inputs are 1

Even Parity Circuit : The output is 1 if

even number of inputs are 1

Example : 4-bit Parity Circuit

Input: 1101 Odd Parity output : 0

Even Parity output : 1

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Exclusive OR and

Exclusive NOR Gates

XOR and XNOR Symbols

Equivalent Symbols of XOR Gate

Equivalent Symbols of XNOR Gate

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Equality Comparator

XNOR

X

Y

Z

Z = !(X $ Y)

X Y Z

0 0 1

0 1 0

1 0 0

1 1 1

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Equality Comparator

4-Bit Equality Comparator

A 0

A 1

A 2

A 3

B 0

B 1

B 2

B 3

A _ E Q _ B

C 0

C 1

C 3

C 2

FIELD A = [A0..3];

FIELD B = [B0..3];

FIELD C = [C0..3];

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4-Bit Magnitude Comparator

Equality Comparator

MagnitudeDetector

A[3..0]

B[3..0]

A_EQ_B

A_LT_B

A_GT_B

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4-Bit Equality Detector

Equality Comparator

EqualityDetector

A[3..0]

B[3..0]

A_EQ_B

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Equality Comparator

TTL Comparators

1

2

3

4

5

6

7

9

10 11

12

8

19

20

17

18

15

16

13

14

GND

Vcc P>Q

P0

Q0

P1

Q1

P2

Q2

P3

Q3

P=Q

Q7

P7

Q6

P6

Q5

P5

Q4

P4

74LS682

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16

GND

Vcc B3

ABin

A>Bout

A=Bout

A

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Equality Comparator

Cascading Two Comparators

A 3 A 2 A 1 A 0 A 7 A 6 A 5 A 4

B 3 B 2 B 1 B 0 B 7 B 6 B 5 B 4

+ 5 V

A < B

A = B

A > B

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Equality Comparator

4-Bit Magnitude Comparator

X Y

1101 0110

1110 1011

1011 1011

0101 0111

1010 1011

gt = 1

eq = 1

lt = 1

1-bit comp1-bit comp1-bit comp1-bit comp

x0

y0

x1

y1

x2

y2

x3

y3

Lin=0

Gin=0

lteqgt

G1G

2G3

L3 L2 L1

L4

G4 G0

L0

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Equality Comparator

1-Bit Magnitude Comparator

The variable Eout is 1

if A = B and Gin = 0 and Lin = 0. The variable Gout is 1

if A > B or if A = B and Gin = 1.

The variable Lout is 1

if A < B or if A = B and Lin = 1.

Gin

Lin

Gout

Eout

Lout

y

1-bit

comparator

x

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Adders, Subtractors,

and ALU

Half Adder: Adds two 1-bit operand

Truth Table

YXHS

YXCO

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Adders, Subtractors,

and ALU

Full Adders: Provide for carries between bit positions

Basic building block is full adder

1-bit-wide adder, produces sum and carry outputs

Truth table:

X Y Cin S Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

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Adders, Subtractors,

and ALU

Ripple Adder

Speed limited by carry chain

Faster adders eliminate or limit carry

chain

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Adders, Subtractors,

and ALU

Full Adder Circuit

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Adders, Subtractors,

and ALU

Subtraction

Subtraction is the same as addition of

the twos complement.

The twos complement is the bit-by-bit complement plus 1.

Therefore, X Y = X + Y + 1 , subtraction can be performed by using

adder circuits.

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Adders, Subtractors,

and ALU

Full Subtractor = Full Adder, almost

X,Y are n-bit unsigned binary numbers

Addition : S = X + Y

Subtraction : D = X - Y = X + (-Y) =

= X+ (Twos Complement of Y)= X+ (Ones Complement of Y) + 1= X+ Y+ 1

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Adders, Subtractors,

and ALU

Arithmetic Logic Units (ALU)

An arithmetic-logic unit, or ALU,

performs many different arithmetic and

logic operations. The ALU is the heart of a processor

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Adders, Subtractors,

and ALU

Using Adder as a Subtractor

Ripple Adder can be used as a

Subtractor by inverting Y and setting

the initial carry ( CIN ) to 1

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