06387701

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 32, NO. 1, JANUARY 2013 87

Leakage and Aging Optimization UsingTransmission Gate-Based Technique

Ing-Chao Lin, Member, IEEE, Chin-Hong Lin, Student Member, IEEE, and Kuan-Hui Li

Abstract—Negative bias temperature instability (NBTI), whichcan degrade the switching speed of PMOS transistors, has becomea major reliability challenge. Reducing leakage consumptionis one of the major design goals. The gate replacement (GR)technique is an effective way to reduce both the NBTI effect andleakage. This technique, however, has less flexibility because thereplaced gate can only produce one output value and carefulalgorithms are needed to decide the output value of the replacedgate. In this paper, we propose a novel transmission gate-basedtechnique to minimize NBTI-induced degradation and leakage.This technique, which can offer logic 1 for NBTI mitigationand logic 0 for leakage reduction, provides higher flexibility, ascompared to the GR technique. Simulation results show thatour proposed technique has up to 20× and 2.16×, on average,improvement on NBTI-induced degradation with comparableleakage power reduction. With a 19.19% area penalty, combiningour technique and the GR can reduce 17.92% of the total leakagepower and 32.36% of NBTI-induced circuit degradation.

Index Terms—Aging, degradation mitigation, leakage reduc-tion, negative bias temperature instability (NBTI), static timinganalysis, transmission gate.

I. Introduction

W ITH REDUCED threshold voltage and thinner gate-oxide thickness, leakage power consumption has in-

creased exponentially. Many studies have shown that leakageconsumes up to 40% of total power consumption. Hence,leakage has been a first class concern in advanced processtechnology. Also, as technology advances, and transistor sizesshrink, negative biased temperature instability (NBTI) hasbecome a major reliability concern. NBTI can increase thethreshold voltage of PMOS transistors. With increased thresh-old voltage and reduced driving current, the switching speedof the transistors slows down. In the long term, this can causetiming violation and system failure [3]. NBTI has been shown

Manuscript received October 13, 2011; revised January 24, 2012 and May17, 2012; accepted July 16, 2012. Date of current version December 19,2012. This work was supported in part by the National Science Councilof Taiwan under Grants NSC 99-2221-E-006-222 and 100-2221-E-006-177.A preliminary version of this paper was presented at the 2011 IEEE/ACMInternational Symposium on Low Power Electronics and Design [8]. Thispaper was recommended by Associate Editor D. Sylvester.

I.-C. Lin and K.-H. Li are with the Department of Computer Scienceand Information Engineering, National Cheng Kung University, Tainan 701,Taiwan (e-mail: [email protected]; [email protected]).

C.-H. Lin was with the Department of Computer Science and InformationEngineering, National Cheng Kung University, Tainan 701, Taiwan. He is nowdoing his military service.

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCAD.2012.2214478

Fig. 1. Schematic view of the NBTI effect.

to be the major reliability limiting factor when the gate oxideis thinner than 4 nm [9].

The analysis of the NBTI effect is more complicated thanother traditional reliability issues, such as hot-carrier injection[12], as it includes stress and recovery phases. Fig. 1 showsthe schematic view of the NBTI effect. The stress phaseoccurs when a PMOS transistor is under a negatively biasedcondition, i.e., V GS=−V DD. In this situation, the interactionbetween the inversion layer holes and the hydrogen-passivatedSi atoms breaks the Si–H bond generated during the oxidationprocess. Then, the H atom converts into H2 molecules. WhenH2 molecules diffuse away, interface traps are left. Wheninterface traps accumulate between silicon and the gate oxideinterface, they cause a shift in the threshold voltage.

However, in the recovery phase, when the biased voltage isremoved, the reverse reaction is performed. Some hydrogendiffuses back toward the interface and bonds with Si, whichreduces the number of interface traps and the NBTI effect.Although the recovery phase can reverse the NBTI effect, itdoes not eliminate all the interface traps generated during thestress phase, and the PMOS threshold voltage will increase inthe long term.

When PMOS is under constant stress, this situation is calledstatic NBTI. On the contrary, if both stress and recovery phasesexist, this condition is called dynamic NBTI. The thresholdvoltage increases when the circuit is in an active mode andcan be estimated using dynamic NBTI models. However, whenthe circuit is clock gated or enters a standby mode, it isaffected by static NBTI. Fig. 2 shows static and dynamic NBTIdegradation for different input signal probabilities for 65 nmPMOS transistors. The input signal probability is defined asthe probability that input signal is at logic 0. When the inputsignal probability is 1, it means the PMOS transistor’s inputsignal is constant 0, and the PMOS transistor is under constantstress. It can be observed that static NBTI is significantlyhigher than dynamic NBTI. In order to correctly predict the

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88 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 32, NO. 1, JANUARY 2013

Fig. 2. Static and dynamic NBTI degradation for different input signalprobabilities [14].

NBTI effect on circuit degradation, it is important to estimateboth dynamic and static NBTI effects. One example is thatin [13], only a 3% circuit degradation saving is obtained atthe 90 nm technology. Part of the reason for this is that thedifferences in the NBTI effects during active and standby timesare not considered.

Many techniques have been proposed to mitigate the NBTIeffect. Bhardwaj et al. [1] proposed a model for the long-termdegradation of the threshold voltage under dynamic stress asa function of time and other design parameters. This papershowed that temperature can significantly affect NBTI, andexperiments have indicated that at higher temperatures thedegradation under stress is faster, but recovery is slower. In[10], the authors proposed a method for characterizing thedelay of every gate in the standard cell library as a functionof the signal probability of each input. A technology mappingtechnique that considered the NBTI effect was proposed toguarantee the performance of the circuit during its lifetime.They also concluded that delay degradation caused by theNBTI effect is dependent on the signal probability. For ex-ample, when the input signal to a CMOS inverter changesfrom logic 0 to logic 1, the PMOS relaxes from stress modeto recovery mode.{, #3} The recovery mode can reduce thecircuit degradation due to the NBTI effect, and it is importantto consider the effect of recovery on the overall NBTI impact.Wu et al. [19] proposed a joint logic restructuring and pinreordering method that is based on detecting functional sym-metries and transistor stacking effects. They also proposed anNBTI optimization method that considered path sensitization[20].

These studies, however, have only considered NBTI whena circuit is in active mode. In addition, not many works onthis topic have attempted to optimize NBTI and leakage at thesame time. Input vector control (IVC) [5], [7], [21], [22] isa well-studied technique used in the circuit standby mode toreduce leakage power consumption. This technique is based onthe observation that the leakage current in a CMOS logic gateis dependent on the gate input state. However, this techniqueis less effective when paths in circuits become deeper becausegates with deep levels are less likely to be affected by theinput vector. One way to improve the controllability is thegate replacement (GR) technique used in [22]. This technique

replaces a gate that is in its worst leakage gate by another gate,while keeping the circuit’s correct functionality in the activemode. A similar technique is the internal node control (INC)technique in which the output of a gate is forced to a specificvalue. Both the GR and INC techniques utilize transistor stackeffects and are effective ways to reduce leakage.

These two techniques can also be used to mitigate NBTIeffects. Bild et al. [2] used the INC technique to mitigate NBTIdegradation. They proposed a mixed integer linear programfor an optimal solution and a linear-time heuristic methodto quickly find a near-optimal solution. However, they didnot attempt to reduce the leakage power at the same time.Instead, Wang et al. [14], [15] proposed fast GR algorithms,together with optimal input vector selection, to simultaneouslyreduce NBTI-induced circuit degradation and leakage powerconsumption.

The problem with both methods is that the extra delayincurred by modified gates is not clearly considered. When agate is modified, the delay of the gate itself will increase, andthe total path delay will increase. Therefore, it is necessaryto carefully examine the timing effect of modified gates onthe critical path. Another issue is that in order to maximizeleakage reduction and NBTI degradation optimization, it isnecessary to understand the most important critical gates thatrequire protection. Focusing on the most critical gates canfurther reduce the area overhead since the number of replacedgates is reduced.

In this paper, we propose a technique that can mitigatethe leakage power consumption and circuit degradation dueto the NBTI effect. The contributions of this paper can besummarized as follows.

1) A novel technique that can reduce NBTI effect andleakage: The technique inserts a transmission gate anda pull up or down transistor in front of the gates, and itforces the inputs of the gates to the desired state. Thistechnique has higher flexibility to connect the fan-outgates before or after the transmission gate to achieveless path delay increase with similar leakage reductioncompared to the GR algorithm. Another benefit is thatthe extra delay incurred by the transmission gate isindependent of the gate type.

2) Algorithms that can insert the transmission gates effi-ciently: In order to achieve efficient NBTI mitigationand leakage power reduction, we propose a transmissiongate insertion algorithm that consists of both an NBTImitigation algorithm and a leakage reduction algorithmin order to determine where the transmission gate shouldbe inserted to control the gate’s input states.

3) NBTI and leakage cosimulation framework: We developa framework to estimate dynamic NBTI and static NBTI.The framework integrates NBTI-aware static timinganalysis that identifies critical paths after aging. Thisframework also takes advantage of the critical gateinformation so that the number of critical gates thatrequires modification is reduced.

4) Comprehensive analysis and comparison with relatedwork: We provide comprehensive result comparisons

LIN et al.: LEAKAGE AND AGING OPTIMIZATION USING TRANSMISSION GATE-BASED TECHNIQUE 89

TABLE I

�Vth Predictive Model for NBTI

Static A(

(1 + δ)tox +√

C(t − t0))2n

Dynamic Stress(Kv(t − t0)0.5 + 2n

√�Vth0

)2n

Recovery �Vth0

(1 − 2ξ1te +

√ξ2C(t − t0)

2tox +√

Ct

)

with the GR technique [15]. Our experimental resultsshow that compared with the GR technique, our pro-posed technique has up to 20× and 2.16×, on average,improvement on NBTI-induced degradation on the sameleakage power reduction. Finally, the combination ofour technique and GR can reduce 17.92% of the totalleakage power and 32.36% of NBTI-induced circuitdegradation.

The remainder of this paper is organized as follows. Sec-tion II introduces the related work. Section III introduces thetransmission gate-based technique to reduce NBTI degrada-tion and leakage power consumption. Section IV introducesthe NBTI and leakage cosimulation framework. Section Vpresents the experimental results. Conclusions are given inSection VI.

II. Preliminaries

This section introduces the NBTI model and the gate delayestimation methods. Related works about IVC, INC, and GRare presented as well.

A. NBTI Modeling and Gate Delay Estimation

The physical mechanism of NBTI is well explained throughthe reaction-diffusion (R-D) model with stress and recoveryphases. Solving the R-D model for NBTI, we can obtain thecycle-by-cycle �Vth predictive model, as shown in Table I. De-fault values for these parameters can be found in [1] and on thePTM website. A and Kv are functions of the vertical electricalfield, and the carrier concentrations (C = exp(−Ea/kT )/T0).δ, ξ1, and ξ2 are constants.

However, cycle-by-cycle models are not efficient enough forlong stress time simulation. A long-term model shown in thefollowing is proposed to speed up the calculation:

�Vth ≤(

K2vαTclk

1 − β1

2nm

)2n

where Kv is a function of temperature, electric field andcarrier concentration, α is the stress signal probability, βm

is the fraction parameter of the recovery, and n is the timeexponential constant. A detailed explanation of each parametercan be found in [16].

Using V th computed by the long-term model, a first-orderapproximation for the propagation delay of the gate (T d) canbe computed by

Td = a0 + a1�Vth + a2Cl. (1)

Fig. 3. CMOS gates modified to include node control.

The number a0 is the intrinsic delay of the gate withoutNBTI, Cl is the gate output load capacity, and a1 and a2 arealso constants.

By fitting the HSPICE simulation results, we can get thecoefficient values for a0, a1, and a2. These NBTI predictivemodels have been widely used to analyze the influence ofNBTI on the circuit at the gate and the architectural level [6],[10], [19].

Using the previous model, we can use a 32-nm PTM [4]model in HSPICE to measure the propagation delay of alltypes of gates used in the testcases. These gates include INV,NAND2, NOR2, AND2, OR2, AOI21, and DFF gates.

B. INC

IVC is a well-known technique to reduce leakage powerconsumption. Since the NBTI effect also depends on the inputstate of a gate, it has also been proposed to mitigate NBTI-induced device degradation in [13]. Unfortunately, the bestinput vectors for leakage reduction normally do not matchwith the best input vector for NBTI degradation because input0 is better to reduce leakage, and input 1 is better to reduce theNBTI effect. To make it worse, the input vector for the smallestleakage power consumption may lead to maximum NBTI-induced circuit degradation. In addition, with the increasingnumber of circuits and a deeper logic path, the IVC techniqueis less effective in reducing the NBTI-induced degradation andleakage power consumption because gates with deep levelsare less likely to be affected by the input vector. In order toovercome the weakness of the IVC technique under a standbymode, the INC has been proposed. INC refers to setting thestates of dividable nodes or gate outputs at any layer of thecircuit to specific values. With this extension to IVC, furthercontrol and thus NBTI mitigation and leakage power reductionare possible. INC can be implemented by additional controlcircuitry at the output of each controlled gate.

The INC implementation is shown in Fig. 3. When the sleepsignal is 1, a gate can allow its output to be forced to eitherhigh or low. To force the output to high, the output of the gateis connected to V DD via a PMOS transistor in parallel withthe existing pull-up network. In order to prevent a short circuitfrom supply voltage to ground through the gate, it is necessaryto place an NMOS transistor in a series with the existing pull-down network. On the contrary, in order to force the outputto low, the output of the gate is connected to the ground viaan NMOS transistor in parallel with the existing pull-down


Fig. 4. GR example for leakage reduction.

Fig. 5. GR example for NBTI mitigation.

network. To prevent a short circuit, the pull-up network isthen placed in series with a PMOS transistor.

For an inverting logic implementation technology such asCMOS, if all the inputs to a gate are high, then the output willbe low. Thus, it seems that in order to control input states tomitigate the NBTI effect and reduce leakage power, INC mustbe implemented at the output of every gate. Unfortunately,adding this extra circuitry that is required for INC increasescircuit delay, and it is not practical to cover every gate withINC. Therefore, we should be careful in adding the internalnode to the critical paths.

C. GR

The GR technique is intended to replace a gate by anothergate that is combined with the sleep signal. The GR techniquehas been proposed to reduce leakage power consumption bytaking advantage of the stacking effect when circuits enterthe standby mode. Fig. 4 shows how to replace an NAND2

gate to reduce its leakage power. The input vector lead to theleast leakage power is referred to as the best leakage state.Otherwise, the input vector lead to the largest leakage poweris called the worst leakage state (WLS). The NAND2 gate G isoriginally in the WLS. After being replaced by an NAND3 gatewith a sleep signal, up to 45.2% of the leakage power can besaved.

Since NBTI degradation is closely related to the time wheninput values of PMOS transistors are 0, where PMOS tran-sistors are under stress, one way to reduce NBTI degradationis to change circuits so that the input values are set to 1.The GR technique can be used to change the gate structureto mitigate the NBTI-induced circuit degradation. Fig. 5 is anexample that shows how to mitigate the NBTI effect by theGR technique. When the circuit is in a standby time, the inputstate of the NAND2 gate G2 will lead to the NBTI effect. Inorder to mitigate the NBTI effect, it is necessary to replacethe NAND2 gate G1 by an NAND3 gate with a sleep signal sothat the output is changed to 1. Hence, the NBTI effect on G2is mitigated during the standby time.

Wang et al. proposed the use of the GR technique to reduceaging by creating values 1 on fan-out gate inputs [14], [15].They proposed two GR algorithms to simultaneously reducethe leakage power and mitigate NBTI-induced degradation.

D. Node Criticality Computation

As was mentioned previously, in order to reduce areaoverhead when reducing the NBTI effect and leakage power

consumption, it is necessary to determine the most importantcritical gates that require protection. Node criticality computa-tion has been proposed in [18]. Wang et al. [17] developed amethodology for identifying the critical nodes, which sufferlarge NBTI-induced delay degradation and have significantimpacts on the circuit timing. The higher the criticality ofthe node is, the more necessary it is to reduce its degradation.The critical gate calculation (CGC) for node ni on the mostcritical path (MCP) is given by

Cni=

�Dni× rni

max(�Dni× rni

)+ 1. (2)

For the node ni that is not on the MCP, the calculation ofits criticality is as follows:

Cni=

�Dni× rni

max(�Dni× rni

)− δ (3)

where �Dniis the delay degradation for node ni, and rni

isdefined to be the number of potential critical paths (PCPs) onwhich node ni has impact. The multiplication, �Dni

× rni, is

normalized by max(�Dni

× rni

), where max

(�Dni

× rni

)is

the maximum value of �Dni× rni

for all the nodes that areon the MCP. δ is a small positive number to ensure that Cni

is smaller than 1. More details can be found in [18].It is important to know how many nodes in the circuit can

be protected, and this really depends on the circuit area andtiming budget. With the node criticality, we will be able toidentify and protect the node that has the most NBTI-induceddelay degradation under the minimum area overhead. Thismethod provides detailed guidance by which circuit designerscan conduct effective circuit optimization to protect circuitsfrom NBTI degradation. Therefore, in order to reduce thenumber of protected gates to avoid excess protection, weintegrate this technique into our framework.

III. TG-Based Technique for NBTI/Leakage

Mitigation

This section details the proposed transmission gate-basedtechnique for NBTI mitigation and leakage reduction. Insteadof modifying the gate directly in the GR technique, we proposethe addition of a transmission gate and a pull-up transistor infront of the protected gates to reduce the NBTI effect. Fig. 6illustrates the technique. As shown in Fig. 6(a), a transmissiongate and a pull-up PMOS are added in front of gate G2.When the circuit is in the active mode, the sleep signal is0; the transmission gate is turned on, and the pull-up PMOStransistor is off; the circuit is functioning as normal. Duringthe standby mode, the transmission gate is turned off, and thePMOS transistor is turned on. The input signal of the fan-outgate, i.e., G2, is 1. Gate G2 stays in recovery mode, mitigatingthe degradation generated during the stress mode.

The transmission gate-based technique does not change thegate function in the active mode. We add a transmission gateto create another state on the wire in the standby mode. Forexample, in Fig. 6(a), the wire that connects G1 with G2 hasboth a 0 and 1 states so that the NBTI effect on G2 is reducedbecause its input is now 1 not 0.


Fig. 6. Example of using the TG-based technique for aging and leakagereduction. (a) TG-gate for NBTI mitigation. (b) TG-gate for leakage reduction.

TABLE II

Increased Delay Comparison Between GR and TG Techniques

Dinc (GR) Dinc (TG) Dinc (GR) Dinc (TG)w/o NBTI w/o NBTI w/ NBTI w/ NBTI

INV 14.17% 19.82% 29.39% 25.51%NAND2 14.76% 14.90% 22.74% 19.19%AND2 26.00% 13.06% 36.60% 16.81%NOR2 −3.25% 13.61% 29.59% 17.53%OR2 24.28% 12.54% 42.08% 16.14%Average 15.19% 14.76% 32.08% 19.04%Standard Deviation 11.63% 2.95% 7.43% 3.79%

As shown in Fig. 6(b), our proposed technique adds a trans-mission gate and a pull-down transistor for leakage reduction.In the active mode, the sleep signal is 0. The transmissiongate is on and the pull-down transistor is off. The circuit isfunctioning as normal. In the standby mode, the sleep signalis 1 and the transmission gate is off; the pull-down transistoris on, and the G4 input signal is 0 for leakage reduction.

A major benefit is that the extra delay caused by the pro-posed method does not depend on the gate type. Table II showsthe increased delay comparison for each gate type between theGR and the TG-based techniques. Columns 2 and 3 are theincreased delay for the GR technique and transmission-basedtechnique without the NBTI effect. Although the average delayincrements are similar (15.19% versus 14.76%), the standarddeviation of the GR technique is 3.94× larger than that ofthe TG-based technique. The reason for this is that the GRtechnique modifies the gate structures. Therefore, the delaydepends on the gate type. Note that the delay of the NOR2 gateis actually decreased since for the GR technique, the additionalpull-up PMOS in the NOR gate increases the pull-up strength.

Columns 4 and 5 are the increased delay for both the GRand TG-based techniques when the NBTI effect is considered.The delay increase for the GR technique is larger than that for

Fig. 7. NBTI and leakage optimization using the transmission gate-basedtechnique is more flexible than the GR technique. (a) Initial state of the givencircuit. We can see that for the G2 gate on the critical path, input equal to1 is better than 0. The G3 gate’s input equal to 0 is better than 1. (b) GRtechnique for NBTI mitigation without leakage reduction. (c) TG-gate forNBTI and leakage optimization.

the TG-based technique since there are more PMOS transistorsand gate topology in the GR technique.

Fig. 7 shows another advantage of the transmission gate-based technique. For the GR technique, there is only oneoutput value for the replaced gate. If the fan-out gate needs adifferent input value for leakage reduction, it will not be ableto provide the required value. For example, in Fig. 7(a), NAND2

gates G2 and G3 are the fan-out gates for NAND2 gate G1. G1and G2 are on the critical path, but G3 is not. Hence, G2and G3 have different optimization needs: NBTI optimizationfor G2 and leakage optimization for G3. To optimize NBTIdegradation on gate G2, 1 is required, and the output of G1also needs to be 1. However, the minimum leakage state ofG3 requires 0 as the input, which is contradictory to the G1output. Therefore, in Fig. 7(b), G3 has to choose states thathave more leakage power consumption, and the circuit cannotachieve maximum leakage reduction.

Our proposed TG-based technique can effectively solve thisproblem. In Fig. 7(c), when the transmission gate is insertedinto the output wire of gate G1, the wire values before and afterthe transmission gate can be different. The two different values


TABLE III

Leakage Comparison Between the TG and GR Techniques for

NAND2 and NOR2

Input of G2 TG+NAND2 Input of G2’ GRNAND2 LeakImp

00 1.98 010 1.95 1.76%01 2.94 011 2.74 7.26%

Fig. 8. Figure leakage power reduction using the TG-based and GR tech-niques. (a) Circuit if a TG is inserted. (b) GR for leakage power.

will suit different needs of both gates G2 and G3; gate G2 canchoose value 1 to optimize NBTI degradation, and gate G3 canalso choose value 0 for better leakage reduction. Therefore,our proposed technique has higher flexibility to connect thefan-out gates before or after the transmission gate to achieveeffective input selection. Note that although gate G3 is affectedby NBTI, the positive slack on the path is sufficient. Therefore,it will not become the most critical path.

It is worth mentioning that the GR technique may achievebetter leakage reduction than the TG-based techniques forthe gates that are on the noncritical path. Fig. 8(a) showsa circuit with the TG-based technique for leakage reduction,and Fig. 8(b) shows the same circuit if the GR technique isused. Gate G2 is replaced by gate G2’. The sleep signal is0 during the standby mode. The leakage for the two circuitsunder different input vectors is shown in Table III. It can beseen that the GR technique has less leakage than the TG-basedtechnique because the G2’ has three inputs and the stackingeffect. Therefore, when the GR technique can achieve lowerleakage for noncritical gates, it is better to apply it for the gateon the noncritical paths.

A. Transmission Gate Insertion Algorithm

In order to mitigate the NBTI-induced circuit performancedegradation, we propose a novel NBTI mitigation algorithm,as shown in Algorithm 1.

The inputs of the algorithm are the critical gate information,which is provided by CGC, as mentioned in Section II. Thetopological order of the overall circuit and the connected wiresbetween the gates can be obtained from the input circuit, andthe primary input vector for the sleep mode can be obtainedby the input vector generator.

The first line of the algorithm is designed to calculate theinternal node state by using a logic simulator (line 1). Afterdetermining all the internal states in the given circuit, we candecide whether the transmission gate should be inserted infront of protected gates. We select critical gate Gi from theset of the critical gates that are calculated by CGC and checkthe Gi’s input value (lines 2 and 3). If the input value is 1,then there is no need to insert the transmission gate and pull-up transistor to mitigate the NBTI effect because this is in thebest NBTI mitigation state (lines 4 and 5). If not, we needto insert a transmission gate and pull-up transistor to change

Algorithm 1 NBTI mitigation algorithm

the input state from 0 to 1 by connecting the output of theinserted transmission gate (lines 6 and 7).

In addition, we record the position of wires where thetransmission gate will be inserted (line 8). Recording thelocation of the transmission gate is quite efficient because thetransmission gate is not inserted every time. In addition, ifa transmission gate is inserted on the wire, the signal valuebefore and after the transmission gate will be different so thatif another gate is connected to this wire, it can choose the bestinput state for NBTI mitigation or leakage reduction.

In line 10, if a transmission gate is inserted in any Gi inputwire, it is necessary to update the output value of Gi. We alsohave to update the signal value of its fanout cone. The leakageand delay need to be updated due to the changes in the Gi

input vector (lines 11–13). The output of this algorithm is theposition of the transmission gates and the number of insertions.

Complexity: The complexity of this algorithm is O(p∗n∗m),where p is the number of input pins of one gate, n is thenumber of critical gates obtained from CGC, and m is thenumber of gates in the fanout cone. A gate normally has oneto three input pins. Therefore, the number of input pins p canbe regarded as a constant, and the complexity of this algorithmcan be simplified to O(n ∗ m).

We integrate the previous NBTI mitigation algorithm intothe following transmission gate insertion algorithm for NBTIand leakage optimization, as shown in Algorithm 2. The criti-cal gates are processed by the NBTI mitigation algorithm, andthe noncritical gates are processed by the leakage reductionalgorithm. Because the NBTI mitigation is discussed in theprevious paragraph, the following will focus on the leakagereduction algorithm.

The inputs of the algorithm are the same as the NBTImitigation algorithm. The first line of the transmission gateinsertion algorithm in Algorithm 2 is to execute the NBTImitigation algorithm, as shown in Algorithm 1 (line 1). Thismeans that the NBTI mitigation algorithm needs to be done


Algorithm 2 NBTI and leakage optimization algorithm

before the leakage reduction algorithm. After we protect thecritical gates, for each gate in the circuit that is not among thecritical gates, we check its gate type to obtain the input valuesthat have the least leakage (lines 2–4). For each Gi input, wecheck if the input can render the gate with the least leakagepower consumption (lines 5 and 6).

If this is true, we do not need to change the circuit. If not,we use the TG-based technique to change the input state (lines7–9). For example, the best input vector of the NOR2 gate forsaving leakage power consumption is 11. If it is already in thebest state, there is no need to insert a transmission gate anda pull-up transistor in front of the NOR2 gate. Otherwise, weneed to change the input state from 0 to 1 by inserting thetransmission gate and pull-up transistor.

Finally, we update the signal state from Gi’s output to pri-mary outputs and recalculate the leakage and delay change dueto the inserted transmission gate. If there are no transmissiongates inserted in front of Gi, we do not need to update theoutput value and circuit functionality (lines 11–13).

Complexity: The complexity of this algorithm is O(p∗n∗m),where p and m are the same as the NBTI mitigation algorithm,but n is the number of total gates. The complexity of thisalgorithm also can be simplified to O(n∗m) since the numberof input pins p can be treated as a constant.

Since the GR technique outperforms the TG-based tech-nique for leakage reduction, we also can use the GR techniquefor leakage reduction and combine it with our proposedtechnique for NBTI mitigation. As shown in Algorithm 3, weuse the TG-based technique to mitigate the NBTI effect andthe GR technique to reduce the leakage power consumption.

Algorithm 3 Combined algorithm for TG-based and gate replacementtechnique

Lines 1–6 are the same as Algorithm 2, and lines 7–12 usethe GR technique for leakage reduction. First, we check thegate input state and replace the gate if its input values donot lead to the least leakage (lines 7–9). Then, we update thesignal and calculate new leakage and delay when the gate isreplaced (lines 10–12).

From the above discussion, it can be seen that due to theflexibility of the transmission gate-based technique, the com-plexity of our algorithms is simple and effective (complexityis O(n∗m)). At the same time, it is straightforward to integrateother algorithms into our algorithm.

IV. NBTI and Leakage Cosimulation Framework

This section introduces the NBTI and leakage cosimulationframework. As mentioned in the introduction, it is critical toestimate both dynamic NBTI and static NBTI to correctlypredict the NBTI effect. It explains how to estimate staticNBTI, dynamic NBTI, and leakage. We improve the NBTIsimulation flow in [17] by using the in-house NBTI-awarestatic timing analysis and then integrate the node criticalitycalculation and leakage estimation into the framework. Whenthe circuit is in the sleep mode, static NBTI and leakage powerconsumption are estimated, and while it is in active mode,dynamic NBTI is estimated.

Fig. 9 shows our simulation flow for both active mode andsleep mode analysis. The left part is the flow for active modeanalysis, and the right part is for sleep mode analysis. Twodefinitions for better explanation are given as follows.

Definition (Potential Critical Path): A path is called apotential critical path (PCP) if it can potentially become thecritical path after some time with delay degradation caused


Fig. 9. NBTI and leakage simulation framework and circuit optimization.

by the NBTI effect. Supposing that there are M paths in acircuit, the timing information for each path will be availableonce NBTI-aware STA is finished. In this paper, we pick upthe top 15% paths as potential critical paths. In the case ofcircuit designers, the analysis targets can be selected accordingto their requirements.

Definition (Most Critical Paths): A path is called a mostcritical path (MCP) if the path has the longest delay amongPCPs in a circuit.

A. Simulation Flow for Sleep Mode

The right part of Fig. 9 shows the simulation flow for thesleep mode. The inputs for sleep mode analysis include theinput circuit in a Verilog gate level netlist format, cell library,and an input vector generator. A logic simulator and lookuptable-based calculation for leakage are also needed. For agiven circuit, we begin with the input vector generator, whichrandomizes to find the least leakage power consumption. Thisprocess will decide the sleep mode input vector for the givencircuit. We use the internal state calculation to obtain theinternal node state. The internal node state is used to esti-mate the static NBTI-induced degradation and leakage powerconsumption in the sleep mode. Leakage power consumptionis estimated based on the lookup table calculation. The NBTI-induced performance degradation is calculated by the thresholdvoltage degradation model. The leakage power informationwill be used by the transmission gate insertion algorithm,and the static NBTI degradation will be used by active modeanalysis to identify critical paths and critical nodes.

B. Simulation Flow for Active Mode

The left part of Fig. 9 is active mode analysis. The inputsare circuits and a cell library both in the gate level netlistVerilog format and the input signal probability for each inputpin. The input signal probabilities are used to calculate the

signal probabilities of each internal wire, which is necessaryfor dynamic NBTI estimation. Based on the signal probabilityinformation, we can estimate dynamic NBTI degradation byusing the threshold voltage degradation model. Therefore, wecan determine the timing degradation of each gate inside thegiven circuit.

The next step, critical path identification, is the most im-portant step in the active mode. The purpose of critical pathidentification is to find MCPs and PCPs. Since the path delaywill increase, and a circuit’s critical path may change due tothe NBTI effect, traditional static timing analysis is not capableof achieving this. Therefore, we implement an in-house NBTI-aware static timing analysis to correctly discover the criticalpaths.

A comparison between the path identification approach in[17] and our proposed path identification is shown in Fig. 10.In [17], their approach first uses traditional static timinganalysis to find path delay without degradation. A thresholdis set to decide MCPs and PCPs. Then, the NBTI degradationinformation for each gate on the path is loaded; the path delayis updated, and new MCPs and PCPs are found. In our flow,we directly load the NBTI degradation information into thecell library and then conduct static timing analysis using theupdated library to find the MCPs and PCPs.

The problem with the approach in [16] is that it is hard todetermine the appropriate threshold. If not chosen correctly,the obtained PCPs may be incorrect. For example, in Fig. 11,the flow in [17] will consider paths a, d, and e as PCPs becausetheir delay is higher than the threshold. However, path cshould be considered as PCP as well because path c has largerincreased degradation caused by NBTI. The path identificationflow in [16] will not be able to identify path c as PCP becausethe threshold is set to high and hence path c is ignored.

In our proposed path identification flow, the cell library isaugmented with NBTI delay degradation. The static timinganalysis considers the NBTI-induced delay. Hence, our pro-posed method can identify the MCPs and PCPs more correctly.

When the MCP and PCP information is obtained, wecan obtain critical gates using the CGC. The critical gateinformation can be used to prioritize the gates that requireprotection. After active mode and sleep mode analysis is done,we can apply our transmission gate insertion algorithm, asshown in the bottom of Fig. 9.

By integrating NBTI-aware STA and CGC, our frameworkcan effectively and accurately estimate static NBTI, dynamicNBTI, and leakage power.

V. Implementation and Experimental Results

A. Implementation

We implement our critical gate calculation and the NBTIor leakage cosimulation framework using C++ on a Linuxplatform. We adopt 32-nm predictive technology modeling [4]and HSPICE to estimate the NBTI degradation for 10 years.Eleven benchmarks are from ISCAS89, and the other fiveare industry-provided benchmarks. These benchmarks containseven kinds of gates (NAND2, AND2, NOR2, OR2, INV, BUF, andAOI21) and DFF. The active time temperature and stand-by


Fig. 10. Comparison between the path identification approach in [17] and our proposed path identification.

Fig. 11. Unable to identify path c as PCP in traditional path identificationflow.

time temperature are both set to 378 K, and the ratio of activeand standby time is set to 1:9. The signal probability of eachinput is set to 0.5, and an in-house tool is used to calculatethe internal node signal probability.

We analyze static and dynamic NBTI degradation based onthe sleep mode internal node state and active mode internalsignal probability and integrate the degradation informationinto our cell library. Then, we use our in-house NBTI-awarestatic timing analysis to discover the MCPs and PCPs for eachbenchmark.

The leakage estimation is based on the table lookup method.We estimate the leakage power of various types of gates indifferent input states and build a table to record the leakagepower when a gate is in different input states. The total leakagepower consumption of the circuit is the summation of eachgate’s leakage power based on its input states.

B. Experimental Results

Table IV shows the delay and leakage optimization resultsfor both the GR technique and the TG-based technique.Columns 2–4 are the percentages of the increased area,

timing improvements, and leakage improvements for the GRtechnique as compared to the original circuit, while columns5–7 are for the TG-based technique. We implement the GRtechnique using the 32-nm high-performance PTM technologyin order to compare with our proposed technique. Since weuse a CGC to determine the protected gates, the number ofinserted gates and replaced gates is minimized.

The runtime of our technique ranges from less than 1 s to 2min. The results show that under similar area overhead (around18%), the TG-based technique improved 32.36% of the delay,but the GR technique only improved 14.96%. The reason isthat the effectiveness of the GR technique depends on the gatetype. A more gate delay is added when more AND2 and OR2

gates are on the critical paths. In addition, the GR techniqueis not able to replace some gates due to output constraints.

For leakage reduction, the GR technique saves, on average,18.03% of the leakage power consumption, while the TG-based technique saves, on average, 13.56%. Although theleakage power consumption for a gate in the GR techniqueis much smaller than that of the TG-based technique becauseof the transistor stacking effect, the leakage reduction in theproposed technique is still comparable since we can use aminimum leakage vector for gates that are not on the criticalpath. Columns 8–10 show the results if we use the GRtechnique for noncritical gates and the TG-based techniquefor critical gates. With a 1.01% (19.19%–18.18%) increase ofarea, we can obtain further 4.36% (17.92%–13.56%) reductionin leakage. Note that the percentage of increased area can beset as a predefined threshold. We can first assign a maximumallowable area increase and then execute the transmissioninsertion algorithms. If the threshold is reached, stop the


TABLE IV

Result Comparison Between GR and Transmission Gate-Based Techniques

algorithm. This can limit the increased area to a user-definedrange.

Our TG-based technique can be used exclusively for eitherNBTI or leakage reduction, as shown in Table V. Columns2–6 show the benchmark circuits’ area, leakage, and delaywithout any circuit modifications. Columns 4 and 5 are delaycomparison before and after the 10-year NBTI degradation.The leakage power consumption is estimated at time 0. Notethat the authors do observe leakage reduction in the agedcircuit due to increased threshold voltage on the degraded gatesdue to the NBTI effect. The amount of leakage reduction isnot within the scope of this paper. This is because our goal forleakage reduction is to reduce leakage power at time 0 as muchas possible to meet the power budget. If the power budget ismet at time 0 after the design is completed, the power budgetshould not be violated in later time since the NBTI effect willincrease the threshold voltage of PMOS transistor and reduceleakage. Hence, we only consider the leakage at time 0, andthe leakage after degradation should not cause power budgetissues. The area estimation of the circuit is based on transistorcounts.

Columns 7–11 are the circuit information when the TGtechnique is used to optimize NBTI only. Columns 12–14are the circuit information when the TG is used to reduceleakage power only. The results show that the path delay ofthe original circuit after 10-year NBTI degradation is largerthan the path delay with the TG technique at time 0 and after10-year degradation. Therefore, our TG-based technique canreduce the NBTI degradation, and no additional design marginis needed when applying the TG technique. In addition, theruntime is smaller than that shown in Table IV because onlyone algorithm is executed, as shown in Table V. If the TG-

based technique is only used to mitigate the NBTI effect, it canachieve the same amount of degradation improvement as inTable IV with only a 2.25% area overhead, which proves thatour proposed TG-based technique only incurs minimum areapenalty. If our technique is used only to reduce leakage, it canachieve 14.85%, increasing from 13.56%, as seen in Table IV.The extra leakage reduction is obtained from the leakagereduction in the critical gates. The area increase is still high(reduced from 17.47% to 16.91%). However, it is a tunableconstraint. If a user allows a lower leakage reduction ratio, theincreased area can be reduced since fewer transmission gatesand pull-down transistors are inserted on noncritical paths.

To illustrate our experimental results, we compare the previ-ous table in Figs. 12 and 13. The TG-based technique has moreimprovement than the GR technique. However, for leakagereduction, our technique has more leakage reduction only ins820, s953, testcase 1, and testcase 5. This is because thestacking effect in the replaced gate can significantly reduce theleakage power consumption. Therefore, we integrate the GRtechnique with our proposed technique. After integration, theleakage improvement is very close (18.03% versus 17.92%).

An important result is that for delay improvement, ourtechnique does not depend on the gate types on the criticalpaths. However, the GR technique does. If a benchmark hasmore AND2 gates on the critical paths, the delay improvementwill be less if the GR technique is used. A typical exampleis testcase 3. The experimental results show that delay im-provement of the GR technique is 6.53%, while that of theTG-based technique significantly improves by 22.37%. Thereason for this is that for the GR technique, a transistor isadded to the serial-connected pull-down NMOS transistor inthe AND2 gate. Thus, the increased delay is more significant.


TABLE V

Result Comparison Between NBTI-Only and Leakage-Only Optimization

Fig. 12. Delay improvement comparison between GR and TG-based tech-nique (higher is better).

Fig. 13. Leakage improvement comparison between GR and TG-based tech-nique (higher is better).

From the experimental results, we observe that the fivetest cases, s641, s713, s820, s838 and s953, have similarareas; both techniques have different leakage reduction. Inthe s641, s713, and s838 test cases, the GR technique hasbetter leakage reduction (21.34% versus 8.59%). However,the leakage improvement in s820 and s953 is better when

Fig. 14. Area and leakage comparison of gate-replacement and TG-basedtechniques for testcase s820.

our technique is used (14.45% versus 23.18%). The reasonfor this can be explained using Fig. 14. Fig. 14 shows theleakage reduction comparison when there is no limitation onthe area penalty. The x-axis is the area penalty, and the y-axis is the percentage of leakage improvement. When the areapenalty is from 0 to 50, this is only a little improvementbecause the TG-based technique focuses on mitigating theNBTI effect. On the contrary, when a gate is replaced bythe GR technique, the leakage power will be reduced dueto the stack effect. When the area penalty is more than 50,the leakage reduction significantly improves and outperformsthe GR technique when the area penalty is more than 90.Finally, both methods have similar leakage reduction. From theresults, we can see that our technique results in better leakagereduction in some cases because our technique is more flexible.

Another observation is that it is not necessary to protect allthe critical gates. Fig. 15 shows the relationship between the


Fig. 15. Number of protected gates versus leakage power versus delay.

numbers of the protected critical gates, the critical path delay,and the leakage power consumption for testcase 3, which hasthe largest number of gates in all the test cases. The x-axisis the number of critical gates that are protected to preventNBTI-induced circuit performance degradation. The solid linerepresents the delay and the dotted line shows the leakagepower consumption.

The results show that the leakage increases slightly since thecritical gates are protected for NBTI. When the protected gatenumber grows, the delay decreases significantly in the begin-ning. However, the improvement saturates after the number ofprotected gates reaches 220. Hence, it is worthless to protectmore than 220 critical gates. We observe similar trends forother test cases.

Although the optimization number for protected gates isin a range between 170 and 220, the delay does not remainconstant in this region. The reason is that, normally, we protectthe most critical gates in the MCP. However, we observe thatthere are many cases in which the PCP will degrade fasterthan that of the MCP, and finally, the delay for the PCP willbe greater than the MCP and will become the new critical path.It is necessary to protect these PCPs as well. Therefore, usingthe CGC to find and protect the critical gates by the ranksof their criticality can improve the effectiveness of TG-basedtechniques.

VI. Conclusion and Future Work

Power and reliability are two major design constraints in45-nm technology and below. In this paper, we proposed anovel technique that can reduce leakage power and NBTI-induced degradation. This technique inserted a transmissiongate in front of protected gates. Compared to related works,the technique significantly reduced NBTI-induced degradationwith comparable leakage power reduction. The results showedthat our proposed technique had up to 20× and 2.44×, on aver-age, improvement on NBTI-induced degradation, as comparedto the GR technique with comparable leakage power reduction.With a 19.19% area penalty, combining our technique and

the GR can reduce 17.92% of the total leakage power and32.36% of the NBTI-induced circuit degradation. Note thatif less leakage reduction is allowed, the area penalty can bereduced if less transmission gates are inserted in noncriticalpaths.

Note that there was a corresponding and dual effect of theNBTI effect, known as positive bias temperature instability(PBTI) for the nMOS transistor. Currently, we only considerthe NBTI effect in this paper because NBTI is more seriousthan PBTI in the process used in this paper. However, PBTIis comparable to NBTI in the more advanced high-k metalprocess technology. The TG technique proposed in this papercan be used with either a pull-up or a pull-down transistor.Pull-up transistors can change the output to 1, mitigating theNBTI effect on the fanout gate, and the pull-down transistorscan change the output to 0, mitigating the PBTI effect on thefanout gate. Future works will include integrating PBTI mod-els into our simulation framework, predicting the degradationcaused by each effect based on the input signal probabilities,improving our algorithms to consider both the NBTI and PBTIeffects at the same time, and deciding whether a TG witha pull-up transistor should be inserted to mitigate the NBTIeffect or whether a TG with a pull-down transistor should beinserted to mitigate the PBTI effect.

Acknowledgment

The authors would like to thank Dr. Y. Cao and J. Velamala,Arizona State University, Phoenix, for their NBTI modeling,and Dr. B. Vaidyanathanand and Dr. R. Krishnan for theirvaluable suggestions.

References

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Ing-Chao Lin (M’09) received the M.S. degree incomputer science from National Taiwan University,Taipei, Taiwan, and the Ph.D. degree from theDepartment of Computer Science and Engineering,Pennsylvania State University, University Park, in2007.

Since 2009, he has been with the Departmentof Computer Science and Information Engineering,National Cheng Kung University, Tainan, Taiwan,where he is currently an Assistant Professor. From2007 to 2009, he was with Real Intent, Inc., Sun-

nyvale, CA, where he worked on the automatic timing exception verifier.His current research interests include very large-scale integration design andcomputer-aided design for nanoscale silicon, computer architecture, and low-power reliable system design.

Chin-Hong Lin (S’11) received the B.S. degreefrom Chang Gung University, Taoyuan, Taiwan, andthe M.S. degree from National Cheng Kung Univer-sity, Tainan, Taiwan, in computer science and infor-mation engineering in 2009 and 2011, respectively.

He is currently completing his compulsory militaryservice. His current research interests include circuitreliability issues and low power design.

Kuan-Hui Li received the B.S. degree in electronicengineering from Chung Yuan Christian University,Chung Li, Taiwan, in 2010. He is currently pursuingthe M.S. degree in computer science and informationengineering from National Cheng Kung University,Tainan, Taiwan.

His current research interests include circuit relia-bility issues and low power design.

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