#04-2020-1000-108 Lecture2 Combinational Logical Circuits V...2020/02/04 · CSCI 150 04.02.20...
Transcript of #04-2020-1000-108 Lecture2 Combinational Logical Circuits V...2020/02/04 · CSCI 150 04.02.20...
04.02.20 14:27
CSCI 150 Introduction to Digital and Computer
System Design Lecture 2: Combinational Logical Circuits V
Jetic Gū2020 Winter Semester (S1)
2 Types of Knowledge
Nothing
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2 Types of Knowledge
1. I know this by heart!
• Important Definitions, Number Systems and Arithmetics, Boolean Algebra
2. Whatever, I can look it up when I need it.
• The rest of lecture 2 today.
• You need to know where to look at if you don’t remember later!
Nothing
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Overview• Focus: Boolean Algebra
• Architecture: Combinatory Logical Circuits
• Textbook v4: Ch2 2.8, 2.9. 2.10; v5: Ch2 2.6, 2.7
• Core Ideas:
1. Other Gate Types: XOR, NAND, NOR, Buffer, High-Impedance, Odd Function
2. Lecture 2 Review
Boolean Algebra I-IIII. AND, OR, NOT Operators and Gates
• Simple digital circuit implementation
• Algebraic manipulation using Binary Identities
II. Standard Forms
• Minterm & Maxterm
• Sum of Products & Product of Sums
III. Optimisation Using K-Map (For 2,3,4 Variables)
Review
P0 Review
Other Gate Types
Summary
P1 Other Gates
Delay PropagationXOR, NAND, NOR, Buffer
Gate Delay
Review
P1 Other Gates
Timing Diagram (REALITY)
Z = X ⋅ YXY
1
X1
Y1
0 1 2 3 4 5
Z
0 1 0 1 0
0 0 1 1 0
Gate Delay
Review
P1 Other Gates
Timing Diagram (REALITY)
Z = X ⋅ YXY
1
X1
Y1
0 1 2 3 4 5
Z
0 1 0 1 0
0 0 1 1 0
1
Gate Delay
Review
P1 Other Gates
Timing Diagram (REALITY)
Z = X ⋅ YXY
1
X1
Y1
0 1 2 3 4 5
Z
0 1 0 1 0
0 0 1 1 0
1 Gate delay �tG
Delays
• Gate Delay
• The time required for a change in value of a signal to propagate from input to output (of a Gate)
• Propagation Delay
• The time required for a change in value of a signal to propagate from input to output (of a Circuit)
Concep
t
P1 Other Gates
Delays
• � : Propagation Delay: longest time for propagating from input to output
• � : Hight2Low propagation time; � : Low2High propagation time;
tpd
tPHL tPLH
Concep
t
P1 Other Gates 2-7 / Gate Propagation Delay 81
for the edge in question, and whether the edge will result in a change in the ID out-put. Since edge b occurs before the end of the rejection time for edge a in the ND output, edge a does not appear in the ID output. Since edge b does not change the state of ID, it is ignored. Since edge d occurs at the rejection time after edge c in the ND output, edge c does appear. Edge e, however, occurs within the rejection time after edge d, so edge d does not appear. Since edge c appeared and edge d did not appear, edge e does not cause a change.
Next, we want to consider further the components that make up the gate delay within a circuit environment. The gate itself has some fixed inherent delay. Because it represents capacitance driven, however, the actual fan- out of the gate, in terms of standard loads, discussed in Chapter 5, also affects the propagation delay of the gate. But depending upon the loading of the gate by the inputs of the logic attached to its output, the overall delay of the gate may be significantly larger than the inherent gate delay. Thus, a simple expression for propagation delay can be given by a formula
IN
OUT tPHL
tPHLtpd
tPLH
tPLH
IN OUT
! max ,( )
FIGURE 2-24Propagation Delay for an Inverter
A
A · B:
TransportDelay (TD)
InertialDelay (ID)
B
Time (ns)0 42 6 8 10 12 14 16
No Delay(ND)
a b c d e
FIGURE 2-25Examples of Behavior of Transport and Inertial Delays
M02_MANO0637_05_SE_C02.indd 81 23/01/15 1:48 PM
Transport and Inertial Delays
Concep
t
P1 Other Gates
2-7 / Gate Propagation Delay 81
for the edge in question, and whether the edge will result in a change in the ID out-put. Since edge b occurs before the end of the rejection time for edge a in the ND output, edge a does not appear in the ID output. Since edge b does not change the state of ID, it is ignored. Since edge d occurs at the rejection time after edge c in the ND output, edge c does appear. Edge e, however, occurs within the rejection time after edge d, so edge d does not appear. Since edge c appeared and edge d did not appear, edge e does not cause a change.
Next, we want to consider further the components that make up the gate delay within a circuit environment. The gate itself has some fixed inherent delay. Because it represents capacitance driven, however, the actual fan- out of the gate, in terms of standard loads, discussed in Chapter 5, also affects the propagation delay of the gate. But depending upon the loading of the gate by the inputs of the logic attached to its output, the overall delay of the gate may be significantly larger than the inherent gate delay. Thus, a simple expression for propagation delay can be given by a formula
IN
OUT tPHL
tPHLtpd
tPLH
tPLH
IN OUT
! max ,( )
FIGURE 2-24Propagation Delay for an Inverter
A
A · B:
TransportDelay (TD)
InertialDelay (ID)
B
Time (ns)0 42 6 8 10 12 14 16
No Delay(ND)
a b c d e
FIGURE 2-25Examples of Behavior of Transport and Inertial Delays
M02_MANO0637_05_SE_C02.indd 81 23/01/15 1:48 PM
Transport and Inertial Delays
Concep
t
P1 Other Gates
2-7 / Gate Propagation Delay 81
for the edge in question, and whether the edge will result in a change in the ID out-put. Since edge b occurs before the end of the rejection time for edge a in the ND output, edge a does not appear in the ID output. Since edge b does not change the state of ID, it is ignored. Since edge d occurs at the rejection time after edge c in the ND output, edge c does appear. Edge e, however, occurs within the rejection time after edge d, so edge d does not appear. Since edge c appeared and edge d did not appear, edge e does not cause a change.
Next, we want to consider further the components that make up the gate delay within a circuit environment. The gate itself has some fixed inherent delay. Because it represents capacitance driven, however, the actual fan- out of the gate, in terms of standard loads, discussed in Chapter 5, also affects the propagation delay of the gate. But depending upon the loading of the gate by the inputs of the logic attached to its output, the overall delay of the gate may be significantly larger than the inherent gate delay. Thus, a simple expression for propagation delay can be given by a formula
IN
OUT tPHL
tPHLtpd
tPLH
tPLH
IN OUT
! max ,( )
FIGURE 2-24Propagation Delay for an Inverter
A
A · B:
TransportDelay (TD)
InertialDelay (ID)
B
Time (ns)0 42 6 8 10 12 14 16
No Delay(ND)
a b c d e
FIGURE 2-25Examples of Behavior of Transport and Inertial Delays
M02_MANO0637_05_SE_C02.indd 81 23/01/15 1:48 PM
Transport and Inertial Delays
Concep
t
P1 Other Gates
2-7 / Gate Propagation Delay 81
for the edge in question, and whether the edge will result in a change in the ID out-put. Since edge b occurs before the end of the rejection time for edge a in the ND output, edge a does not appear in the ID output. Since edge b does not change the state of ID, it is ignored. Since edge d occurs at the rejection time after edge c in the ND output, edge c does appear. Edge e, however, occurs within the rejection time after edge d, so edge d does not appear. Since edge c appeared and edge d did not appear, edge e does not cause a change.
Next, we want to consider further the components that make up the gate delay within a circuit environment. The gate itself has some fixed inherent delay. Because it represents capacitance driven, however, the actual fan- out of the gate, in terms of standard loads, discussed in Chapter 5, also affects the propagation delay of the gate. But depending upon the loading of the gate by the inputs of the logic attached to its output, the overall delay of the gate may be significantly larger than the inherent gate delay. Thus, a simple expression for propagation delay can be given by a formula
IN
OUT tPHL
tPHLtpd
tPLH
tPLH
IN OUT
! max ,( )
FIGURE 2-24Propagation Delay for an Inverter
A
A · B:
TransportDelay (TD)
InertialDelay (ID)
B
Time (ns)0 42 6 8 10 12 14 16
No Delay(ND)
a b c d e
FIGURE 2-25Examples of Behavior of Transport and Inertial Delays
M02_MANO0637_05_SE_C02.indd 81 23/01/15 1:48 PM
Transport and Inertial Delays
• Transport Delay: output in response to input changes after propagation delay
Concep
t
P1 Other Gates
2-7 / Gate Propagation Delay 81
for the edge in question, and whether the edge will result in a change in the ID out-put. Since edge b occurs before the end of the rejection time for edge a in the ND output, edge a does not appear in the ID output. Since edge b does not change the state of ID, it is ignored. Since edge d occurs at the rejection time after edge c in the ND output, edge c does appear. Edge e, however, occurs within the rejection time after edge d, so edge d does not appear. Since edge c appeared and edge d did not appear, edge e does not cause a change.
Next, we want to consider further the components that make up the gate delay within a circuit environment. The gate itself has some fixed inherent delay. Because it represents capacitance driven, however, the actual fan- out of the gate, in terms of standard loads, discussed in Chapter 5, also affects the propagation delay of the gate. But depending upon the loading of the gate by the inputs of the logic attached to its output, the overall delay of the gate may be significantly larger than the inherent gate delay. Thus, a simple expression for propagation delay can be given by a formula
IN
OUT tPHL
tPHLtpd
tPLH
tPLH
IN OUT
! max ,( )
FIGURE 2-24Propagation Delay for an Inverter
A
A · B:
TransportDelay (TD)
InertialDelay (ID)
B
Time (ns)0 42 6 8 10 12 14 16
No Delay(ND)
a b c d e
FIGURE 2-25Examples of Behavior of Transport and Inertial Delays
M02_MANO0637_05_SE_C02.indd 81 23/01/15 1:48 PM
Transport and Inertial Delays
• Transport Delay: output in response to input changes after propagation delay
• Inertial Delay: if a value changes twice in a short time (rejection time), ignore
Concep
t
P1 Other Gates
2-7 / Gate Propagation Delay 81
for the edge in question, and whether the edge will result in a change in the ID out-put. Since edge b occurs before the end of the rejection time for edge a in the ND output, edge a does not appear in the ID output. Since edge b does not change the state of ID, it is ignored. Since edge d occurs at the rejection time after edge c in the ND output, edge c does appear. Edge e, however, occurs within the rejection time after edge d, so edge d does not appear. Since edge c appeared and edge d did not appear, edge e does not cause a change.
Next, we want to consider further the components that make up the gate delay within a circuit environment. The gate itself has some fixed inherent delay. Because it represents capacitance driven, however, the actual fan- out of the gate, in terms of standard loads, discussed in Chapter 5, also affects the propagation delay of the gate. But depending upon the loading of the gate by the inputs of the logic attached to its output, the overall delay of the gate may be significantly larger than the inherent gate delay. Thus, a simple expression for propagation delay can be given by a formula
IN
OUT tPHL
tPHLtpd
tPLH
tPLH
IN OUT
! max ,( )
FIGURE 2-24Propagation Delay for an Inverter
A
A · B:
TransportDelay (TD)
InertialDelay (ID)
B
Time (ns)0 42 6 8 10 12 14 16
No Delay(ND)
a b c d e
FIGURE 2-25Examples of Behavior of Transport and Inertial Delays
M02_MANO0637_05_SE_C02.indd 81 23/01/15 1:48 PM
Parameters of Gate Delay
Concep
t
P1 Other Gates
Parameters of Gate Delay
• Fan-innumber of inputs of a logic gate
Concep
t
P1 Other Gates
Parameters of Gate Delay
• Fan-innumber of inputs of a logic gate
• Fan-out (standard load)number of gates that each logic gate can drive while providing voltage levels in the guaranteed range is called the standard load or fan-out
Concep
t
P1 Other Gates
Standard Load
Demo
P1 Other Gates
1
X1
Y1
0 1 2 3 4 5
X ⋅ Y
0 1 0 1 0
0 0 1 1 0
1 Gate delay �tG
• Digital circuits are driven by power, each component also takes power
Standard Load
Demo
P1 Other Gates
1
X1
Y1
0 1 2 3 4 5
X ⋅ Y
0 1 0 1 0
0 0 1 1 0
High Voltage Area
Low Voltage Area1 Gate delay �tG
• Digital circuits are driven by power, each component also takes power
Standard Load
Demo
P1 Other Gates
1
X1
Y1
0 1 2 3 4 5
X ⋅ Y
0 1 0 1 0
0 0 1 1 0
High Voltage Area
Low Voltage AreaGate delay �tG
• Digital circuits are driven by power, each component also takes power
1
Standard Load
Demo
P1 Other Gates
1
X1
Y1
0 1 2 3 4 5
X ⋅ Y
0 1 0 1 0
0 0 1 1 0
High Voltage Area
Low Voltage AreaGate delay �tG
• Changes in input voltage can also affect output voltage
1
Standard Load
Demo
P1 Other Gates
1
X1
Y1
0 1 2 3 4 5
X ⋅ Y
0 1 0 1 0
0 0 1 1 0
High Voltage Area
Low Voltage AreaGate delay �tG
• If it takes too much power, it will not be able to guarantee output voltage
• Standard load is defining that power consumption, which also affect delay
1
Standard Load
Demo
P1 Other Gates
• OR Gate: 0.8 SL; AND Gate: 1.00 SL;
• Delay for AND: �
• Delay for OR: �
tpd = 0.07 + 0.021 × ∑ InputSL
tpd = 0.05 + 0.02 × ∑ InputSL
XY Z
AND
OR1
OR2
Standard Load
Demo
P1 Other Gates
• OR Gate: 0.8 SL; AND Gate: 1.00 SL;
• Delay for AND: �
• Delay for OR: �
tpd = 0.07 + 0.021 × ∑ InputSL
tpd = 0.05 + 0.02 × ∑ InputSL
XY Z
AND
OR1
OR2
• Estimation for OR2�
• Precise estimation is very hard, since we lack a lot of these information
• We can ignore this computation, but you should know roughly
tpd = 0.05 + 0.02 × (0.8 + 1.00) = 0.086ns
Other Gates
Concep
t
P1 Other Gates
XOR GateExclusive-OR
Buffer
3-State Buffer
Z = X ⊕ YXY
Z = XX
ZX
E
Buffer
Concep
t
P1 Other Gates
XOR GateExclusive-OR
Buffer
3-State Buffer
Z = X ⊕ YXY
Z = XX
ZX
E
• Has delay
• Increases output Voltagee.g.: input 0.8 V, output 1.0 V
3-State Buffer
Concep
t
P1 Other Gates
XOR GateExclusive-OR
Buffer
3-State Buffer
Z = X ⊕ YXY
Z = XX
ZX
E
• Has delay
• Increases output Voltagee.g.: input 0.8 V, output 1.0 V
• When � , outputs no electricity(Open circuit/Hi-Z/High Impedance)
E = 0
3-State Buffer
Concep
t
P1 Other Gates
XOR GateExclusive-OR
Buffer
3-State Buffer
Z = X ⊕ YXY
Z = XX
ZX
E
• Has delay
• Increases output Voltagee.g.: input 0.8 V, output 1.0 V
• When � , outputs no electricity(Open circuit/Hi-Z/High Impedance)
E = 0
3-State Buffer
Concep
t
P1 Other Gates
XOR GateExclusive-OR
Buffer
3-State Buffer
Z = X ⊕ YXY
Z = XX
ZX
E
• Has delay
• Increases output Voltagee.g.: input 0.8 V, output 1.0 V
• When � , outputs no electricity(Open circuit/Hi-Z/High Impedance)
E = 0
3-State Buffer
Concep
t
P1 Other Gates
XOR GateExclusive-OR
Buffer
3-State Buffer
Z = X ⊕ YXY
Z = XX
ZX
E
3-State Buffer Truth Table
0 0 Hi-Z
0 1 Hi-Z
1 0 0
1 1 1
ZXE
XOR Gate
Concep
t
P1 Other Gates
XOR GateExclusive-OR Z = X ⊕ YX
Y
XOR Truth Table
0 0 0
0 1 1
1 0 1
1 1 0
Z = X ⊕ YYX
XOR Gate
Concep
t
P1 Other Gates
XOR GateExclusive-OR Z = X ⊕ YX
Y
XOR Truth Table
0 0 0
0 1 1
1 0 1
1 1 0
Z = X ⊕ YYX
= XY + XY
XOR Gate
Concep
t
P1 Other Gates
• �
• �
• �
X ⊕ 0 = X
X ⊕ X = X
X ⊕ Y = X ⊕ Y
• �
• �
• �
X ⊕ 1 = X
X ⊕ X = 1
X ⊕ Y = X ⊕ Y
Odd and Even Functions
Concep
t
P1 Other Gates
• Odd Functions
• Outputs 1 if the number of 1s in the input is an Odd number
• 2 variables: XOR
• Even Functions
• Outputs 1 if the number of 1s in the input is an Even number
• 2 variables: XNOR
Odd Function K-Map
Concep
t
P1 Other Gates
2-6 / Exclusive-Or Operator and Gates 79
expression. In particular, the 3-variable case can be converted to a Boolean expres-sion as follows:
X ⊕ Y ⊕ Z = (XY + XY)Z + (XY + X Y)Z
= XY Z + XYZ + X YZ + XYZ
The Boolean expression clearly indicates that the 3-variable exclusive- OR is equal to 1 if only one variable is equal to 1 or if all three variables are equal to 1. Hence, whereas in the 2-variable function only one variable need be equal to 1, with three or more variables an odd number of variables must be equal to 1. As a consequence, the multiple- variable exclusive- OR operation is defined as the odd function. In fact, strictly speaking, this is the correct name for the ⊕ operation with three or more variables; the name “ exclusive- OR” is applicable to the case with only two variables.
The definition of the odd function can be clarified by plotting the function on a map. Figure 2-22(a) shows the map for the 3-variable odd function. The four min-terms of the function differ from each other in at least two literals and hence cannot be adjacent on the map. These minterms are said to be distance two from each other. The odd function is identified from the four minterms whose binary values have an odd number of 1s. The 4-variable case is shown in Figure 2-22(b). The eight minterms
00
01
00 01CD
AB
C
D
A
11 10
11
10
B
1
1
1
1
1
1
1
10
1
Y
Z
X 1
00 01 11 10
1
YZ
X
(a) X Y Z
(b) A B C D
1
1
FIGURE 2-22Maps for Multiple- Variable Odd Functions
X
YZ C
P
XY
ZP
(a) P ! X ! Y ! Z (b) C ! X ! Y ! Z ! P
FIGURE 2-23 Multiple- Input Odd Functions
M02_MANO0637_05_SE_C02.indd 79 23/01/15 1:48 PM
Odd Function Boolean Expressions
Concep
t
P1 Other Gates
2-6 / Exclusive-Or Operator and Gates 79
expression. In particular, the 3-variable case can be converted to a Boolean expres-sion as follows:
X ⊕ Y ⊕ Z = (XY + XY)Z + (XY + X Y)Z
= XY Z + XYZ + X YZ + XYZ
The Boolean expression clearly indicates that the 3-variable exclusive- OR is equal to 1 if only one variable is equal to 1 or if all three variables are equal to 1. Hence, whereas in the 2-variable function only one variable need be equal to 1, with three or more variables an odd number of variables must be equal to 1. As a consequence, the multiple- variable exclusive- OR operation is defined as the odd function. In fact, strictly speaking, this is the correct name for the ⊕ operation with three or more variables; the name “ exclusive- OR” is applicable to the case with only two variables.
The definition of the odd function can be clarified by plotting the function on a map. Figure 2-22(a) shows the map for the 3-variable odd function. The four min-terms of the function differ from each other in at least two literals and hence cannot be adjacent on the map. These minterms are said to be distance two from each other. The odd function is identified from the four minterms whose binary values have an odd number of 1s. The 4-variable case is shown in Figure 2-22(b). The eight minterms
00
01
00 01CD
AB
C
D
A
11 10
11
10
B
1
1
1
1
1
1
1
10
1
Y
Z
X 1
00 01 11 10
1
YZ
X
(a) X Y Z
(b) A B C D
1
1
FIGURE 2-22Maps for Multiple- Variable Odd Functions
X
YZ C
P
XY
ZP
(a) P ! X ! Y ! Z (b) C ! X ! Y ! Z ! P
FIGURE 2-23 Multiple- Input Odd Functions
M02_MANO0637_05_SE_C02.indd 79 23/01/15 1:48 PM
N-Gates
Concep
t
P1 Other Gates
NAND Gate Z = X ⋅ YXY
Z = XXNOT Gate
NOR Gate Z = X + YXY
XNOR Gate Z = X ⊕ YXY
Summary
Review
P1 Other Gates
Summary• Delay: Remember the Definitions!
Review
P1 Other Gates
Summary• Delay: Remember the Definitions!
• Gate Delay and Propagation Delay
Review
P1 Other Gates
Summary• Delay: Remember the Definitions!
• Gate Delay and Propagation Delay
• Transport and Inertial Delays
Review
P1 Other Gates
Summary• Delay: Remember the Definitions!
• Gate Delay and Propagation Delay
• Transport and Inertial Delays
• Standard Load
Review
P1 Other Gates
Summary• Delay: Remember the Definitions!
• Gate Delay and Propagation Delay
• Transport and Inertial Delays
• Standard Load
• Other Gates: Remember the Definitions!
Review
P1 Other Gates
Summary• Delay: Remember the Definitions!
• Gate Delay and Propagation Delay
• Transport and Inertial Delays
• Standard Load
• Other Gates: Remember the Definitions!
• XOR, Buffer, 3-State, NAND, NOR
Review
P1 Other Gates