02) Lecture Plan

7/21/2019 02) Lecture Plan

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International Islamic University Chittagong (IIUC)

Department of Electronic & Telecommunications Engineering (ETE)

Lecture Scheme

Course Code EEE!""#$

Course Title Electrical Circuits I ! DC

Credit %ours $

Contact %ours per ee' $

Course *ective

1. Understanding of comprehensive idea of circuit variables and elements.

2. Understanding of techniques of circuit analysis, network theorems.

3. Understanding of energy storage elements.

4. Understanding of magnetic quantities and magnetic circuits.

. Understanding the analysis of first!order circuits.

Lecture +lan,

Course +lan ETE!""#$

-id!term E.am

"eek 1 #ircuit variables and elements$ %oltage, current, power, energy, independent

and dependent sources, and resistance

"eek 2 &irchhoff's current and voltage laws. (mmeter, %oltmeter, "attmeter ) *ther meters

"eek 3 +eries and parallel circuits

"eek 4 %oltage and current division"eek "ye!elta transformation

"eek - eduction of complicated networks

/esh and node circuit analysis including super node and super mesh

eduction of complicated networks

/inal E.am

"eek 0 /esh and node circuit analysis including super node and super mesh

"eek +ource transformation, hevenin's, orton's heorem

"eek +uperposition, /a5imum power theorem

"eek 16 /a5imum power theorem, eciprocity and +ubstitution theorems

"eek 11 7nductors and capacitors, series parallel combination of inductors and capacitors

"eek 12 esponses of 8 and # circuits$ atural and step responses

"eek 13 9lu5, permeability and reluctance, magnetic field strength, magnetic potential,

flu5 density /agneti:ation curve, 8aws in magnetic circuits$ *hm's law and

(mpere's circuital law

"eek 14 /agnetic ! +eries, ;arallel and series!parallel circuits analysis

<he instructor reserves the right to make minor changes in the above lecture plan.

Course Code ETE!""#0

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Lecture Scheme

Course Title Electrical Circuit I DC Sessional

Credit %ours "


List of E.periments

ETE!""#0

-id!term E.am

"eek 1 9amiliari:ation with the # #ircuit 8ab

"eek 2 esistance /easurements and esistor #olor #odes

"eek 3 %erification of *hm's 8aw

"eek 4 %erification of &%8 ) %oltage ivider ule

"eek %erification of &#8 ) #urrent ivider ule

"eek - 8ab est/inal E.am

"eek 0 7ntroduction to ;+pice

"eek (nalysis of elta!"ye network

"eek %erification of +uperposition heorem in #ircuit (nalysis

"eek 16 +tudy of hevenin's heorem in #ircuit (nalysis

"eek 11 %erification of /a5imum ;ower ransfer heorem

"eek 12 7ntroduction to (# circuit and elements.

"eek 13 8ab est


Course Code ETE!1$#$

Course Title Digital Electronics & Logic Design

Credit %ours $

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Lecture Scheme


Course *ective

1. Understanding of =oolean functions.2. Understanding of implementation of basic static logic gates in #/*+ and =i#/*+.

3. Understanding of the process of simplifying =oolean functions.

4. Understanding of combinational logic with /+7 and 8+7, sequential 8ogic.

. Understanding of counters, shift registers and their applications.

Lecture +lan,

Course +lan ETE!1$#$

-id!term E.am

"eek 1 igital vs. analog systems. (dvantages of digital system, (pplication of igital

system, igital waveform, ata ransfer, *,(, (, *, 7%>

7mplementation.

"eek 2 iode logic gates, ransistor +witch. 8ogic 9amilies$ 8, >#8, 778 and #/*+ logic

with operation details

"eek 3 =inary, *ctal, he5adecimal umbers, umber =ase #onversions, (rithmetic

operations

"eek 4 =ase #omplement$ +ubtraction using #omplements. =inary codes, =inary storage,

=inary logic, +witching circuits

"eek 9undamentals of =oolean algebra. =asic postulates$ fundamental theorems of,

=oolean algebra, switching functions, truth tables.

"eek - (lgebraic forms of switching functions. erivation of canonical forms, igital logic

gates, Universal logic gates

/inal E.am

"eek 0 9orms of =oolean functions, +hannon?s theorem, /inimi:ation of =oolean functions

using &arnaugh map, ( and * implementation

"eek #ombinational 8ogic$ esign of combinational circuits @(dders, +ubtractors, #ode

#onversionA

"eek ifference between combinational circuits and sequential circuits, ecoder, >ncoder,

#omparators, /ultiple5er, emultiple5er "eek 16 ;rogrammable logic devices$ logic arrays, field programmable logic arrays and

programmable read only memory

"eek 11 ifference between combinational circuits and sequential circuits, ypes of sequential

circuit, 9lip!9lops @=asic flip!flop circuit, clocked + flip!flop, flip!flop, B& flip!flop,

flip!flopA, riggering of 9lip!flop

"eek 12 (nalysis of clocked sequential circuits @state table, state diagram, state equationsA, state

reduction, state assignment

"eek 13 ypes of counters, esign of synchronous and asynchronous counter, /* number,

;ropagation delay in ipple counter, ,ing counter, he Bohnson #ounter, (synchronous

down counter, igital clock

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Lecture Scheme

"eek 14 =asic shift register, +erial 7nC+erial out shift registers, +erial 7nC;arallel out shift register,

;arallel 7nC+erial out shift register, =idirectional shift register, 7ntegrated circuit memory,

/agnetic!core memory


Course Code ETE 2 1$#0

Course Title Digital Electronics & Logic Design Sessional

Credit %ours "34


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Lecture Scheme

List of E.periments

ETE!1$#0

-id!term E.am"eek 1 9amiliari:ation with necessary resources of igital >lectronics +essional.

"eek 2 %erification of operation of different 8ogic Date 7# @(, *, *, (, *

and E*A.

"eek 3 7mplementation of different logic gates by diodes, transistors and resistors.

"eek 4 7mplementation of =oolean function by basic logic gates.

"eek %erification of Universal gates.

"eek - 7mplementation of a Falf!adder and 9ull!adder.

/inal E.am

"eek 0 9amiliari:ation with +even segment display and =# to seven segment decoder 7#.

"eek 7mplementation of multiple5er and de!multiple5er."eek 9amiliari:ation with flip!flops.

"eek 16 esign and implementation of synchronous counter.

"eek 11 esign and implementation of asynchronous counter.

"eek 12 7mplementation of +hift egister

"eek 13 8ab test.


Course Code ETE!05#5

Course Title 6LSI System Design

Credit %ours $


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Lecture Scheme

Course *ective

1. Understanding of %8+7 design technique and modeling.

2. Understanding of #/*+ circuit design, characteristics and applications.

3. Understanding the %8+7 fabrication processes.

Lecture +lan,

Course +lan EEE!05#5

-id!term e.am

"eek 1 esign 7ntegrated #ircuits. 7ntegrated #ircuit /anufacturing

"eek 2 #/*+ echnology. 7ntegrated #ircuit esign echniques. ( 8ook into the 9uture.

+ummary

"eek 3 /*+ device structure, design equations

"eek 4 hreshold voltage, body effect, 7!% equations and characteristics

"eek #/*+ process enhancements, layout design rules and latch up"eek - /*+ inverter, #/*+ inverter, pass!transistor and transmission gates

/inal E.am

"eek 0 esistance, capacitance, rise and fall times, delay of #/*+ circuit

"eek +witching characteristics, gate transistor si:ing and power dissipation

;rogrammable logic device$ ;*/, ;8(, ;(8, D(8, 9;D($8U, #8=, +=, esign

flow, #omparison

+emiconductor review, &ey working materials, *5idation, ;hotolithography, /*+

preparation, /*+9> preparation$ /*+, ;/*+, #*/+, "ell and +ubstrate aps

7on implementation$ #oncept, ;rocedures, +ome practical e5amples.

#%$ 7ntroduction, #haracteristics, /echanism, ypes.*5idation$ 7ntroduction, Drowth /echanism and &inetics, +i o5idation model,

9actors effecting o5ide growth rate, >pita5y, >tching, "afer cleaning, /etalli:ation,

;assivation

"eek esign strategies, #/*+ chip design options, design methods, design capture tools,

design verification tools, design economics! /*+ , /*+ and #/*+ process

"eek 16 F8s applications, ange of use, %F8 ! overview$ %F8 ! Fistory, %F8 !

(pplication 9ield, (+7# evelopment

"eek 11 (bstraction, (bstraction 8evels in 7# esign, (bstraction levels and %F8,

escription of (bstraction 8evels

"eek 12 =ehavioral escription in %F8, 8evel in %F8, Date 8evel in %F8,7nformation #ontent of (bstraction 8evels, /odularity and Fierarchy

"eek 13 Fardware escription 8anguages. egister!ransfer esign. Figh!8evel +ynthesis

eed for esting, /anufacturing est ;rinciples, esign +trategies for est, #hip

8evel and +ystem 8evel est echniques

"eek 14 (rchitecture for 8ow ;ower. (rchitecture esting

#/*+ +ubsystem esign $ ;arity Denerator, (dder, /ultiple5er, =us architecture,

crossbar switch, barrel shifter, ynamic switch egister, (8U, ynamic (/ cell

and pseudo!static (/ cell


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Lecture Scheme

Course Code ETE!05#7

Course Title 6LSI Design Sessional

Credit %ours "

Contact %ours per ee' 1

List of E.periments

ETE!05#7

-id!term E.am

"eek 1 7ntroduction to /icrowind

"eek 2 8ayout design and simulation of an /*+ inverter.

"eek 3 8ayout design and simulation of an #/*+ inverter.

"eek 4 8ayout design and simulation of 2 input logic gates.

"eek 8ayout design and simulation of 3 input logic gates."eek - 8ayout design and simulation of comple5 gates.

/inal E.am

"eek 0 8ayout design and simulation of logicCcomple5 gates in +#F.

"eek 8ayout design and simulation of /ultiple5er and +ubmitting the name of #lass

proGects.

"eek 8ayout design and simulation of (dder and 9inali:ation of #lass proGects.

"eek 16 7ntroduction to ;rogrammable logic design$ 9;D(

"eek 11 esign of (dder, /ultiple5er, and #ounter using 9;D(.

"eek 12 ;resentation on #lass proGect.

"eek 13 8ab test.<he instructor reserves the right to make minor changes in the above lecture plan.

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02) Lecture Plan

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