01b RISC CISC - unipi.it · RISC and CISC Instruction Sets • Nature of instructions distinguishes...
Transcript of 01b RISC CISC - unipi.it · RISC and CISC Instruction Sets • Nature of instructions distinguishes...
SISTEMIEMBEDDED
InstructionSetArchitecture:RISC/CISCAddressingModesAssemblyLanguage
FedericoBaronti Lastversion:20160308
InstructionsandSequencing• InstructionSetArchitecture(ISA)canbeseenasthespecificationsofaprocessor– ISAaffectsprocessorperformances(RISC,CISC,ASIP*)– PossibledifferentimplementationsofthesameISA
• Instructionsforacomputermustsupport:– datatransferstoandfromthememory– arithmeticandlogicoperationsondata– programsequencingandcontrol– input/outputtransfers
• Let’sstartbyintroducingsomenotation
2* Application-Specific InstructionsetProcessor
RegisterTransferNotation(1)• Registertransfernotation(RTN)isusedtodescribehardware-leveldatatransfersandoperations
• Source/Destinationcanbeeitherprocessorregisters(e.g.R0,R1,…)ormemorylocations(usuallymemoryaddressesarerepresentedbysymbols,suchasLOC,VARx,A,B,...)
• […] todenotethecontentofalocation• ← todenotetransfertoadestination• Example:R2← [LOC]
(transferfrommemorylocationLOCtoregisterR2)
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RegisterTransferNotation(2)
• RTNcanbeextendedtoshowarithmeticoperationsinvolvinglocations
• Example:R4← [R2]+ [R3](addthecontentsofregistersR2andR3,
placethesuminregisterR4)• Right-handexpressionalwaysdenotesavalue,left-handsidealwaysnamesalocation(i.e.,specifiesitsaddress)
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Assembly-LanguageNotation(1)
• RTNshowsdatatransfersandarithmetic(usefultodescribethebehaviorofaninstruction)
• Anothernotationisneededtorepresentmachineinstructions&programsusingthem
• Assemblylanguageisusedforthispurpose• ThetwoprecedingexamplesusingRTNcanberelatedtotheassembly-languageinstructions:
Load R2,LOCAdd R4,R2,R3
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Assembly-LanguageNotation(2)
• Aninstructionspecifiestherequestedoperationandtheoperandsthatareinvolved
• WewilluseEnglishwordsfortheoperations(e.g.,Load,Store,andAdd)
• Commercialprocessorsusemnemonics,usuallyabbreviations(e.g.,LD,ST,andADD)
• Mnemonics differfromprocessortoprocessor
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RISCandCISCInstructionSets
• Natureofinstructionsdistinguishescomputer• Twofundamentallydifferentapproaches– ReducedInstructionSetComputers(RISC)haveone-wordinstructionsandrequirearithmeticoperandstobeinregisters
– ComplexInstructionSetComputers(CISC)havemulti-wordinstructionsandallowoperandsdirectlyfrommemory
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RISCInstructionSets(1)• EachRISCinstructionoccupiesasingleword• Aload/storearchitectureisused,meaning:– onlyLoadandStoreinstructionsareusedtoaccessmemoryoperands
– operandsforarithmetic/logicinstructionsmustbeinregisters,oroneofthemmaybeprovidedexplicitlyintheinstructionword(Immediate operand)
– Loadproc_register,mem_location– Addressingmodespecifiesactualmemorylocation
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RISCInstructionSets(2)
• Considerhigh-levellanguagestatement:C= A+ B;
• A,B,andCcorrespondtomemorylocations• RTNspecificationwiththesesymbolicnames:
C← [A]+ [B]• Stepsinvolved:retrievecontentsoflocationsAandB,computesum,andtransferresulttolocationC
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RISCInstructionSets(3)
• SequenceofsimpleRISCinstructionsfortaskC=A+B:
Load R2,ALoad R3,BAdd R4,R2,R3(AddR3,R2,R3)Store R4,C(StoreR3,C)
• Loadinstructiontransfersdatatoregister• Storeinstructiontransfersdatatothememory.StoreusesthereverseoperandordercomparedtotheLoadorAddinstructions
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Assumptions:• Memoryis32-bitwordlengthandbyte-addressable
• Load/Storeinstructionshavethedesiredoperandaddressspecifieddirectly• Limitationsonusable
memorylocationsforvariablesbecauseofRISCsinglewordinstructions
• Needforalternativeaddressingmodes
InstructionExecution/Sequencing
• Howistheprogramexecuted?• Processorhasprogramcounter(PC)register• Addressi forfirstinstructionplacedinPC• Controlcircuitsfetchandexecuteinstructions,oneafteranother→ straight-linesequencing
• Duringexecutionofeachinstruction,PC registerisincrementedby4
• PC contentisi + 16afterStoreisexecuted
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Sumn numbersstoredinmemoryatconsecutivelocations(array)startingatlocationaddressNUM1• n isstoredatlocationaddressN
• ResultneedstobestoredatlocationaddressSUM
• Conditionalbranching• Registerindirectaddressingmode
LOOP
Branching
• Branchesthattestaconditionareusedinloopsandvariousotherprogrammingtasks
• Onewaytoimplementconditionalbranchesistocomparethecontentsoftworegisters,e.g.,
Branch_if_[R4]>[R5] LOOP• Ingenericassemblylanguagewithmnemonicstheinstructionabovemightactuallyappearas
BGT R4,R5,LOOP14
GeneratingMemoryAddresses• Loopmustobtain“Next”numberateachloopiteration
• Loadinstructioncannotcontainfulladdresssinceaddresssize(32bits)= instructionsize
• Also,Loadinstructionitselfwouldhavetobemodifiedineachpasstochangeaddress
• Instead,useregisterRi foraddresslocation– InitializeRi toNUM1andincrementitby4insidetheloop
– Thismethodworkswellforaccessingtheelementsofanarray
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AddressingModes(1)
• Programsusedatastructurestoorganizetheinformationusedincomputations
• High-levellanguagesenableprogrammerstodescribeoperationsfordatastructures
• Compilertranslatesintoassemblylanguage• Addressingmodesprovidecompilerwithdifferentwaystospecifyoperandlocations
• ConsidermodesusedinRISC-styleprocessors
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AddressingModes(3)
• RISC-styleinstructionshaveafixedsize,henceimmediate,absolute andindexmodeinformationlimitedto16bits
• Usuallysign-extendedtofull32-bitvalue/address
• immediate,absolute andindexmodeisthereforelimitedtoasubsetofthefull32-bitaddressspace
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32-bitImmediateValues• Toconstruct32-bitimmediates oraddresses,usetwoinstructionsinsequence:
OrHigh R4,R0,#0x2000Or R4,R4,#0x4FF0
• R0alwayscontains0• ResultisNUM1=0x20004FF0inregisterR4• Usefulpseudoinstruction forabovesequence:
Move(ImmediateAddress)R4,#NUM1– AssemblersubstitutethepseudoinstructionwithOrHigh &Orandappropriate16-bitvaluesforeachinstruction
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AssemblyLanguage
• Mnemonics(LD/ADDinsteadofLoad/Add)usedwhenprogrammingspecificcomputers
• ThemnemonicsrepresenttheOPcodes• Assemblylanguageisthesetofmnemonicsandrulesforusingthemtowriteprograms
• Therulesconstitutethelanguagesyntax• Example:suffix‘I’tospecifyimmediatemode
ADDIR2,R3,5(insteadof#5)
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AssemblerDirectives
• Otherinformationalsoneededtotranslatesourceprogramtoobjectprogram
• Howshouldsymbolicnamesbeinterpreted?• Whereshouldinstructions/databeplaced?• Assemblerdirectivesprovidethisinformation• ORIGINdefinesinstruction/datastartposition• RESERVEandDATAWORDdefinedatastorage• EQUassociatesanamewithaconstantvalue
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ProgramAssembly&Execution
• Fromsourceprogram,assembler generatesmachine-languageobjectprogram
• AssemblerusesORIGINandotherdirectivestodetermineaddresslocationsforcode/data
• Forbranches,assemblercomputes±offsetfrompresentaddress(inPC)tobranchtarget
• Loader placesobjectprograminmemory• Debugger canbeusedtotraceexecution
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ExampleProgram:DigitPacking
• MemorycontainstwoASCIIdecimaldigitsstartingataddressLOC.WewanttoextracttheBCDofthetwodecimaldigitsand“pack”themtoabytetobestoredatmemorylocationPACKET
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RISCSummary• Singlewordinstructions• OperandsofarithmeticandlogicoperationsinREGISTERSonly
• Load/storearchitecture(nomemorytomemorytransfers)
• Simpleaddressingmodes
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CISCInstructionSets(1)
• Notconstrainedtoload/storearchitecture• Instructionsmaybelargerthanoneword• Typicallyusetwo-operandinstructionformat,withatleastoneoperandinaregister
• ImplementationofC= A+ BusingCISC:Move Ri,AAdd Ri,BMove C,Ri
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CISCInstructionSets(2)
• MoveinstructionequivalenttoLoad/Store• Butalsocantransferimmediatevaluesandpossiblybetweentwomemorylocations
• Arithmeticinstructionsmayemployaddressingmodesforoperandsinmemory:
Subtract LOC,RiAdd Rj,16(Rk)
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AdditionalAddressingModes(1)
• CISCstylehasothermodesnotusualforRISC• Autoincrementmode:effectiveaddressgivenbyregistercontents;afteraccessingoperand,registercontentsincrementedtopointtonext
• Usefulforadjustingpointersinloopbody:Add SUM,(Ri)+MoveByte (Rj)+,Rk
• Incrementby4forwords,andby1forbytes
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AdditionalAddressingModes(2)• Autodecrementmode:beforeaccessingoperand,registercontentsaredecremented,thennewcontentsprovideeffectiveaddress
• Notationinassemblylanguage:Add Rj,−(Ri)
• Useautoinc.&autodec.forstackoperations:Move−(SP),NEWITEM (push)MoveITEM,(SP)+ (pop)
• SPistheStackPointerREGISTER,NEWITEMandITEMaretwogenericREGISTERS
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ConditionCodes
• Processorcanmaintaininformationonresultstoaffectsubsequentconditionalbranches
• Resultsfromarithmetic/comparison&Move• Conditioncodeflagsinastatusregister:
N(negative) 1ifresultnegative,else0Z(zero) 1ifresultzero,else0V(overflow)1ifoverflowoccurs,else0C(carry) 1ifcarry-outoccurs,else0
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BranchesusingConditionCodes
• CISCbranchescheckconditioncodeflags• Forexample,decrementingaregistercausesNandZflagstobeclearedifresultis> zero
• AbranchtochecklogicconditionN+ Z= 0:Branch>0 LOOP
• Otherbranchestestconditionsfor<,=,≠, ≤,≥• AlsoBranch_if_overflow andBranch_if_carry• ConsiderCISC-stylearray-summingprogram
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RISCvsCISCSummary• Singlewordinstructions• Operandsofarithmetic
andlogicoperationsinREGISTERSonly
• Load/storearchitecture(nomemorytomemorytransfers)
• Simpleaddressingmodes• Fasterinstruction
execution• Largersizeprograms
• Instructionsmayspanmultiplewords
• Operandsofofarithmeticandlogicoperationsmaybeinmemory
• Moveinstructionswiderscopethanload/store
• Morepowerfuladdressingmodes
• Smallersizeprograms• Slowerinstruction
execution
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RISCreduceshardwarecomplexityattheexpenseofthesoftwarecomplexity.Needforsophisticatedcompilers.
EncodingofMachineInstructions
• Assembly-languageinstructionsexpresstheactionstobeperformedbyprocessorcircuitry
• Assemblerconvertstomachineinstructions• Three-operandRISCinstructionsrequireenoughbitsinsinglewordtoidentifyregisters
• 16-bitimmediatesmustbesupported• InstructionmustincludebitsforOPcode• Callinstructionalsoneedsbitsforaddress
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