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Comparison between Different Data Buses Configurations

A. Lopez and D. Deschacht

Laboratoire dInformatique, de Robotique et de Microlectronique de Montpellier

UMR CNRS 5506, 161 Rue ADA, 34092 Montpellier Cedex 5, France

[email protected] [email protected]

Abstract

With increasing clock frequencies and shrinkingprocess geometries, both capacitive and inductive

crosstalk become important concerns in designs. In deep

sub-micron technologies, we can ignore neither theamplitude of the noise due to the coupling between bus

lines, nor the delay variation due to this crosstalk

voltage.

In this paper we study different design solutions on bus

configurations in order to take advantage of DSM

technologies, and evaluate their impact on crosstalk

reduction. The use of intra-layer low-k dielectrics,

reduces the coupling capacitances and a permittivity of

two reduces the crosstalk voltage by 22%. An electrical

screening ground lines solution between signal lines

exhibits favorable interest for a typical SoC structure.Space between lines can be significantly reduced for an

equivalent crosstalk voltage. Crosstalk and timing

performances of these different solutions are evaluatedand then compared. The reduction of the input switchingdelay with technology evolution leads to an important

increase in the inductive effect. These lines are modelled

as RC and RLC lines, and the two models are comparedto define the effects caused by neglecting inductance.

1. Introduction

With the reduction of distances between wires in deep

sub-micron technologies, coupling capacitances are

becoming increasingly significant. As a result theamplitude of the noise due to this coupling cannot be

ignored [1], especially as an on-chip bus crosstalk noise

poses a serious problem in VLSI design. In bus structures,crosstalk immunity is extremely important because long

interconnect wires often run together and in parallel.

Several factors relating to technology contribute to the

gravity of the crosstalk problem such as the increase inthe number of metal layers [2], the wire thickness which

is often greater than the wire width, the density of

integration and the reduction of the spacing between lines.

Closed-form formulas are particularly efficient whendetermining design rules. Recently, a number of simple

crosstalk noise models was proposed. The effects of the

coupling capacitance have been addressed by Shoji [3]

using a simple linear RC circuit, and by Becer [4] and

Vittal [5], using and L lumped-circuit models. Recent

models such as [6], [7] propose complex models ofprediction of crosstalk requiring complex calculations,and, as a result important CPU time. [8] proposes a

closed-form peak noise formula by assuming that there is

a saturated ramp input for the aggressor net. Most of thesemodels, however, did not consider the distributed natureof RC networks, which is necessary in deep sub-micron

designs. Servel [9] proposes an analytic expression of

crosstalk voltage for one, two and four adjacent lines,which takes into account interconnect capacitances, line

resistance and their distributed nature, driver resistance

and variable strengths of the buffers driving coupled lines.

The increasing operation speed of integrated circuitstogether with the increasing mean length of

interconnection may cause transmission line effects tobecome important [10] [11]. Consequently, because of theuse of wider wire for critical signals, inductance of theinterconnect when compared with its resistive component

can no longer be ignored. Using copper and wider wires

for critical signals are typically dependent on thetransmission line effect, and buses must now be modelled

as coupled transmission lines.

In this paper we highlight the impact of the use of

various dielectric materials in intra-layer configuration toreduce coupling capacitances and we will study their

impact on crosstalk reduction. This solution will then be

compared to the other one where we use screening linesbetween signal lines. The paper is organised as follows. In

the first part we show how we calculate the electrical

parameters to model the coupled lines for electricalsimulations. Then, we highlight the impact of the use ofvarious dielectric materials, to reduce the coupling

capacitances and thus the corresponding crosstalk

reduction. The design rules are determined so that there isa crosstalk voltage lower than Vdd/5 and the

corresponding timing performances evaluated. The lines

are also modelled as RC lines and the two models (RC

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and RLC) are compared to define the effects caused by

neglecting inductance. In the second part we study the

influence of ground lines which are adjacent at the two

signal lines. The similar performances are evaluated andin the last part we compare these two design solutions.

2. Impact of intra-layer dielectrics

2.1. RLCG equivalent parameters calculation and

crosstalk evaluation

The principles of the analysis we have followed in

order to obtain the numerical values of the R, L, C, G

equivalent parameters from which a set of coupled

transmission lines could be modelled, have beenpresented in [12]. This work has been carried out by using

commercial FEM packages developed for two

dimensional computation of electromagnetic problems

[13]. The accurate values of the R, L, C, G have beencalculated, for the geometry shown in Fig. 1 and Fig. 7.

9.3r =

9.3r1 1

1

1

0.8S

1 2 3

Fig. 1: Sketch of the studied structure consistingof three Cu lines, denoted from 1 to 3, spaced by

a dielectric material, and immersed in a SiO2matrix.

For this study, the interlines have been filled with

various dielectric materials, each with its own permittivity

r in order to enable us to study the integration of low-k

dielectric for coupling capacitance reduction. We can now

simulate the crosstalk voltage in percent with respect to

Vdd, , versus interconnection length, for differentpermittivity values, by keeping the space of 0.6 m

between lines. The corresponding electrical parameters

are given on Table 1. We have C11 = C33, and inductance

values are the same, whatever the intra-layer dielectricused : L11 = L22 = L33 = 0.36 nH/mm ; L12 = L23 = 0.0902

nH/mm and L13 = 0.0202 nH/mm.

Table 1: Calculated values of the capacities ofthe structure described on Fig.1.

r C11 fF/mm C22 fF/mm C12 fF/mm

1 111 89.9 31.9

2 118.7 91.2 46.4

3 125.1 92.3 60.8

Si02 130.7 92.8 75

We consider three copper adjacent lines ( R = 21.6

ohms/mm) in the worst-case configuration, that is to say

when the input of the aggressors changes from 0 to Vdd

and the input of the victim line is at Vdd. This is theconfiguration where we have the most important noise

voltage induced on the victim line. The buffer sizing iscalculated to keep a constant loading factor equal to 4,and a 0.5 m receiver size is used. The crosstalk

amplitude is obtained by HSPICE simulations, the

interconnections being modelled by an RLCG distributed

model and the buffers and load inverters with the foundryspecified card model.

2.2. Crosstalk reduction by using low-k intra-

layer dielectrics.

Fig. 2 shows the variation of the crosstalk amplitude with

respect to Vdd, versus interconnection length for different

intra-layer dielectrics.

0

5

10

15

20

25

30

35

40

45

50

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15Length of coupled lines (mm)

Vcrosstalk/Vddin%

epsilon 4

epsilon 3

epsilon 2

epsilon 1

Fig. 2: Simulated crosstalk voltage in percentwith respect to Vdd, for different intra-layerdielectric values.

As was expected, the use of an intra-layer low-k

dielectric, while decreasing the coupling capacitance, alsodecreases the crosstalk voltage. We can express the

lowering as :

!

T v P

h W p h y x

xy

h W p h y x

to have the percentage of the decrease versus

interconnection length. We show that using a low-k

dielectric equal to 3 reduces the crosstalk voltage by about12%, a low-k equal to 2 by 22% and a low-k equal to 1 by

37%. We can benefit from this decrease in terms of space

reduction between lines ; and in order to do so we plot the


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variation of the crosstalk voltage in percent with respect

to Vdd, versus oxide permittivity, for different spaces

between lines, Fig. 3. The coupled interconnections length

is 5mm.

10

15

20

25

30

35

40

45

0 1 2 3 4Oxide permittivity

Vcrosstalk/Vddin%

s=0,6

s=0,8

s=1

s=1,2

Fig. 3: Variation of the Crosstalk Voltage withrespect to Vdd, versus Oxide Permittivity for

Different Space (in m) between Lines.

If, when facing the signal integrity problem, thecrosstalk noise with respect to Vdd does not have an

amplitude greater than Vdd/5, we find that, for this

configuration the space between lines must be strictly

greater than 1.25m for SiO2 and greater than 1m for apermittivity equal to 2.

The crosstalk amplitude is at the first order dependenton the ratio of coupling capacitance over groundcapacitance (C12 + C23) / C22 , in this configuration.Whatever the oxide permittivity, the space between lines

must be determined to have a capacitance ratio of 0.47.

The corresponding electrical parameters are given inTable 2.

Table 2: Electrical Parameters for CrosstalkLimitation

C11fF/mm

C22fF/mm

C12fF/mm

L11nH/mm

L12nH/mm

L13nH/mm

SiO2,

S=1,25m

147 126.8 29.8 0.306 0.046 0.004

r = 2,

S = 1m

127.9 108.6 25.3 0.306 0.058 0.008

2.3. Timing performances

In this last case, an intra-layer with r = 2, we can now

determine the two most important timing performances :

that is to say, the latency and the output switching delay.

The latency is defined as the time when the ouput of the

line reaches 20% of Vdd, minus the time when the inputof the buffer reaches 80% of Vdd. We define the

transition time as the delay evaluated between 20% and

80% of the power supply, Vcc, representingapproximately the range Vtn and Vcc - | Vtp | , Vtn and Vtpbeing the threshold voltages. The transition time is thelinearization of the switching delay over Vcc. This

permits a better representation of the real signal waveformat the buffers output. The performances are evaluated for

a constant loading factor equal to four, calculated when

the two adjacent lines are in a constant logic level. In this

case, Cline is equal to: Cline = C22 + C12 + C23, where Cii

represents the ground capacitance, and Cij the couplingcapacitance between line i and line j. In the best-case,

when the three lines have the same logic transition C line,becomes: Cline = C22, and in the worst-case, when the two

adjacent lines have an opposite logic transition: Cline = C22+ 2 C12 + 2 C23. The load seen by the buffers is different,

consequently the performances are different. The resultsare shown on Fig. 4 and Fig. 5 respectively.

0

50

100

150

200

250

300

350

400

0 1 2 3 4 5 6 7 8 9 10

Length of coupled lines (mm)

Latency(ps)

Best-case

Worst-case

Fig. 4: Variation of the latency versusinterconnection coupled lines length

These results show the importance of the crosstalk-

induced-delay: we have an 80% variation between best-

case and worst-case for the latency and 190% for theoutput switching delay for a length of 5 mm. If we have a


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clock cycle of 1 GHz, we are always under a half cycle

time for a length of coupled lines lower than 10 mm.

0

50

100

150

200

250

300

350

400

450

500

0 1 2 3 4 5 6 7 8 9 10


Outputtransitiontime(ps)

Best-case

Worst-case

Fig. 5: Variation of the output transition time

versus interconnection coupled lines length.

To evaluate the impact of neglecting inductance ininterconnection modelization, we compare the variation,

in percent, between RLC and RC model line inperformance determination. The discrepancy rate is

dependent on the input transition time, so, for a possible

comparison we keep a constant loading factor equal to 4

for the middle line. All the buffers have the samedimensions. We show in Fig. 6, only the best-case for the

latency and the output switching delay (O.S.D.), which

corresponds to the lower input transition time and the

worst-case for the crosstalk voltage determination.

0

10

20

30

40

50

60

0 1 2 3 4 5 6 7 8 9 10Length of coupled lines (mm)

Discrepancyrateinpercent

Latency

O.S.D.

Crosstalk

Fig. 6: Discrepancy rate caused by neglectinginductance on performance evaluation.

The output switching delay is the more sensitive

parameter, the inductance decreases the output transition

time by around 50%, which is a beneficial effect, but it

also increases the crosstalk by around 25%. This showsclearly the importance of including inductance in the

interconnect model. A specific study of the influence onthe inductive effect will be the subject of future work.

3. Influence of ground lines adjacent at two

signal lines

To minimize the aggressor influence, we consider a

new interconnect configuration. Two signal lines areinserted between two constant voltage lines (electrical

screening), as shown in Fig7. In this configuration, with

the same geometric parameters for the interconnections,the dielectric material is the same in the entire structure.

Cu

1

Cu

2

Cu

3

S

W1

T

H

H

Cu

1T

W1W2

Fig. 7: Configuration of the studied structure

Here, the victim interconnect is perturbed by only one

aggressor line. As a result, the coupling capacities aredivided by two and the crosstalk voltage decreases. The

constant voltage can be Vdd or ground potential. Theimpact of these two potential levels is negligible for

crosstalk voltage. For the last generation circuits the

research aims to introduce the low-k material andsubsequently decrease interconnect capacitance. The goalconsists in improving the higher performance circuits.

Here, we change the dielectric material in the totality of

the structure. Fig. 8 plots the simulated crosstalk voltagewith respect to Vdd, for different spaces between lines

and an oxide permittivity of 2.5. A comparison is thenmade between S = 0.6 m by using SiO2 as usual.

Corresponding electrical parameters are given on Table 3.As expected this configuration reduces the crosstalk

voltage. For the crosstalk, we obtain similar results

between different homogeneous relative permittivity forthe same line geometry: at the first order crosstalk voltage

is dependent upon the coupling to ground capacitance

ratio. For this configuration, the ratio is : C 23 / ( C22 +

C12). If we calculate this ratio versus the space betweenthe lines, we verify that it is equal to 0.46 for S = 0.6 m.

For the same signal integrity constraints: crosstalk noisewith respect to Vdd does not have an amplitude greater

than Vdd/5, we find that the space between lines can bereduced to 0.6m.


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0

5

10

15

20

25

0 5 10 15


Vcrosstalk/Vddin%

S = 0.4 m

SiO2 (0.6m)

S = 0.6 m

S = 0.8 m

Fig. 8: Crosstalk voltage with respect to Vddversus interconnection length of coupled linesfor different spaces between lines and different

oxide permittivity values.

Units for table 3 are fF/mm for capacities and nH/mm

for inductances.

Table 3: Equivalent electrical parameters ofthe structure described on Fig. 7

r = 2.5 S = 0.4m S =0.6m S = 0.8m

C11 79.8 83.4 87

C22 52 59.3 66.1

C12 71.5 48 34.7

C23 70.9 49.3 34.5

L11 0.306 0.306 0.306

L12 0.1082 0.0921 0.0722

L23 0.1093 0.0901 0.072

L13 0.03 0.02 0.0103

3.1 Timing performances

To compare the timing performances, we determine

these performances, by using the same loading factor F =

4, when the signal line 2 (Fig.7) commutes, the adjacentline 3 being at a constant logic level. We have : Cline = C22+ C12 + C23 + C24. For the best-case, (B-C) Cline becomes:Cline = C22 + C12 + C24 and for the worst-case, (W-C) Cline= C22 + C12 + 2 C23 + C24 . We report here the results for

two different oxide permittivity: SiO2 and r = 2.5. Fig. 9

shows the latency variation and Fig. 10 the output

transition time variation.

0

100

200

300

400

500

600


Latency(ps)

B-C 2.5

W-C 2.5

W-C Si02

B-C SiO2

Fig. 9: Variation of the latency versus

interconnection coupled lines length.

0

100

200

300

400

500

600

700


Outputtransitiontime(ps)

B-C 2.5

B-C SiO2

W-C 2.5

W-C SiO2

Fig. 10 : Variation of the output transition timeversus interconnection coupled lines length.

Numerical calculation of Cline shows that the values

obtained with r = 2.5 are the same as those obtained with

the intra-layer low-k of 2 in the previous configuration.

The importance of the crosstalk-induced delay is aboutthe same, whatever the permittivity used. We have an

increase of 85% for the latency and 190% for the ouput

transition time, for coupled lines of 5mm. Using a lowerpermittivity than the one of SiO2 increases the

performances only above 3mm. For 10mm, the gain is


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around 50% for the latency and 70% for the output

switching delay for the permittivity of 2.5.

Fig. 11 shows the discrepancy rate between RLC and

RC models. We show that whatever the oxide permittivitythe amplitude of the discrepancy remains the same

(inductance values are independent of oxide permittivity),but, the inductance effect appears for lower values oflength, for SiO2 and the effect of a greater attenuation

factor reduces the range of length

concerned.

0

10

20

30

40

50

60


Discrepanv

yrateinpercent

Latency O.S.D.

Crosstalk Latency SiO2

OSD SiO2 Crosstalk SiO2

Fig. 11: Discrepancy rate between RLC and RCmodels on performance evaluation.

4. Conclusion

Different solutions of design have been studied to

evaluate their impact on crosstalk reduction, and to reduce

the coupling between lines. The use of intra-layer low-kdielectric exhibits favorable interest for a typical SOC

structure. To cite an example an intra-layer dielectric with

a permittivity of three reduces the crosstalk voltage by12% whereas one with a permittivity of two reduces it by

22%. If for the signal integrity problem, the crosstalk

noise with respect to Vdd, does not have an amplitude

greater than 0,2Vdd, we find that for a standardconfiguration composed of three lines, in an

homogeneous oxide, the space between lines must bestrictly greater than 1,25m. The space can then be

reduced to 1 m by using an intra-layer with apermittivity equal to 2. An electrical screening lines

solution has been proposed with which we obtain a

significant crosstalk voltage reduction. For this, twoground lines surround two signal lines and allow a

reduction of the coupling effect. With the screening

configuration, the space between lines can be reduced to

0.6m for the same crosstalk reduction constraint Timing

performances are equivalent, whether it concerns a first

solution using an intra-layer with a permittivity of 2 and a

space between the lines which is equal to 1 m, or in asecond solution with screening lines having a permittivity

of 2.5 and a space between the lines equal to 0.6 m. Theimportance of including inductance in the interconnectmodel has been clearly shown and a specific study of the

influence ofn the inductive effect will be the subject of

future work.

6. References

[1] L. Gal, On-chip crosstalk-the new signal integrity

challenge, IEEE Custom Integrated Circuits Conference, pp.251-254, 1995.

[2] Semiconductor Industry Association, National TechnologyRoadmap for semiconductors, 1997.

[3] M. Shoji, Theory of CMOS Digital Circuits and CircuitFailures, Princeton University Press, Princeton, NJ, 1992.

[4] M Becer, I. N. Hajj, An Analytical Model for Delay and

Crosstalk Estimation with Application to Decoupling,Proceedings of the IEEE 1st International Symposium on Qualityelectronic Design, March 20-22 2000, San Jose, California, pp.

51-57.

[5] A. Vittal, L.H. Chen, M. Marek-Sadowska, K.P. Wang, X.

Yang, Modeling Crosstalk in Resistive VLSI

Interconnections, Proceedings of the IEEE International

Conference on VLSI Design, January, 1999, pp. 470-475.

[6] M. Kuhlmann, S.S. Sapatnekar, K.K. Parhi, Efficient

Crosstalk Estimation, IEEE Int. Conf. On Computer Design :

VLSI in Computer & Processors, 1999, pp. 266-272.

[7] A. B. Kahng, S. Muddu, D. Vidhani, Noise and Delay

Uncertainty Studies for Coupled RC Interconnects, IEEE Int.ASIC/SOC Conference, 1999, pp. 3-8.

[8] J. Cong, D.Z. Pan, P. V. Srinivas, Improved Crosstalk

Modeling for Noise Constrained Interconnect Optimization,

ASP-DAC, 2001, pp.373-378.

[9] G. Servel, D. Deschacht, On-chip crosstalk evaluation

between adjacent interconnections, 7th IEEE InternationalConference on Electronics, Circuits and Systems, December,2000.

[10] F. Moll and all, Inductance in VLSI interconnection

modelling, IEE Proc. Circuits Devices Syst., Vol.145,n3,

pp.175-179, June 1998.

[11] L. He and all, Efficient inductance modeling for on-chipinterconnects, IEEE CICC99, pp. 457, 1999.

[12] G. Servel, D. Deschacht, F. Saliou, J.L. Mattei, F. Huret,

Impact of Low-k on crosstalk, Proc. 3rd

International

Symposium on Quality Electronic Design, San Jos,

USA,March 2002, pp.298-303.

[13] OPERA2D, Vector Fields, 24 Bankside, Kind-lington.


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