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IEEE JOURNALOF SOLID -STATE CIRCU ITS, OL. SC-9, O.6,DECEMBER1974 35 3 Macromodeling of Operational Integrated Circuit Amplifiers GRAEME R. BOYLE, BARRY M. COHN; DONALD O. PEDERSON, F EL LO W, I EE E, A ND JAMES E. SOLOMON, MEMB ER, IEE E Abstracf—A m a cr om od e l h as been d evelop ed for integrated circuit (IC) op amps which provides an excellent pin-for-pin repre- sen ta tion . Th e m odel elem en ts are t hose wh ich a re com mon to m os t cir cu it s im u la t or s. Th e m a cr om od el is a fa ct or of m or e t h an six times less complex than the original circuit, and provides simu- lated circuit responses that have run times which are an order of magnitude fa st er and less cost ly in com pa rison to modeling the op a m p a t t h e e le ct r on ic d evi ce le ve l. Expressions for the values of the elements of the macromodel are developed starting from values of typical response characteristics of the op amp.Examples are given for three representativeopamps. In addition, the performance of the macromodel in linear and non- linear systems is presented. For comparison, the simulated circuit p er for ma n ce wh en mo eling at the device level is a ls o d em on - strated. 1. INTRODUCTION I NTEGRATED circuit (IC) simulators have proven to be a useful t ool i;o the IC design engineer. None- theless, their widespread acceptance in the design of large-scale integrated ircuits and IC subsystems has been im peded by excessive simu lation co ts and incr eas- ing convergence problems. Present simulators model s em icon du ct or devices at the p-n ju nct ion a nd 2-t er min al element level. Becaqse c,f the large number of these de- vices in lar ge-sca le IC yyst em s, t he an alysis can surpass the com pu ter ’s m em or y ca pa bilit y, sim ula tor cir cu it -size capability, or the inheren numerical accuracy of the computer. Even if ~n adequate simulator and computer are available, the required simulation time makes the a na lysis fin an cia lly im pr act ica l. Thi~ paper describes on e solution to this problem: macromodels which have been developed for I C’S such as operational amplifiers and com p ar a t or s . The idea and use of acromodels in electronic circuit design is ver y com m on at the system level. For example, in developing an analc)g signal processor, on e might u tilize a nu mber of ideal volt age amplifiers, n t egr at or s, Ma n us cr ip t r ece ive d Au gu st 2, 1974; revised August 16, 1974. Th is research was sponsored in part by the Joint S er vices E lec- t ron ics Program under Contract F44620-71-C-0087 and by the N a ti on a l S ci en ce F ou n da t ion under Grant GK-17931. This p a pe r was presented at the International Solid-State Cir cu it s C on fer - ence,Philadelphia, Pa., February 1974. G. R. Boyle and D. O. P eder son are with the Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of C a li for n ia , B er k e le y, C a li f. B. M. Coh n is wit h I nt e)l Cor por at ion , S an ta Cla ra , Ca lif. J. E. Solom on is wit h N at ion al S em icon du ct or Cor por at ion , S a n t a C la r a , C a li f. and ot her subsystem block s. In effect , a va riet y of zer o- or der cir cu it m odels a re u sed. To determine the a ct ua l system per for ma nce, a r ot ot ype cir cu it is con st ru ct ed a nd ested at the device level. Th e size a nd com plexit y of t oda y’s in expen sive I C’S are large; t her efor e, the cost of u sin g present simu la tor s for design a nd eva lu at ion ca n be very large. The cost for large I C’S ca n only be ju stified if ver y la rge m a nu fa ct u re is a nt icipa ted. The cos ts and other problems can be relieved by the clevelop- ment of macromodels for I C’S wh ich p rovide an adequate pin -for -pin r epr esen ta tion of t he IC. For digita l IC’S, logic simulation and macromodels have been d evelop ed for digital logic blocks [1], [8]. For analog IC’S, this paper describes a very effective m a cr om od el that has been developed for IC op a mps [2], [3], [9]. The a im of m acr om odelin g is to obtain a cir cu it m od el of an IC or a portion of an IC which has a significantly r eclu cecl com plexit y to p rovicle for s ma ller , less cost ly simulation time, or to permit the simulation of la r ger I C’S or IC systems for the same time and cost. In the macro- model for IC op amps shown in Fig. 1, a reduction of approximately 6 in branch and node count has been a ch ieved wh ile pr ovidin g a very close a pp r oxim at ion to t he in pu t a nd ou t pu t ch ar acter istics, differ en tia l- a nd com m on -m od e gain versus frequency characteristics, qui- escent dc characteristics, offs et ch a r a ct er is t ics , and large- s ign a l characteristics, s u ch as slew rate, output volt age swing, and sh or t-cir cu it current lim it in g. Further, s in ce much of a simulation run is involved with iterative analysis to an equilibrium cir cu it solu tion , t he r ed uct ion of 60 t 80 p-n junctions in a n actual op amp to the 8 junctions in the macromodel of Fig. 1 indicates better h ow m uch fa st er a nd ch ea per can be the simulation u sin g the m acr om od els in st ea d of device-level moclels. The r e- sults with a mplifier s, t im er s, and filt er s t ha t a re cit ed in this paper show that a reduction in time of 6 to 10 is typical. In many design or eva lua tion sit ua tion s, it is not nec- essary to model an op amp in all of its performance characteristics. F or e xa m ple, m a xim u m s hor t -cir cu it cu r - rent limiting may n ot e of interest. If the elements in t h e m a cr om od el which provide this feature are eliminated, further simplification of the macromodel is obtained. As an example, the simulation time of the filter in Section IV is reduced by a factor of 1.4 if the current and voltage lim it er s are om it ted .

Transcript of 01050528

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IEEEJOURNALOF SOLID-STATECIRCUITS,OL.SC-9,O.6,DECEMBER1974 353

Macromodeling of

Operational

In tegra ted Circu it

Amplifiers

GRAEME R. BOYLE, BARRY M. COHN; DONALD O. PEDERSON, FELLOW, IEEE, AND

JAMES E . SOLOMON , MEMBER, IEEE

Abstracf—A macr om odel h as been d evelop ed for in tegr at ed

ci rcu i t (IC) op amps which prov ides an exce ll en t p in -for -p in repre-

sen ta tion . Th e m odel elem en ts a re t hose wh ich a re common t o

mos t cir cu it s im u la t or s. Th e m a cr omod el is a fa ct or of m or e t h an

s ix t imes les s complex than the or iginal ci rcu i t, and prov ides s imu-

la ted cir cu it r esp on ses t ha t h ave r un t im es wh ich a re a n or der of

m agn it ude fa st er a nd less cost ly in com pa rison t o m odelin g t he

op amp a t t h e e le ct r on ic devi ce le ve l.

Exp r es sion s for t h e va lu es of t h e e lement s of t h e macromodel a r e

developed s ta r t ing from values of typica l re sponse cha racte r is t ics

of the op amp.Examples a re g iven for th ree represen ta t iveop amps.

I n addit ion , t h e per formance of t h e macromodel in lin ea r a nd non -

lin ea r s ys tems is p r es en t ed . For compar is on , t h e s imu la t ed cir cu it

p er forma nce wh en m odelin g a t t he device level is a lso d em on -

strated.

1. INTRODUCTION

I

NTEGRATED circu it (IC) simulators have proven

t o be a useful tool i;o the IC design engineer . None-

theless, their widespread acceptance in the design

of large-scale in tegra ted circuits and IC subsystems has

been im peded by excessive simu lat ion cost s an d incr eas-

ing convergence problems. Presen t simulators model

sem icon du ct or devices a t t he p-n ju nct ion a nd 2-t er min al

element level. Becaqse c,f the la rge number of these de-

vices in lar ge-sca le IC yyst em s, t he an alysis can surpasst he com pu ter ’s m em or y ca pa bilit y, sim ula tor cir cu it -size

capability, or the inheren t numer ical accuracy of the

computer . Even if ~n adequa te simulator and computer

a re available, the required simulat ion t ime makes the

a na lysis fin an cia lly im pr act ica l. Thi~ pa per descr ibes

one solut ion to this problem: macromodels which have

been developed for IC’S such as operat iona l amplifiers

a nd compara t or s .

The idea and use of macromodels in elect ron ic circuit

design is ver y common at the system level. For example,

in developing an analc)g signal processor , one migh t

u tilize a nu mber of ideal volt age amplifiers, int egr at or s,

Ma nus cr ip t r ece ive d Augu st 2, 1974; r evis ed Augu st 16, 1974.

Th is r esea rch wa s sp on sor ed in p ar t by t he J oin t S er vices E lec-

t ron ics P rogr am u nder Con tr act F 44620-71-C-0087 a nd by t he

Na ti ona l Sci ence Founda t ion unde r Gran t GK-17931 . Th is p ape rwa s p re se nt ed a t t h e I nt er n at ion a l S olid -S ta t e Cir cu it s C on fer -

ence, Phi ladelphia , Pa. , February 1974.G. R. Boyle and D. O. P eder son a re wit h t he Depa rt men t of

E lect r i ca l Enginee r ing and Computer Sciences and the E lect ron ics

Resea rch Labora tory , Univers ity of Ca li forn ia , Berke ley, Ca li f.B. M. Coh n is wit h I nt e)l Cor por at ion , S an ta Cla ra , Ca lif.

J . E . Solom on is wit h N at ion al S em icon du ct or Cor por at ion ,San ta Cla ra , Ca li f.

a nd ot her su bsyst em block s. In effect , a va riet y of zer o-

or der cir cu it m odels a re u sed. To deter mine th e a ct ua l

syst em per forma nce, a pr ot ot ype cir cu it is con st ru ct ed

a nd test ed a t t he device level. Th e size a nd com plexit y

of t oda y’s in expen sive IC’S a re la rge; t her efor e, t he cost

of u sin g pr esen t simu la tor s for design a nd eva lu at ion

can be very large. The cost for large IC’S can only be

ju st ified if ver y la rge ma nu fa ctu re is a nt icipa ted. Th e

cos ts a n d ot her p roblem s ca n be r elieved by t he clevelop-

m en t of m acr omodels for IC’S wh ich p rovide a n a dequ at e

pin -for -pin r epr esen ta tion of t he IC. For digita l IC’S,

logic sim ula tion a n d macr omodels h ave been d evelop ed

for digita l logic blocks [1], [8]. For analog IC’S, th is

p ap er d es cr ibe s a ver y effe ct ive macromodel t h at h a s be en

developed for IC op a mps [2], [3], [9].

Th e a im of m acr om odelin g is t o obt ain a cir cu it m odel

of an IC or a por t ion of an IC which has a significant ly

r eclu cecl complexit y t o p rovicle for sma ller , les s cost ly

sim ula tion t im e, or t o permit t he s im ula tion of la r ger IC’S

or IC systems for the sa me time a nd cost . In the macro-

model for IC op amps shown in Fig. 1, a reduct ion of

approximately 6 in branch and node count has been

a ch ieved wh ile pr ovidin g a ver y close a ppr oxim at ion t o

t he a ct ua l per formin g op amp, i.e., a ccu ra te m odelin g oft he in pu t a nd out pu t ch ar acter ist ics, differ en tia l- a nd

common-mode ga in ve r su s fr equency charact er is t ics , qui-

e scent dc cha ract e ris t ics , offs et cha ract er is t ics , and la rge -

s igna l cha ract er is t ics , s uch as slew r a te, ou tpu t volt age

swin g, a nd sh or t-cir cu it cu rr en t lim it in g. F ur th er , s in ce

much of a simulat ion run is involved with itera t ive

a na lysis t o a n equ ilibr ium cir cu it solu tion , t he r ed uct ion

of 60 to 80 p-n junct ions in an actua l op amp to the 8

junct ions in the macromodel of Fig. 1 indicates bet ter

h ow much fa st er a nd ch ea per ca n be t he sim ula tion u sin g

t he m acr omod els in st ea d of device-level moclels. Th e r e-

su lt s wit h amplifier s, t im er s, a nd filt er s t ha t a re cit ed in

th is paper show that a reduct ion in t ime of 6 to 10 istypical.

In ma ny design or eva lua tion sit ua tion s, it is n ot nec-

essary to model an op amp in all of its performance

ch a ra ct er is tics . F or example, maximum shor t -cir cu it cu r -

r en t limit ing may not be of in terest . If the elements in

t h e macromodel wh ich p rovid e t h is fea t ur e a re e lim ina ted ,

fur ther simplifica t ion of the macromodel is obta ined. As

an example, the simulat ion t ime of the filter in Sect ion

IV is reduced by a factor of 1.4 if the cur ren t and voltage

lim it er s a re om it ted .

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354 IEEEJOURNALOF SOLID-STATEIRCUITS,ECEMBER1974

7 (Vcc)

1

RCIJ Rcz Vc+I11c,

:Rp

+va–6

3.(+)

@

-~ --INPUT STAGE IN TERSTAGE OUTPUT STAGE

Fig.1. Cir cu it d ia gr am of t he op amp macr omod el.

II . MACROMODEL DEVELOPMENT

The circuit model for an IC op amp which is devel-

oped in t his pa per is sh own in F ig. 1. Th e con figu ra tion ,

wit h a su it able ch oice of pa ramet er s a nd elem en ts, a ccu -

ra tely models a broad class of IC op amps. For a given

Op amp, t he m odel pr ovides a n essen tia lly pin -for -pin

cor respon den ce wit h t he op amp, a nd a ccu ra tely r epr e-

sen ts t he cir cu it beh avior for n on lin ea r dc, a c, a nd la rge-

s igna l t r ans ient r es pon s es .

The circuit of Fig. 1 is subdivided into three stages.

The in put sta ge consists of idea l t r ansist or s ~1 a nd Q,z

a nd t he a ssocia ted sour ces an d pa ssive elements, Th is

st age pr odu ces t he n ecessa ry lin ea r a nd n on lin ea r dif-

ferent ia l-mode (DM) and common-mode (CM) inpu t

ch ar act er ist ics. F or con ven ien ce, t he st age is design edfor unity voltage gain. The stage can be designed to

pr ovide desir ed volt age a nd cu rr en t offset s. As br ou gh t

ou t in t he n ext sect ion , t he ca pa cit or CB is u sed t o in tr o-

duce a second-order effect for the slew ra te [4], a nd thb

capa cit or Cl in t rod uces a s econ d-or der effe ct t o t he p ha se

response.

The DM and CM voltage gains of the op amp are

pr ovided by the linea r intersta ge a nd out put sta ge ele-

m en ts con sist in g of Gm , G,., R%, Gb, and Roz. Th e fu nc-

t ion of ea ch elem en t is pr esen ted in t he n ext sect ion . Th e

dom inan t t im e consta nt of the op a mp is pr odu ced with

t he in ter na l feedba ck ca pa cit or C2. A feedba ck con nec-

t ion in the m acr om odel is u sed for Ca in or der t o pr ovide

t he n ecess ar y a c ou tpu t r es ist an ce ch an ge wit h fr equ en cy.

In addit ion , the two nodes of C2 can be made ava ilable

to the out side wor ld in order tha t the circuit designer

can in t roduce the same compensa t ion modifica t ion as

might be added to the actual op amp. Not ice the com-

plete isola tion th at exists bet ween the input a nd the in-

ter ior sta ges. This leads t o a sim plifica tion of the fre-

qu en cy an d t h e s lew i-a t e p er forman ce s.

The ou tput st age provides the proper dc and ac ou t-

pu t resist ance of the op amp. The elements Dl, Dz, Rc,

[

Q,2

Q9

39 k R5

Q,, Q,O

3k R4

* 1Q13SA

6

Q,T100

~ R8

:j;:~,c. I INPUT I ,N:;TX

NETWORK STAGE

+&

OUTPUT

STAGE

F ig. 2. Cir cu it dia gr am of t he ICL8741 op amp.,.,,,..,

and Go produce the desired maximum short -circuit cur -

ren t . The element s D3, Vc and 114j VE are voltage-clamp

cir cu it s t o pr odu ce t he desir ed maximum volt age excu r-

sion.

Th e circuit m odel of F ig. 1 ha s been developed using

two ba sic macr omode lin g t ech niqu es : s implifica t ion an d

bu ild -u p. I n t he s implifica t ion t ech niqu e, r ep re sen ta t ive

por tion s of op amp cir cu it ry a re su ccessively simplified

by u sin g sim ple idea l elem en ts t o r epla ce n um er ou s r ea l

elements. Thus, the fina l model using this approach

bea rs a st r ong resemblan ce t o t he r eal circuit . In Fig. 1,

t h e in pu t s ta ge de sign is a n example of t he s implifica tion

t ech niqu e. I n t he bu ild-u p t ech niqu e, a cir cu it con figu -

r at ion com posed of idea l elem ent s is pr oposed to meet

ce rt a in ext ern a l cir cu it s pecifica t ion s wit hou t n ece ss a rily

resembling a por t ion of an actua l op amp circuit con-

figura tion. The build-u p technique is em ployed in t he

d evelopment of t he ou t pu t s ta ge.

To illu st ra te t hese a spect s fu rt her , con sider t he sch e-

mat ic diagram shown in Fig. 2 of the 741-type op amp

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BO1-LEtC1l.:ACROMODELINGOFOPERATIONALAMpL~~lERs 355

TABLE I

DI:SICiN I?CjUziTIONSFOR THE OP ANIPhL4cRoMoD,m,

V, = ~ = 25.85 mV for 300 K

1s, = I.sD, = 1~~4 = 8.10-” A

R, = 100 k!l

C.=+-c,R

1.2=1.–+

~, = IcI / IBI

(32 = IC2/ IB2

R. = 200/IRB

‘s2=d’ +%)1—= v*/Icl

9?n1

R ., = l/ 2m fo ~BC ,

c, =

l ?p =

Ga =

$ tan Ad

( Vcc + V. E )’/(F’, – VCC(.21CJ – V. E IE E)

I /Rc ,

G1

c. =R ,, (C iMRR)

R ,, = Ro-.c

R oz = Rout — Rol

avDRC1Gb = –—

R2ROZ

Ix = (21 JGbR , – Isc

I

R0,18C

SD1= ISD2 = Ix exp — — v,

(In tcr sil ICL8741 ). Th is t ype is t he m ost common , gen -

era l purpose IC op amp. In developing a macromodel

using the simplifica t ion technique, the circu it ry em-

ployed for biasing can be replaced with ideal passive

elem en ts (pu re cu rr en t a nd volt age sou rces).

Sim ila rly, t he a ct ive loa cl a nd ba la nce-t o-u nba la nce

convert er in t he input stage can be replaced with idea l

elemen ts. Fin ally, it is n ot n ecessa ry t o u se composit e

t ransistor s in the input stage. Thu s, as sh own in Fig. 1,

a , s im ple d iffer en t ia l s ta ge ca n be p rop os ed t o m oclel a c-

cu ra tely t he n on lin ea r in pu t ch ar act er is tic of t he op amp .

Th e op amp m acr om odel is developed k eepin g in m in d

exist in g IC sim ula tor s. Th erefor e, t he m odel con ta in s

on ly elem en ts wh ich a re common t o m ost IC sim ula tor s

(i.e., r es is tor s, ca pa cit or s, in du ct or s, d ep ende nt cu r ren t

s ou rces, in depen den t s ou rces , d iod es , a nd bip ola r t ra n-

sistor s). In addit ion , effor t is made to minimize the

n umber of p -n ju nct ion s. Th ese n on lin ea r elem en ts m ak e

n ecessa ry it er at ive an alysis t o obt ain t he equ ilibr iu m

sta te of the circu it . A reduct ion of the number of non-

lin ea r elem en ts lea ds t o sm aller sim ula tion t im e.

F or t he in pu t st age, ou r in vest iga tion s sh owed t ha t a t

lea st fou r idea l ju nct ion s wer e n ecessa ry t o pr ovide t he

n ee de d b ala n ced , n on lin ea r beh a vior in t h e macr omodel.

It wa s det er min ed t hat t he sim plest a rr an gemen t is t ha t

of Fig. 1 where the four idea l ju nct ions were obtained

wit h two idea l t ra ns is tor s, ea ch m ocleled wit h t he lowes t

order Ebers–Moll (E–M ) t ransistor model which in-

cludes two ideal p-n junct ions and two dependent cur -

r en t sou r ce s.

For the out pu t stage, a simplified model of an actua l

op a mp does n ot pr ovide t he best solu tion . A st rippecl-

down class-AB stage with ideal t ransistor s leads to a

br an ch cou nt , of over 13 in com pa rison wit h 11 br an ch es

in t he ou tpu t st age of F ig. 1. In a cldit ion , t he cla ss-AB

stage must be augmented with voltage limiters in the

dr ive cir cu it ry t o lim it t he volt age excu rsion a t t he t ra n-

sistor bases to t he supply potent ia ls. It was foun d tha t

t he idea lized bu ilt -u p p roced ur e p rovid es a n ou tp ut s ta ge

wh ich is con sid er a bly s impler .

III. PARAMETERS AND ELEMENT VALUES

OF THE MACROMODEL

I n t h is s ect ion , exp res sion s a re d evelop ed t o r ela te t he

performance of the op amp and the macromodel to the

parameter s and elements of the macromodel. A sum-

mary of all design equa t ions is present ed in Table I.

Th e det erm in at ion of t he elem en t valu es of t he ma cr o-

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356

model proceeds from the input , t r ansfer , and output

ch ar act er ist ics of t he op amp.

The Input S tage: Icl and CB

The value of the necessa ry collector cur ren t of the

first stage is established by the slew r ate of the op amp.

If the op amp is connected as a voltage follower , the

pos it ive going s lew ra t e L%+is

(1)

where an n-p-n stage has been assumed [4]. From a re-

a r r angemen t of t h is exp res sion

For a qu iescent situ at ion , equ al collector cu rr en ts a re

u sed in t he in pu t st age ICZ = IcI.

Th e n ega tive goin g slew r at e SE - is sm aller beca use of

the cha rge-storage effect s in the input stage which is

modeled by C~ [4].

or

(3)

21C,c. = ~B_ – c,. (4)

If SE’ < Sri-, the macromodel should be modified to

u se p-n -p t ra nsist or s in t he in pu t st age. In t he equ at ion s

above #R,+and 81?- s hou ld t h en b e in t er ch anged.

In a ddit ion to th e tr ansien t slew r at e effect s, th e ele-

men t CE a lso in tr odu ces a desir able modifica tion t o t he

ac response of the CM gain of the macromodel.

The Trans is t or Parameters

Th e va lu es of 131a nd #Z for t he two idea l t ra nsistor s

a re obt ain ed fr om th e specifica tion s for th e a ver age in-

p ut bia s cu rr en t IB a nd t he desir ed level of in pu t cu rr en t

offset IBOJ.

IB1=IB+LB$, I.,=IF~. (5)

pl=~, & = ~. (6)

Th e volt a ge offs et Vo, for t he m acr omodel is p rod uced

by specifyin g differ en t sa tu ra tion cu rr en ts Is for t he t wot ra nsist or s. Assu me a given va lu e for Isl of QI

(7)

where VT = hT / q = 0.02585 V a t T = 300 K. A sim ila r

expr ession h olds for Icz = Icl

VBE2 .Ic, = 1s, exp ~

T(8)

IEEEJOURNALOF SOLID-STATEIRCUITS,ECEMBER19

vos = VBE1 – vBE2

= V.ln*. (9S2

This leads to

I S2 “-%-=1+%1 “T he In pu t S tage: R ., an d R ,l

Va lu es for t he r esist or s R,l = R ,z a re der ived fr om

t he r equ ir ed va lu e of t he O dB fr equ en cy j~ ~E of t he fu lly

compensated op a mp. The O dB frequency is approxi

ma tely th e pr odu ct of t he DM volta ge goin g a ~~ a nd t h

–3 dB cor ner fr equ en cy fs t E of t he ga in fu nct ion

fOdB = aVDj3dB. (11

Th e cor ner fr equ en cy ca n be est im at ed u sin g a Miller

effect a pp roxima tion in t h e in t er ior s ta ge.

The DM voltage gain a t very low frequencies is

(12

av~ = (G.R J (G5ROJ . (13

G. is chosen to be equal to l/R,l in order to obta in

con ven ien t slew r at e expr ession a s in (1). Th e la st t hr e

exp re ss ion s le ad t o

or

R., = ‘—-.2~f0‘BC2

(14

(1

Alt er n at ely, a r ela t ion sh ip b etween fod~and Sn+ can b

wr it ten u sin g (1).

‘0 ‘B = 2TR f;IcJ “(1

The value of R.l is usu ally sma ll, of t he or der of 2/g~

Rcl and RC2 should be small in order that sa tura t ion o

t he in pu t sta ge (a nd con comit t ent Ia tch up of th e op am

model) is a voided wit h m axim um in pu t. Th e r esist an ce

R,l a nd R.2 in t he in pu t st age a re int roduced t o pr ovid

a degree of freedom with respect to slew rate and O dfr equ en cy, a nd t o sim ula te bet ter cer ta in op amps wh ic

u se em it ter r esist or s for slew r at e en ha ncem en t, e.g., t h

LM118. R.l is found from the I)M voltage gain of th

fir st st age, wh ich for con ven ien ce is t aken t o be u nit y.

v5_ DIR., + @,R ., ———

= A= 1. (1

Vi*~ + (A + ORI + : + (B2 + DR.2

.

Th e offs et volt age is

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BOYLEe~Uz.:MACROMODELINGOFOPERATIONALMPLIFIERS

T he Inpu t S tage: IBB a nd R n

The value of the dc current source in the input stage

for equ a l collect or cu r rent s is

(19)

The resis t or RE is a dded t o pr ovide a fin ite GM in pu t

r esist an ce. Beca use t he cu rr en t sou rce IDE is oft en r ea ]-

ized wit h a n n -p-n t ra nsist or , t he r esist an ce R B is taken

a s it s ou t pu t r es is ta n ce

(20)

where VA is the ear ly voltage of the device. VA for a

sm all n-p-n t ra nsist or is typica lly 200 V.

T he In pu t S tage: Cl

To in tr odu ce excess ph ase effect s in t he DM amplifier

r esponse, another capacitor Cl is added in the input

stage. The second pole of the DM gain funct ion is lo-

ca ted a t

p, = – l/2Rc,C,. (21)

Notice tha t there is no in teract ion amongst the three

ca pa citor s beca use of t he u se of u nila ter al devices a nd

stages.

The excess phase a t ~ = f. ~Bdu e t o t he n on dom in an tpole pz is

%rfOB 2C,

’44 = ‘a n-’ IP21 = t an -’ (2r f0 .,)(2RCIC,) = t an -’ ~.

(;2)

Th e ph ase m ar gin of t he DM open -loop r espon se is t hen

& = 90° – A~. (23)

The n ecessa ry va lu e of Cl to pr odu ce t he excess ph ase is

C’, = $ t an A+. (24)

DC Pow er Dv ain

To model the actual dc power dissipat ion of an op

amp, a r esist or RP is in tr odu ced in to t he m acr omodel.

For the circu it of Fig. 1, in a quiescent sta te, the power

d is sipa tion is

P, = Vcc21c1 + VEJE, +(Vcc + v..)’

R,(25)

‘Th e n ecess ar y va lu e of RP to p rod uce t his d iss ipa tion is

R= =(v,, + VEE)

P. – Vcc21c1 – VE.IEE’(26)

In a typical op amp, most of the cur ren t drain from

t he volt age su pplies is du e t o diode-r esist or cu rr en t de-

fining pa ths. Therefore, a s the supply voltages are

357

changed, the current drain var ies almost linear ly and

RP will con tin ue t o model a ccu ra tely t he power clis sipa -

tion.

The Interstate: G., R ,, and G,,,,

As in dica ted ea rlier , t he coefficien t G. of t he volt age

depen den t cu rr en t sou rce Ga va is ch osen equ al to l / R~l

for con ven ien ce. Sim ila rly, t he va lu e of Rz or G~ can be

a rbit ra rily ch os en . On ly t he p rodu ct is det ermin ed by t heDM ga in . F or “a ct ive r egion ” con sid er at ion s, t he ch oice

of R2 is n ot impor ta nt . H owever , it m ust be kept in min d

th at t he volt age r espon se a t n ode b is lin ea r wit h R2. If

too large a value of v~ is developed dur ing a t ransien t

excu rsion t hr ou gh t he a ct ive r egion of t he op amp, a con -

s ider able disch ar ge or r ecover y t im e ca n be en cou nt er ed

a fter t he a ct ive r egion excu rsion . To pr even t t hese dis-

charge delays in rela t ion to actual op amp behavior , a

sma ll value of R2 should be used. Empir ically, a value

of 100 k ~ is fou nd t o be a ppr opr ia te.

I f a secon d volt age-con tr olled cu rr en t sou rce is in tr o-

d uced acr os s Rz, the CM voltage gain response can be

in tr odu ced. Th e CM volt age ga in in t he in pu t st age fr om

vi. to v, is approximately unity since Rn is la rge. Th e

CM voltage gain from the input to VOis then approxi-

mately

The differen t ia l voltage gain fr om the input to v~ is

v~~~. G.R , = EL R,. (28)

v,n~~ c1

The CM reject ion rat io (CMRR) is the rat io of the two

ga in s [5]

1

CMRR = a: = Rc,G; ”(29)

Therefore,

———““ = (CM;R)R.,

(30)

The dominant behavior of the CM frequency response

will be approximately the same as the DM frequency

r espon se except t ha t t he pr esen ce of t he ca pa cit or Cm i n

t he in pu t st age in tr odu ces a t ra nsm ission zer o in t he CM

gain funct ion at – l / RBCB.

T he Ou tpu t S tage: R ~l, R U,, an d Gb

The output stage provides the desir ed dc a nd a c out -

pu t r esist an ces a nd t he ou tpu t cu rr en t a nd volt age lim i-

t at ion s. F rom F ig. 1, it is seen t ha t t he ou tpu t r esist an ce

a t ver y low fr equ en cies for t he qu iescen t st at e is

R 0“ t = R,, + R ,,. (31)

At h igh fr equ en cie s, RO, is sh or ted ou t by t he (cu rr en t)

Miller -effect ou tp ut ca pa cit an ce a cr os s it d ue t o Cz. Th e

effect ive sh un t ca pa cit an ce is C,fi e CZ( 1 + R2 Gb). For

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358

th e situ at ion wher e a la rge loa d r esist an ce is pr esen ted

to the macr omodel, the corner frequency of the ou tpu t

imped an ce is

(32)

For frequencies well above th is value, the ou tpu t re-

s is ta n ce is RO1.Therefore,

R,, = R , . . . . (33)

Wit h th is va lue est ablish ed, Roz fr om (31) a nd G~ fr om

(13) a re

R,, = Ro., –R ,, (34)

and

aV~RC1

“ = Z,E,”(35)

T he Ou tpu t S tage: Cu rren t L im itin g

In th e ou tpu t st age of F ig. 1, t he desir ed out pu t-cu r-

r en t lim it in g is pr ovided by t he elem en ts GcV6, Rc~ Dl,

D2, and Rol. Th e R c, GCV6 combin at ion is a n equ iva -

len t t o a volt age-con tr olled volt age sou rce (wh ich is n ot

a va ila ble in sim ula tor s su ch a s pr ogr am SP ICE). T hu s,

V,..t = V6 a ls o app ea r s a cr os s Rc. If bot h of t he volt age-

clamp diodes D3 and D4 are off, the maximum

to the ou tpu t is the ra t io of the potent ia l a cross

and RO1

V. = V, I n $:

Ix Maximum cu rr en t t hr ou gh D, or D,.

18~, Sat u ra t ion cu r re nt of d iod es D,, D,.

current

Dl, D2,

(36)

(37)

Since Rol is known, 1~~1 can be established once Ix is

determined. In Fig. 3, a reduced por t ion of the ou tpu t

sta ge is shown which applies for a posit ive ou tpu t ex-

cursion, and where a very small load resist ance is as-

sumed. A Th 6ven in equ iva len t for G~v~ a n d R02 is u sed.

Th e Th 6ven in op-en -cir cu it a va ila ble volt age is a r~vi..

An idea l volt age-con tr olled volt age sou rce V. is a lso u sed

in place of GCV6 and Rc. Assume fir st t ha t t he volt age

a vDv,i. is n ot la rge. Th e ou tpu t cu rr en t flowin g t hr ou ghthe re sis t or Rol t hen pr odu ces on ly a sm all volt age dr op.

The polar ity of the volt age v. is such as to forwar d bias

diode D,. If the voltage drop across Ro, is sma ll, t he

cu r r en t t h rough D1 is very small and can be neglected.

As a v~vi, in cr ea ses, so does IL a nd the voltage dr op

a cr oss Rol. As t he la tter a ppr oa ch es t he ‘(ON” volta ge

of Dl, i.e., t he volt age for a ppr ecia ble cu rr en t t hr ou gh

the diode, the increasing cur ren t from the source IDI

flows t hr ou gh t he d iod e. I L is t hen a ppr oximat ely lim it ed

beca use of t he expon en tia l in cr ea se of 1~1 wit h r es pe ct

IEEEJOURNALOF SOLID-STATEIRCUITS,ECEMBER197

v~ ROI

-m-

DI ~IXlL~ +

R02

+ +v~

avdvinV.

. . .

F ig. 3. S implified cir cu it d ia gr am of t h e ou t pu t s ta ge

to I~Rol. Th e a ppr oxim at e lim it in g con dit ion is fou nd

from

I. = I.., exp 9T

Th e lim it in g va lu e of

con dit ion a t th e input .

r en t fr om Gbvb is I~~x

Im ax = Ix

(38

lx is det erm in ed by a n over dr ive

Th e s hor t-cir cu it a va ila ble cu r-

+ I scs = 21c,R ,G ,,. (39)

A t ypica l va lue of &.X is 100

F rom t he equ at ion a bove,

I –I –IxSD1— ,SD2—

A.

@d-R*) ’4F or la rge r equ ir ed va lues of Rol, the value of ~fl~l can

be ext remely small which may lead t o numerica l diffi-

cu lty. In many applica t ions when the ou tpu t resist ance

is n ot cr it ica l, a smaller value of Rol can be us ed neglect -

in g t he exa ct r ea liza tion of Ro–~c, e.g., if lsD1 = ~~1,

R,, C-S ~v~n ~. (41Sc 81

R oz is t hen in cr ea sed t o Rout – ROI, a nd G~ is decr ea sedto main ta in the same value of the G~ Roz product.

I n or der t o a pp roxima te well a volt age-con tr olled volt -

age sou rce , Rc must be very sma ll. If the volt age drop

across Rc is to be only 1 percen t of VD1 or VD!2 ,

R.=&100IX

In ~ IK .SDl

(42

Th e n ecessa r y va lu e for t he volt age-con tr olled cu rr en

sou rce GCV6 is

(43

Th e Ou tp ut S t age: V oltage L im it in g

Th e ou tput volta ge excur sion is lim ited by th e volta ge

sou rce -d iode clamp combina t ion s Vcj D3 and VE, D 1

shown in Fig. 1. With a large, posit ive ou tpu t volt age

su ch a s t o for wa rd bia s D3

v+ut = Vcc – Vc + VD3

l..+=Vcc–Vc+V.ln~- (44

As indica ted a bove, the diode curr en t is limited to the

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BOYLE43U1.:MACROMODELINGOFOPERATIONALMPLIFIERS 35’9

TABLE II

CIRCUITDATA .4NDGUMMEL-POON TRANSISTORPARAMETERSFORTHE ICL8741OP AMP

CLrCUit Data-.

Guom.1-Poon Tr an sis tor ?a r.m et ms

‘E1.mmt Nodes value.mMODEL_13NPi_ NGP_ 0FII=209. _ 8QM=2. 5__

,?~RLI= 670 .._

02 17 1.0< + RC=300. CC7=1.417P TF. I.ISN TX= 405. N

R2 Ez 16 50. { + CJE. O.55P CJC=O. S6P 1s. 1.26 E-15 V2=178.6

—R3— 02 18 l.o K____+. CZ= 1653._ IK=l.611M _NE.2. o PE=c .60_

Fib 02 08 3.0 K + MS=3. PC. O.45 ric=3.

04 05 39. K .MO13EL

—zz——

SNP2 NGP 13FM=400. BRM=6. I Ril= 185.

12 26 77. + _.RC= 15. CC S.3.455P_. iF=O.76N__TR. 243. N_

Q7 12 25 22. + CJE=2.80P CJC=l.55P IS= 0.395:-15 IVA.267. O

32 2s 100. + C2= 1543. IK=lO. OOH

—~: —

NE=2. O

02 21 50. K

PE=o . 60

.—.+ —-—— .ME=3. Pc=o. k5RIO Zk 27 40. K

XC=3. _.!400EL 8PN1 PGP QFM= 75. ERM=3.8

Rli

Ru= 500.

02 22 50. K + RC=150. CC S=2.259P TF=27.4N TR=2540. N

.c.— 15 19 30. P__+__ _cJE. o.io P___cJc=i.05P___ Is= 3.i5E-i5 vA.55. il_

&l 10 07 13

10 06 11

—:$—— 14 09 13

Q4 15 09 ii

14 16 17

—.:;— 15 16 18

01 14 16

10 10 Oi

__::___ 09 10 01

010 09 05 08

oil 05 05 02

DNPI + C2= 1764. IK=270. ou NE=2,0 ?E=O.45

ONP1 ME=3. PC= C.45 tlc=3.

oPNl__:M00EL_BPN2_ PGP..._ - BFM=117. _--_--B RM=8.8 RB= ..80. _

8PNi + Rc=i56. TF.26.5N TR=2430. N

6NP1 + CJE=4.05P CJC. Z. 80P Is= 17.6E-15 Vfi=57.94

P.NP1 ——_— .— .——— ——— ——-. .—. ——

13NP1

QPPJ1 + CZ= 478.4 IK=590.7u N:=2. o PE=o.60

BPN1_.+ –— . .._. ME=4 . . . ..—. .PC=O.60 -–—

BNP1 .MOOEL BPN3 PGP

14C=4..

BFH=i3.8 13RM=1.4

ENPi +

RB=1OO.

RC= 80. CC S=2.126P TF. z7.4N T?= 55. N

_Q12 _D4 04 01

0i3A 20 04 0:

Q13B 19 04 01

_fli4 ___Ol 20 26

Q15 20 26 12

Qlb of 15 21

_G:7_ .19 21 23

018 20 27 24

219 20 20 27

_ Q20__.02 24 25

a2i 22 25 12 BPN1 + CJE=i.10P CJC=2.40PQZ2

IS= 0.79E-i5 VA=79.45

15 22 02 BxPi + Cz= 12!9. IK=$o.55u h ’E. z .o P := C .6P

_.-oz3A_., 02 i9 24 BP)/5_” +___ ME=4 . PC= D.60. —___ MC=+. -,

ciz3a 02 i9 15 OF’N6 .MOOEL BPN6 PGP BFII= 19.

Q24 22 22 C2 BNP1

C!w. i.fl RU= 6SC.

[:lNc=ioo, T<r=2G.5N Tfl=2i20. M

cJE. i .9 0P.— cJC=2.40P— Is=0,0063E-15 ‘JA=i67 -l_

+ C2=5?. I+9K IK=80.55U

+

NS=Z. O PE=o.60

Mg.4 . pG. o.60 UC=+.

OPNi + CJE=O.lOP __._ CJC=O.30P__ IS= 2.25E-15

aPN 3—-+ C’2=84.37K IK.5. ooi3N N[=z. o

BPN4 + t+E=3, PC= O.45 !ic=3.

3N?2__ .HOQEL__BPN4_ PGP_ aFM=i4.8 _ BRM=l.5_.

BNP1 + RC=120. CCS=Z.126P

r3NPi + CJE=O. IOP

TF.27.4N

CJC=0,90P Is= 2.25E-15

L3!lPi. _.+.— cz. ?4.37K_ IK=ii:.8U _ !! E=2. O___

3!4?1 + tlc=3. PC. O .45

BNPi

NC=3.

.I{ODFL BPN5 PGP !3Fli= 80.

BPN2

ORM=I.5

__+__– -.. RC=170. _ _.__. _TF=26.5N _

~vA=s 3.55_

PE=O .95

RD=i60. _

TR= 220. N

VA=83 .55

Pi. C.i5 _

!2.0=1100.TR=9550.N—

short current I,yo+.The nece ssa ry

Similarly,

v. = v.. + v.”,- +

The Comp let e Model

bia s volt age is

V, in ~;. (45)SD3

TABLE I II

OP AMPPERF ORMANCEHt iR.kCT~RISTICS

8741 LM741 LM118Device-Level 8741 Data Data

Model Macromodel Sheet Sheet

v InI&~T (46) C, (pF )

I“ D4 SE+ ( v/p s )

A su mm ar y of t he design equ at ion s for t he pa ra met er s

of the macromodel is given in Table I. An example of

th e u se of t hese equ at ion s is given in t he Appen dix. Th e

:st ar tin g poin t is op a mp per forma nce da ta .

Th e p ar ticu la r IC u sed t o illu st ra te t he design p roced -

u re wa s t he object of a n ear lier stu dy [6]. Th e configu -

rat ion of th is IC was established to be that of Fig. 2 and

t h e t r an sis tor s wer e cha ra ct er ized by t h e Gumnlel–P eon

(G-P ) p ar amet er s of Ta ble 11.1

P rogr am SPICEha s been u sed t o es ta blis h t h e per for n l-ance and character ist ics of the op amp [7]. The r esult s

are summarized in Table III, column 1. These values

are used in the Appendix to develop the element and

par am et er valu es of t he m acr om odel. As br ou ght ou t in

t he Appen dix, sever al par amet er s of t he macr om odel

cou ld be chosen a rbit r a rily:

1 A sligh t m odifica tion of t he G–P pa ramet er s of t he ou tpu tt r ans is tor s ha s been made to p roduce a typ ica l leve l of maximumshor t-circuit available current .

SR- (v//.Ls)

I fl (nA)In.. (nA)V., (mV)

Ct iRR (dB)R .., (Q)

R .-.c (Q)

I sc+ (mA)

Z,SC-(mA)

v+ (v)

v- (vj

Pd (mW)

30

0.9

0.72

256

0.7

0.29!?

4.17.10’

1.219.103

16.8

106

566

76.8

25.9

25.9

14.2

–12.7

59.4

300.8990.718

255<1

0.2984.16.10’1.217.10’

16.310656676. S26.226.214.2

–12.759.4

300,670.62

802012.10’

103

20

90

75

252514.0

–13.5—

510071

120622,. ]05

16.10$40

10075

252513

– 13—

T = 300 K(V, = 25.85 mV),

Is, = Ism = 8.10-” A,

R , = 0.1 MQ,

wh er e 1s 1, 1s~3 ar e the satur at ion currents of the fir st

t r an sis tor a nd t h e volt a ge-lim it er cliod es , r es pect ively.

In a ddit ion , t he m ajor com pen sa tion ca pa cit Qr is fixed

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360 IEEE JOURNALOF SOLID-STATEIRCUITS,ECEMBER19

TABLE IV

MACROMODELARAMIJTICRS

8741 LM 741 LM 118

T (K) 300 300 300

Is, (A) ~ .10-16 8.10-16 8.10-16

I~D, (A) 8.10-16 8.10-16 8.10-16

R, (ka) 100 100 100

C, (pF) 30 30 ~

C~ (pF) 7.5 2.41 2.042

& 52.6726 111.67 2.033.103

P2 52.7962 143.57 2.137.103I~E (PA) 27.512 20.26 500R~ (m~) 7.2696 9.872 0.401,$, (A) 8.0925 .10-’6 8.309.10-1$ 8.619.10-’8R., (Q) 4352 5305 1989

R., (o) 2391.9 2712 18846“, (pF) 4.5288 5.460 2.098

~ (kQ) 1,5.363U (pmho) 229.774 188.6 .502.765Gc~ (nmho) 1.1516 6.28 5.028R,, (n) 76.8 32.13 ‘32.13Ro, (Q) 489.2 42.87 42.87G* (mho) 37.0978 247.49 92.792Ix (A) 100.138 —

1~~, (A) 3.8218.10-3’ ~ .10-16 8.10-16

Rc (Q) 0.1986 .10-3 0.02129 .10-3 0.00279 ~10-3Gc (mho) 5034.3 46964 358000Vc (v) 1.6042 1.803 2.803VE (v) 3.1042 2.303 2.803

‘7 ~o device-level model

. macro model

-5{l’I 1 I I I

Q 10 20 30 40

t Ipsec )

F ig. 4. S imula t ed volt a ge followe r s lew r a te p er forman ce u sin g bot h d evice-leve l mod els a nd macr omod els .

by the type of op amp under study or is chosen appro-

pr ia tely. For the case at hand, Cz = 30 pF.

Th e r em ain in g va lu es of t he pa ramet er s of t he m acr o-

model a re presented in Table IV, column 1.

IV. COMPARISON WITH DEVICE-I,EVEL iklODELS

Basic Macro model Perf orm tance

Th e valu es for t he m acr omodel of Table IV, colum n 1

wer e u sed t o define an ext er nal model in pr ogr am SPICE .

The same set of computer runs was made as lead to the

op a mp per for ma nce r esult s of Table III, colum n 1. The

r esu lts for t he macr omodel ar e pr esen ted in colu mn 2 of

t his t able. It is seen t hat th e compar ison is excellen t for

bot h sma ll-s ign a l a nd la r ge-s ign a l exper imen t s.

To pr ovide a fu rt her compa ris on , t he la rge-sign al, sle

r at e per for man ce for a voltage follower is sh own Fig.

for bot h t he device-level m odel a nd t he m acr or nodel. I

is seen that the responses are very similar.

The presence of C@ p roduces a step in the init ial response of the voltage follower . From simple theory [4]

t he jump sh ou ld be a ppr oxim at ely

For t h is example,

AVin = 10V and AVOU,= ~ (10) = 2.5V.

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361OYLEetal.: MACROMODELINGOFoPERATIONALmplifierS

20k

.:*W———ig. 5. A m on ost able t im e dela y cir cu it .

From Fig. 4, the observed jump for the macromodel is

3.6 and 3.4 V for t h e d evice-le vel model.

A m ea su re of t he com plexit y of t he t wo op amp models

can be obtained by compar ing the node and branch

cou nt s of ea ch cir cu it . F or t he device-level model, wh er e

each G–P t ransistor model has 2 internal nodes and 7

branches, the tota ls are 81 nodes including the da tum

node, a nd 193 br an ch es . F or t he m acr omodel, wh er e ea ch

E-M transistor model has no in ternal nodes and 4

branches, the tota ls are 16 nodes and 28 branches. The

ra t ios for the two models are 5.1 for the nodes and 6.9

for the branches. The number of p-n junct ions in the

device-level m odel is 52 a nd 8 in t he m acr om odel, a r at io

of 6.5.

The tota l computer cent ra l processing unit (CPU)

t ime on a CDC 6400 to simulate the voltage follower

slew r at e per formance is 39.2 s for t he device-level mod el

a nd 4.0 s for t he m acr omodel, a r at io of 9.8. An a lt er na te

com pa rison is obt ain ed if on ly t he sim ula tion t im es for

t he in it ia l st at e a nd t he t ra nsien t a na lyses a re u sed. Th e

impr ovemen t r at io is t hen 12.0.

F or t he dc a nd a c sim ula tion s, t he device-level m odel

t o ma cr omodel CPU tim es, for t he a na lyses on ly, ha ve

t he r at ios of 3.9 a nd 6.0, r espect ively. Note th at t he im-

pr ovemen t r at io is less for th e dc a na lyses.

A R egenerat iv e T imer

Th e mon ost able t ime dela y cir cuit of Fig. 5 pr ovides

a good t est of t he a bility of t he ma cr omodel to per for m

a s d esir ed wh en deman din g n on lin ea r per formance is r e-

quired. The voltage a nd t iming levels of the circuit ofFig, 5 ha ve been ch osen t o provide a maximum stress on

the op amps with respect to voltage limits, cr it ica l volt-

age switching levels and speed of response, slew-ratelim ita t ions, etc. The output waveforms of the circu it as

pr edict ed by pr ogra m SP ICE u sing both t he device-level

model and the macromodel are shown in Fig. 6. It is

seen t hat t he r esponses com par e closely. The leadin g and

tra iling edges of the ou tpu t pulse differ in t iming by less

than 1 time step of the computer outpu t , i.e., bet t er than

3 percen t of the overa ll pulsewidth. The tota l CPU times

for the simulat ions using the two models a re in the ra t io

of 8.9. If the common outpu t t ime is deleted, the im-

pr ovem en t r at io is 9.6.

Vou! (

15–

[

lo- ),

v)

5- (h

o- , ,,

-5- P

k

-lo– <1$

. device-level model

o mocro model‘h.

-15+ I I [o 20 40 60

t ( , u sec )

F ig. 6. Sim ula ted ou tpu t pu lse r espon se of t im e dela y cir cu it

us ing both dev ice -level model s and macromodels.

100k 100k

399k

10k 10k 10k

v:

— — . T

F ig, 7, “Ring of Thre e” bandpas s filt er .

TABLE V

l?.ESPONSE DATA FOR THE , ’[RING OF THREE” BANDPASS FILTI;R

Design Actual Gain Gain GainCenter Cen ter Ma gn it ude Ma gn it ude Ma gn it udeFrequency Frequency at a t

f., (kHz) f.a (kHz) ~R o.~f.d l.lf,a

1 0.998 11.01 4.806 4.311

(O.998) (11.00) (4.806) (4.311)

2 1.996 12.24 4.898 4.368

(1.996) (12.23) (4.896) (4.367)

10 9.’934 112.1 5,547 4.398

(9.934) (107.1) (5.542) (4,401)

Numbers inparenthesesefero resultsithdevice-levelodel.

An Active R C Filter

To fur th er check t he secon d-or der a c r espon se of th e

macromodel, the simple “Ring of Three” op amp filter

of Fig. 7 was designed for a center frequency of 1 kHz

and a ~ of 10. The frequency response from program

SPICE for the two models is summarized in Table V.

Again, itis seen that the comparison isvery close.

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362 IEEE JOURNALOF SOLID-ST.4TECIRCUITS,DECEMBER19

At higher fr equencies, the phase response of the (1 expr essions of Ta ble I. Th e fin al r esu lt s a rc pr esen te

lllH z) 741-t ype op amps com es in to effect . A r espon se in column 1, Ta ble IV.

compar ison for the two models as shown in rows 2 and From the slew rate performance of the 8741 a s give

3 indica tes that the macromodel is providing the proper in Table III

phase response.

The tota l CPU simulat ion t imes to determ ine the dcs,+ = 0.90 V/ps and SIZ- = 0.72 V/ps.

state a nd t he fr equ en cy r espon se u sin g t he two m odels For the given compensa t ion capacitor of Cz = 30 p

have the rat io of 5.8. If the common output t ime is these values lead to

om it ted, t he r at io becomes 6.8.In t his a pplica tion, th e n on linea r per for ma nce of th e ICI = ;SE+C, = 13.50 PA

op amp is not of major in terest . In order to check on

the improvement of computer run t ime for a reduced C, = ~? – C, = 7..5OPF.

m acr om odel, t he volt age a nd cu rr en t lim it in g cir cu it ry..

Th e a ver age ba se cu rr en t is 256 nA a nd th e desir ed baof Fig. 1 was omit ted. The simulated response of the

filter did n ot ch an ge, of cou rse; h owever , t he t ota l CPUcu r rent offs et is 0 .7 nA.

run t ime was reduced by a factor of 1.4. I,, = 256.3 nA, IB , = 255 .7 nA

l’.MACROMODICL PARAMETERS FOR OTHER IC OP AMPS /3,= 52.6727, /32= 52.7962.

Th e det ailed, p recis e p er forman ce ch ar a ct er ist ics for

an individual op amp as obta ined from the use of the

device-level m odels a re u su ally n@ a va ila ble. Th e pr e-

cision used in the numerical example of th is paper is

employed in or der t o obt ain a n a ccu ra te est im at e of t he

per formance of a macromoclel in rela t ion to a known

reference. Exper imental r esu lt s with actual op a mps

cou ld inclucle s ign ifican t measuremen t inaccu racie s,

Typically, one has a da ta sheet or averagecl exper i-

menta l data for a type of op amp which is to be in-

cluded in a system. As an example of the choice of

ma cromodel pa ra meters in th is situat ion , two fur ther

examples a re given . In Ta ble III, colu mn s 3 a nd 4, mea -

su red t ypica l op amp da ta a re given for bot h t he LM741

and the LMl 18. The macromodel parameters corre-

sponding to these data are given in columns 2 and 3 of

Ta ble IV.

It is possible to in t roduce programming into a simu-

la tor t o det ermin e a ut om at ica lly t he m acr omodel pa r am -

eters. This has been done at one locat ion for program

SPICE.In th is situa tion , all tha t is necessary to define a

specific op amp model is to list its ch ar act er ist ics on a n

op amp “model card’) in much the same way tha t one

~urren t ly defines a t ra nsistor model by specifying it s

ch ar act er ist ics on a t ra nsist or model ca rd. Wh en a n op

amp ch ar act er ist ic is n ot in pu ted, a defa ult va lu e is u sed.

A high level of pr ecision is u sed in t his example in or d

to obta in an accur ate compar ison of macr omoclel pe

formance in rela t ion to that of the op amp modeled

the device leve l.

The necessa ry emit ter curren t source for the inp

stage is ~~fl = 27.512 PA. The value of the CM emit t

r es is tor is

R, = 200/ I BB = 7.2696 Ma

where a value of VA = 200 V ha s been used.

For ~1, the assumed value of satura t ion current

8”10-’6A which is a typicalvalue for a small n-p-n I

transistor.o proclucethe desiredinput offsetvoltag,

0.299 mV

IS2=8’0-1’(10) =80’2510-16For a fully compensa ted op amp with a rolloff of –

dB/octa ve, the O dB frequency can be calcu la ted fro

the product of the gain and the value of the frequenc

at which it is mea sur ed providing that the frequency

well a bove t he cor ner fr equ en cy of th e ga in ch ar acter

ist ic. From the da ta of column 1, Table III,

f, dB = (1.219” 103)(103 ) Hz = 1.219 .106 MHz.

Th e va lu e of t he collect or r esist or s of t he fir st st age is

APPENDIX R., = ——1-— = 4352 Q.2~f0dBc2

THE 8741 MACROMODEL The value of the reciprocalof g.,forthe firststage is

In t his Appen dix, a n um er ica l example is u sed t o illu s-

tr ate the development of the pa rameters of the op a mp1

— = 1915 Q.

m acr oln odel. F or t he examp le, t he r es pon se ch ar act er is -9m1

tics of the 8741 op amp are used as determined by sev- The required value of the emit ter resistor is

er al sim ula tor r un s u sin g device-level modelin g. Th e cir -R ., = 0.9814(4352 – 1915) = 2392 Q.

cu it ’ of F ig. 2 t oget her wit h t he t ra nsist or pa ramet er s of

Ta ble I I h as been a na lyzed t o obt ain t he ch ar act er ist ics The final element for the input stage is (71, w hich pro

whicb a re summar ized in column 1, Table III . duces the nondominant pole of the gain funct ion . Fo

Th e developmen t pr ocedur e follows t he sequ en ce of A+ = 16,80°

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BOYLEet d.:MACROMODELINGOF OPERATIONALMPLIFIERS

C, = ~ tan 16,80° = 4.529 pF,

Th e va lu e of t he r esist or RP to s imu la t e power d is sip a -

t ion for *15 V supplies a nd a dissipa t ion of 59.4 mW is

R. = 15,363 kQ,

F or t he in ter st age, Rz is t aken to be 100 k~ and

~a = #- = 229.7 74 /Jld10 .

For a CMRR of 106 ~~ (199.5” 10S)

GG.

CM = CIV!RR= 1.1516 nmh o.

In the ou tpu t st age, the desired dc and ac ou tpu t re-

sist an ces a re 566 ~ a nd 76.8 0, r espect ively. Th er efor e,

R o, = 76.8 Q, R OZ= 489.2 Q.

The value of Go to pr ovide the correct DM voltage gain

of 417. 10s is

aV~R.l

‘b = KR;; = 37 “097”

The maximum cur ren t th rough the diode DI or

Ix = 21ClGbR, – I.c = 100.14A

where the desired value of I~ c is 25.9 mA. Wit h

va lues, the sa tu ra t ion cur rent s of DI a nd D2 are

I SD = Ix exp – ‘~~’z = 3.822.10$’2 A.T

The va lu es for t h e app roxima te volt a ge -con t rolled

a ge sou rce a re

Dz is

these

volt-

l’ort h e volt a ge -clamp cir cu it s, t h e s at u ra t ion cu r re nt s

of diodes D3 and D4 are chosen to be 8.10-16 A. The

volt a ge s ou r ce s s hou ld b e

Vc = 15 – 14.2 + 0.02585 in ~$~~% = 1.604 V

and

V. = 15 – 12.7 + 0.804 = 3.104 V.

AGIciNOWT~E~~~~~~

The au thors are pleased to acknowledge the a id a nd

discussion on th is topic with C. Bat t j es, R. Bohlman ,

S. Taylor , R. Dut ton , and I. Getr eu .

Th e st affs a t t he Com pu ter Cen ter s a t t he Univer sity

of Ca lifor nia j Ber keley, a nd a t Tek tr on ix, I nc., Bea ver -

t on , Or eg., h ave been ext rem ely gen er ou s a nd h elpfu l in

363

the suppor t given for the numerous computer runs neces-

sa ry for t his p roject .

REFERENCES

[11 J . R. Gr een ba um , ‘[Di~ it a l-IC model s for comnute r -a ided

[21

[31

[41

[51

[61

[71

[81

[91

design,” Electronics, vol~ 46, 25, pp . 121-125 ,Dec.’6 , 1973.B. M. Coh n, D. O. P eder son , and J . E , Solomon , “Ma cr o-model ing of oper a t ion a l amplifie rs ,” in ISSCC Dig, Tech.

F’apem, Feb. 1974,pp. 42-43.

D. 0. Pederson and J . E , Solomon , “The need and use ofmacromodels in 1 (3 s ub sys tem des ign ,” in F%oc. 1974 IEEE

Sqmp. Circuits and Systems, p, 488.

J . E . Solom on , “Th e m on olit hic op a mp: a t ut or ia l st udy,”IEEE J. Solid-state Circuits, t h is i ssue, pp . .314-332 .P. R. Gray and R, G. Meyer , “Recen t advances in mono-

l ith ic opera t ional amplifier design,” IEEE Trans. Circuits anti

S~st., vol . CAS-21, pp. 317-327, May 1974,B. A. Woolcy, S.-Y. J . Won g, a nd D. O. P eder son , “A com -pu te r-a id ed eva lu a t ion of t h e 741 ampl ifie r,” IEEE J. SolicZ-

State Circuits, vol. SC-6 , pp. 357-366 , Dec. 1971 .I ,YW. Nagel a n d D. O. P ed cr son , “S imula t ion p rogr am wit hi nt egr a t ed ci rcu it empha sis (SPICE) , “ 131cct ron . Res. La b.,

Univ. of California, Berkeley, Memo ERL-M382, and in

Proc. 16th Midwest &mp. Circuit Theory, 1973.

D. N. P ocock a nd M. G. Kr ebs, ‘{Termin al m odelin g a ndphotocornpensat ion of complex microcircui ts ,” IEEE Trans.

Nucl . Sci ., vol . NS-19, p p. 86-93, Dec. 1972.D. H. Tleleaven and F . N . T rofimenkoff, “Model ing o~er a -

t iona l ampli fi er s for computer -a ided ci rcu i t ana lysi s? IEEE

Trans. Circuit Theor~ (Cor r cs p.), vol . CT -18, pp. 205 -207,J a n . 1971.

G ra eme R. Boyle was born in Echuca, Vic-

t or ia , Au st ra lia , on Oct ober 26, 1949. H er e ce iv ed t h e B .E , a nd M .Eng.Sc. d egr e es ine le ct r ica l e ngin ee ri ng fr om the Un ive rs it yof Melbou rn e, Melbou rn e, Au st ra lia , in

1972 and 1974, re spect ive ly .H e is cu r ren t ly a t t h e Univer sit y of Ca li-

forn ia , Berke ley, work ing toward the Ph .D .

degr ee in t he field of m odelin g a nd com -pu te r s imu la t ion of in t egr a t ed cir cu it s.

Ba r ry M. Cohn (S’68) was bor n in S ea t tle,Wa sh ., on Apr il 8, 1949. H e r eceived t heB.S .E .E . d egr ee, gr adu at in g Ma gn a CumLa ud e a nd wit h College H on or s, fr om t he

Un iv er s it y of Wash ingt on , Sea t t le , in 1971.H e r eceived t he M.S . d egr ee in elect rica len gin eer in g fr om t h e Ca lifor n ia I ns tit u teof Tech n ology, P as ad en a, in 1972.He has done power engineer ing for

Sea tt le Cit y Ligh t d ur in g t he summer s of

1968–1970. “F rom 1972-1974 , whi le a t t h eUn ive rs it y of Califor n ia , B erk ele y, h e d id r es ea r ch and pub lis hedon t h e t op ic of macromodeli rr g in t eg ra t ed cir cu it s for comput er -a ided design . Du rin g t he summer of 1973, h e wa s em ployed a s

a n Engin ee r w it h Na tion a l Semiconduct or Corpor a t ion , wher e h ed id r es ea r ch on t h e t op ic of ma cr omod elin g op er a tion a l amp li-fier s. F rom 1973-1974 h e h as been a Resea rch Assist an t a t t heE lect ron ic Resea rch La b a nd a Tea ch in g Assist an t a t t he U ni-versity of California, Berkeley, from which he is currently on

leave and presently employed by Intel Corporation, Santa Clara,

Calif., w here h e d irects CAD op erations.

Mr. Cohn is a member of Tau Beta Pi and Phi Eta Sigma. He

is the recipient of a National Science Foundation Trainceship, a

General Telephone Electronics Grad uate Fellow ship, and nu mer-

ous undergr aduat e s chola rsh ip s.

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364 IEEE JOURNALOF SOLID-STATEIRCUITS,OL.SC-9,O.6,DECEMBER197

Don ald O. Pederson (S’49-A’51-M’56-F’64)

was born in H allock, Minn., on Septem ber

30, 1925. He received the B.S. d egree from

North Dakota Agricultural College (now

North Dakota State University), Fargo, in

1948 and the M .S. and Ph.D. degrees from

Stanford University, Stanford , Calif., in

1949 a nd 1951, r espect iv ely .

From 1951 to 1953 he was a Research

Associate in the Electronics Research Lab-

oratory, Stanford University. From 1953 to

1955 h e wor ked a t Bell Teleph on e La bor at or ies, In c., Mu rr zyHill, NJ ., a nd wa s a lso a Lect ur er a t N ewa rk College of E ngi-neer ing, Newark , N.J . In 1955he joined the E lect r ica l Engineer ingDepar tmen t , Un iver s it y of Cali forn ia , Berke ley, where is is now a

P rofe ss or an d engaged in r es ea r ch in in t egr a t ed cir cu it s an d com -

A High-Performance

put er -a id ed cir cu it an alys is an d d es ign . F r om 1960 t o 1964h e wasD ir ect or of t h e E le ct r on ics Res ea r ch Labor a t or y.

Dr . P eder son is a mem ber of Sigm a Xi a nd E ta Ka ppa Nu . H e

and t hr ee coa uthor s wer e a war ded a Best Pa per Awa rd for a

p ape r p res en te d a t t h e 1963 I nt er na t ion al S olid -S ta t e Cir cu it sCon fer en ce. H e wa s a Gu ggen heim F ellow in 1964 a nd wa s t he

r ecipien t of t he IE EE E du ca tion Meda l in 1969. I n 1974 h e wa

e le ct ed t o t he Nat ion al Aca demy of E ngin eer in g.

James E. Solomon (S’57–M’61) , for a .photograph and b iog raphy

p le as e s ee p . 332 of t h is is su e.

Monolith ic Mult ip lier

Using Act ive Feedback

BARRIE GILBERT , SENIORMEMBER,IEEE

Absfrac f—Since it s concept ion in 1967, the l in eari zed t r an scon -

d uct a nce mult iplier (LTM) h as r a pidly ga in ed a cce pt a nce a s t he

preferred approach to the realization of monolithic analogmultipliers,

a nd it s s im plicit y h as commend ed it for u se in low -cos t m od ula r

d es ign s. Accu r a cie s of t h es e u n it s h ave b een lim it ed t o abou t 0.5 t o

t o 2 p er cent , a n d d rift a n d nois e p er formance h ave gene ra lly b een

worse than tha t possibl e u s ing the dominan t a l te rnat i ve t echn ique

of p uls e-wid th -h eigh t m od ula t ion , Th is p ape r s hows t ha t wh en

ca r efu l a t t en t ion is given t o a ll t h e sou r ce s of e r ror it is p os sible t o

a t ta in a five-fold im pr ovement in a ccu ra cy a nd cor r es pon din gr ed uct ion s in t h e d rift a n d nois e leve ls . Odd -or d er n on lin ea r it ie s

can b e r edu ced t o n egligib le magn it u de s b y t h e u se of a ct ive fe ed -

back , by sub st it u tin g t h e u su a l r es is tive -br id ge fe ed back p at h b y

an amplifie r i d en t ica l t o t h at u sed a s t h e in pu t s tage s.

I. INTRODUCTION

T

HE LINEARIZED t ra nscon du ct an ce mu lt iplier

(LTM) technique’ is now widely used in one or

another of it s several forms, the commonest of

wh ich ar e sh own in Fig. 1. Usin g idea l t ra nsist or s t hese

cir cu it s a re fu ndamen ta lly exa ct a nd in sen sit ive t o iso-

t herma l va ria tion s of t emper at ur e. Compa red t o a lt er na -

t ive mult iplica t ion techniques, the LTM core is ex-t remely sim ple a nd h as in tr in sica lly wide ba ndwidt h.

It is t he ba sis of m an y ot her ‘(fu nct ion al” cir cu it s, su ch

Manuscr ip t r e ce ived May 25, 1974; revised August 11, 1974.

Th is p ap er w as p resen ted at th e In tern ation al Solid -State Circu its

Co nfer en ce, Ph ilad elp hia., P a., Febr uar y, 1974.

The au t hor is w it h Ana log Devi ce s S em icondu ct or , Wilm in g-

ton , Mass. 01887 .

1 B. Gilber t ,, “A new wide-band amp li fi er t echn ique,” IEEE J.

So.M-Stute Circuits, vol . SC-3 , pp. 353 -365 , Dec. 1968.

&1 12 1, 14

(a) J,J4 =+J3

I,

l+%, 1, 14

(b) J 1~=J3J4

“ +X)w-c) (d)

F ig. 1. Ba sic LTM con figu ra t ion s. (a ) “Norma l” form. (b) ‘Tn -

ve rt ed ” form. (c) S pecific ver sion of t he n orma l form h avin glow bet a sens it ivit y. (d ) Common in ve rt ed form , which is con -

venien t but has h igh beta-sensit ivi ty.

as p re cis e two-qua dr a nt d ivid er s, rm s conver t er s, vect or

sum modu les, et c.

This pa per descr ibes a fou r-qu adr an t mult iplier de-

s ign ed t o m ak e fu ll u se of t he pot en tia l a ccu ra cy a ffor ded

by t his t ech niqu e u sin g cu rr en tly a va ila ble m on olit hic

processes. The basic er ror sources are reviewed, an d

method s p re sen t ed t o m in im ize t h eir effect s. A s ign ifica n t

improvement has resulted from the use of an act ive

feedba ck s ch eme wh ich la rgely elim in a tes t h e non lin ea r -

it ies in tr odu ced by t he in pu t amplifier s. Apa rt fr om t his,

t he r es ult in g d es ign is s im ila r t o mos t t ra ns con du ct an ce