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High-performancesymmetric-gate and CMOS-compatibleVt asymmetric-gate FinFET devices

Jakub Kedzierski, David M. Fried*, Edward J. Nowak', Thom as Kanarsky', Jed H. Rankin*, Hussein Hanafi, W. Natzle', Diane

Boydt, Ying Zhang , Ronnen A. Roy , J. Newbury, Chienfan Yu', Qingyun Yangt, P. Saun ders, Christa P . Willets*, A. Johnson*, S.

P. Cole', H. E. Young', N. Carpenter', D. Rakowski', Beth Ann Rainey', Peter E. Cottrell', Meikei Ieong, and H.-S. Philip W ong

IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, NY 10598,'IBM Microelectronics Sem iconductor Research and Development Center (SRDC ), Hopewell Junction, NY 12533,

'IBM Microelectronics Division, Essex Junction VT , 05452; e-mail: jakub@ us.ibm.com ; phone: 914-945-3 796

Abstract

Double-gate FinFET devices with asymmetric and symmetric

poly-silicon gates have been fabricated. Symmetric gate

devices show drain currents competitive with fully optimized

bulk silicon technologies. Asymm etric-gate devices show

IV,I-O.lV, with off-currents less than 100nA/um at Vgs=0.

Introduction

Double-Gate CMOS (DGCMOS)[ ] is a promisingarchitecture for MOSFETs with gate lengths below 40nm.Th e attainment of low extrinsic resistance and threshold

voltages suitable for high-speed logic has, however, remaineda significant obstacle to high-performance DGCMOS

structures. In this work, we demonstrate symm etric double

gate (SDG) fully depleted FinFETs[2,3] (Fig. 1) with low R,,,,

providing record double-gate NMOS and PMOS currents at

electrical channel lengths (Leff)of 30nm and fin thickness (T,,)

of 20nm . Furthermore, we demonstrate, for the first time,

asymmetric double gate (ADG)[4,5] self-aligned NMOS and

PM OS F inFE Ts with IV,I-0. lV , which provide off-current

centered for high-performance logic, of <100nA/um at Vgs=0.

Figure I : Schematic of the planar FinFET structure. Light(gray) regionsindicate the single crystal silicon mesa used for the tin and source/drain

pads, dark(red) regions indicate the polysilicon gate line and pad.

Device Fabrication

The S DG and A DC experiments were run in parallel; the SDG

process targeted high performance, the ADG process targeted

V, appropriate for CMOS logic. The SDG experiment beganwith SO1 wafers that had a 65nm thick Si layer topped by a

50nm oxide hard mask. The fin layer was defined usingoptical lithography and a hard mask trimming technique. The

gate stack consisted of a 1.6nm thermal gate oxynitride(T,,),

an undoped polysilicon gate, and an oxide hard mask. Fig. 2

shows S EM of a 60nm gate length device after gate etch. Fig.

3 shows a SEM/TEM of the gate stack. Extension regions

were implanted at a high tilt angle of 45 , with 4 differentwafer twists, see Table 2. Implants with twist vectors

perpendicular to the fin surface resulted in a smaller AL.

Following spacer formations, the sourceldrain regions of som e

of the SDG devices were expanded using selective silicon

epitaxy. Fig. 4 shows a LPI,=3Onm, <loo> directed device

before and after the selective Si epitaxy raised sourceldrain

(RSD) process.

The ADC experiment started with SO1 wafers having 120nm-

thick Si and 90nm-thick thermal oxide hard mask layers. The

fin was defined using a process similar to the one used for the

SDG devices. Due to process and design differences, the

resulting minimum ADC fin thickness was 40nm (Tsi). ADC

gate stack consisted of 2.2nm thermal gate oxide, a 75nm

undoped polysilicon gate, and an oxide hard mask. Fig. 5

shows cross section SE M of an A DC F inFET, the inset shows

gate doping profile, as simulated on T SUPR EMT M. Implantstilted at 30° done before and after the gate etch, were used to

dope the gate and extension regions, see Table 2 for implant

details. The thinner gate and taller fin in the ADC structure

were used to facilitate gate implant shadowing, resulting in an

N+ dope d gate on one side of the fin and a P + doped fin on the

opposite side.

Device Performance

In order to facilitate a fair comparison with single-gateMO SFET s, FinFET currents are normalized by the effectivedevice width (W) using W = 2x fin height H). Id-vg curve s of

AD C devices Leff=180nm and 2 pm are shown in Fig. 6. Thefin thickness (TSJ and fin height (H) for ADG devices was

40nm and 120nm respectively. NMOS ADC devices show

positive V,,, = 0.15V (Id=300nA W/L condition), with

IOff=84nA/pm t v,,=Ov, for Leff=180nm, with v d= l.5 v. The

subthreshold sw ing S) is 89mVldec and 70 mV1dec for Leffof

180nm and 2pm respectively. PMOS AD C devices show

V,,,,= -O.lO V, with Lff= lnA /pm at V,,=OV, for Leff= 180n m,with vd=1.5v. S is 69mV/dec and 67 mV1dec for Leff of

180nm and 2pm respectively. The achievement of CMOS

compatible V, is a key component needed for the integration

of FinFETs into VLSI technology. The external parasiticresistance of the long fin extension region between the gateedge and the probe pad limited I,, in ADC devices; see

summary in Table 1.Id-vg and Id-Vd curves of SDG devices with Leff = 30nm,

Lply= 60nm are shown in Figs. 7 8 9. Fig. 7 shows Id-vg

characteristics of NMOS and PMOS devices without RSD.

Devices with T,, of lOnm and 20nm show linear swings of

75mV ldec and 90mV ldec respectively. Thinner fins show

lower I,, due to higher external resistance. Fig. 8 shows the

Id-Vg characteristics of devices with and without RSD.Reducing the devices external resistance with RSD increases

I,, without increasing I,ff. The RSD extension formation wasmodified to reduce boron diffusion and produce symmetric

PFET/NFET V,. Fig. 9 shows the Id-Vd characteristics ofdevices with and without RSD. To compensate for the low

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SDG V, the gate voltage range is shifted by OSV, but IV,ON-

V g 0 ~ ~ ls kept at 1S V . At VgOFF=( OSV) (+ for PMOS, - for

NMOS) and vdk 1S V , I,ff - 200nNpm, for both the NFET

and PFET. At IVg0~I=I.OL' nd Ivd kl. 5v , I,, is 129 6p Np m

for NFE T and 850pA/pm for PFET, in devices with RSD.This to our knowledge is the highest current reported for

NMOS and PMOS double-gate devices, and is competitivewith state-of-the-art bu lk silicon and SO1 technology[6,7].

Without RSD current levels are lower, with I,, o f 6 7 5 p N y m

for NFET and 370pNpm for PFET. Important deviceparameters for the SDG and ADG devices are summarized inTable 1. Fig. 10 shows the swing contours of 48 SD G NMOS

devices with 6 different fin thickness TSJ and 8 differentphysical gate lengths (Lpply). ue to the boundary con ditions at

the gates and the extensions, the extrapolated contours merge

at a point. As expe cted that point occurs at T,,=-~(E,,/E,,)T,,,

and a certain LpIy.Th is L,,, can be used to de fin e the AL, the

extension region overlap with the gates. A natural coordinate

system for short channel effects (SCE) of double gate devices

can be cons tructed by defining:

Lerr= LyoR- L Tef = T +2-E TE ,

Devices with a similar Leff/Teff ill have similar S CE providedthat ~(E,,/E,,)T,,<<T,,, and the junctions are abrupt. The Teff

relation ca n be obtained rigorously by ex panding the modified

scale length T,~~= ~ E,,/E,,)T,,T,,+T,~)~~8] to the second

order; the higher order corrections were small for devicespresented in this study. Figs. 11,12 show V I roll off and swing

characteristics of de vices with different T,, and L,I, in term s

of their Leff/Teff atio. In ord er to maintain A Vlc0.2V L eff/Teffmu st be larger than -1.3. T he transconductance (G,) of SD G

devices drawn in the <loo> and <110> directions is shown in

Fig. 13. In long channel NM OS devices G, is significantly

lower for fins drawn in the <110> direction, even though theelectrically measured differen ce in the To, is less than 10 . nshort channel devices the same trends persist with the <loo>

NFETs showing higher G,.

. 4 2 , 6 ,

Conclusion

We have demonstrated significant progress towards theultimate integration of FinFETs for ULSI CMOS. Firstly, the

SDG M OSF ET s in this work have demonstrated drive currents

rivaling the best reported for any device architecture,including conve ntional bulk, SOI, and double gate MO SFETs.Furthermore, these SDG devices also delivered excellent

double-gate CVA results of 0.92~s nd 1.36ps, for the nFET

and pFET respectively, and represent the first double gate

results competitive with state-of-the-art bulk or SO1

MO SFE Ts. Secon dly, we have produced the first asym metric

gate NMOS and PMOS FinFETs thereby achieving CMOS

com patib le VI with I,ff<lOOnA/um at V,,=O. Thirdly, we usedscalable lithography techniques to fabricate FinFETs with

LpIy=30 nm and Tsi=lOnm. Fourthly, we dem onstrated that thecombina tion of highly ang led extension implants and selective

Si epitaxy can be used to fabrica te devices with low parasitic

series resistance. The se results significantly adva nce the state-of-the-art for FinFETs as a technology that enables the

advanc emen t of CM OS to the end of the scaling era.

SDG extension implants, tilt of 45 .

only one of following per wafer:

Acknowledgement

The authors would like to ackno wledge the fabrication supportreceived from the facilities of the Semiconductor Researchand Development Center (SRDC), without which this work

would be impossible.References

[ ] H . 3 . P. Wong, et al., Pro c. IEEE Vol. 87(4), p. 537-569, 1999

[2] D.Hisamoto, et al., lEDM 1998 p. 1032- 1034, 1998[3] X. Huang, et al., IEDM 1999 p. 67-70, 1999

[4] S. Tang, et al., Proc. 200 0 IEEE Infer.SO/ Conf. p. 120-121, 2000[5] K. Kim, et al., IEEE Truns. Elec. Dev.. Vol. 48(2), p. 294, 2001[6] S Tyagi. et al., IEDM 2000 p. 567-570.2000[7] I. Y. Yang, et al., IEDM 1999 p. 431-434, 1999[8] K. Suzuki, et al.. IEEE Truns. Elec. Dev . Vol. 43(7), p. 1166, 1996

DeviceSummarv I NFET I PFET I

+U.00 50

I ADG gate and extension implants, tilt of 30'. Both of the gate implants Iwere done for each w afer, but only one of extension implants per wafer.Prior to Gate Etch both) I After Gate Etch (only one)

1.00 I 0.25

Table 2: Extension and gate implant conditions. SDG Dose and energy is

given in relative units. Ra is the simulated 10% interstitial Siconcentration range after implant, measured normal to fin surface.

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Figure 2: Top Down SEM, of a < I I O > SDG FinFET device after gate andhardmask etch. Device measurements: Tsi = 15nm, Lpoly = 60nm.

~~~~~

Figure 3: Xsection of a <110> SDG FinFET perpendicular tocurrentflow. Measurements: Tsi = 20nm, Tox = 1.6nm, Tpoly=l50nm

W=130nm (2x Fin Height). Inset shows TEM of fin and gate oxide.

Figure 4: Top Down SEM, of <loo> SDG FinFET before and afterselective Si epitaxy. Device measurements: Tsi = 20nm. Lpoly = 30nm.

Figure 5: Xsection SEM of ADG NMOS FinFET perpendicular to currentflow. Tsi=40nm, Tox=2.2nm, Tpoly=l20nm, W=240nm (2x Fin Height).

Inset shows the simulated doping profile after extension implant.

1E-47

1E 5

1E-6h5

1E-7

1E-9

1E-10

- v .= 1.5v

v, = 0.1v. '.

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

vg V) vg V IFigure 6: Id-Vg plot of ADC FinFET devices. NMOS Vt=O.ISV, PMOSVt=O.IV. Ion is limited by high parasitic series resistance. Tsi= 40nm.Leff=l80nm and 2um.

Figure 7: Id-Vg plot for Leff=30nm Tsi=2Onm,and IOnm, SDG devices. N-

poly gate was used for NMOS. P-poly for PMOS. Devices shown in t h is

figure have no RSD, see Fig. 2.

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A. No Raised SourcelDrain (RSD)V, = 1.5V

+Selective Si EpitaxyRSD

-0.2-h

>- 0.3

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

vg V)Figure 8: Id-Vg plot for Leff=30nm Tsi=20nm, SDG evices with and withoutRSD. T he sourcd drain formation process was modified for devices with RSD

to reduce boron diffusion from the sourcdd rain areas into the body.

L physical (nm)

40 60 80 100 120 140 160

100

90

80

60 E5 .40 8

7 h

c

30 I

20

10

00 20 40 60 80 100 120

L effective (nm)

Figure I O : Swing contours for SDG NMOS devices, Vd=O.IV. Fin thicknessTsi, varies from 20nm to 82.5nm in steps of 12.S nm. physical gate length, L

poly varies from 70nm to 157.5nm in steps of 12.Snm. Contours areextrapolated with dotted lines to a common origin, at (Leff,Teff)=(O,O).

1607

. Qg

,os

1401 1000-

8 :

Y

0 400:

- 600-

4 0 1 . I I . I .

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Left 1 e

Figure 12: Swing of SDG NMOS devices in terms of Leff/Teff ratio. Tsivaries from 20nm to 90nm; Leff varies from 30nm to 120nm. Minimumswing for Vd=O. I V and 1S V s shown.

€ =

1400- . o Raised SourcelDrain (RSD).

2oo-

1000-

-Selective Si EpitaxyRSD

Vg teps of 0.25V

I(V*ON-Vt)I =d .35v

-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5

'd (1Figure 9: Id-Vd plot for short channel, Leff=30nm, Tsi=20nm,symmetric gate devices with and without raised sourcddrain (RSD).

N E T Vg v ar ie s from -0 SV t o 1 .OV in steps of 0.25V.

-0.1. O I . I

0J

0.5

0.0 0.5 1.0 1.5 2.0 2.5 3.0 21 22

Le 1TeffFigure 1: Vt of SDG NMOS devices in terms of Leff/Teff ratio. Tsivaries from 20nm to 90nm; Leff varies from 30nm to 120nm. Long

channel Vt is shown on the right.

14007NMOSGmSat

1200/ PMOSGmSat

2001V,=l .sv

Figure 13: Transconductance (Gm) of <loo> and < I IO> directed

tins. Long channel NMOS devices in <loo> have -SO% better Gm

than devices directed in < I I O > suggesting higher mobility.

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