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ASIC BIST Synthesis:A VHDL Approach

Tom Eberle ,Bob M cVay, Chris Meyers, Jason M oore

Sand ers, A Lockheed M artin CompanyAdvanced Engineering & Technology, DFT Technology Group

Nashua, NH 03061

AbstractThis paper describes the practical aspects of an automated

design process and tool environ ment developed to rapidly

and effectively include BIST into AS IC design s An

overview of the BIST architecture is given describin g

BIST capabilities for ASIC mission logic, emhedded and

external memory devices, and an interconnect BIST

capability used to assist modulePCB BIST. A high level

synthesis approach is employed using the VHDL languagein a way unique to its intended purpose. An automatic

means for instantiating VHDL BIST structures into an

ASIC design is described. Other automated phases of the

development cycle are discussed including testability

enhancement of the ASIC core and test stimulus

generation for foundry, factory, and field test. Results are

presented for 6 ASIC designs ranging in gate count from56k-164k gates (complexity from controllers to data

processors).

1. Introduction

The ability to provide high reliability, maintainability, and

availability for military and aerospace systems is ofparamou nt imp ortancc. Futurc m ilitary con tracts will

emphasize this point with a continued theme of reduced

systcm lifc cycle costs. Rome Labs C31 ‘95Technology[ 13

goals includc:

- Achieving an order of magnitude increase in mean time

between maintenance actions and a factor of four or

greater decrcase in support costs attributed to external test

cquipm ent, personnel, and training.

- Developing efficient diagnostic m ethodolog ies to reduce,

by 10 fold, the high levels of unnecessary maintenance

actions and to allow for on-equipm ent fault detection an disolation.

- Develop design tools and test methodologies to

incorporate reliability technology at the earliest stages of

system development.

A strategy employ ing robust integrated diagnostics with a

system wide test strategy, based on BIST (Built-In Self-

Test), is the only realistic means of obtaining the high

levels of reliability and maintainability set forth in these

aggressive goals. More challenging still, is creating adesign environment which enables designers to rapidly

and economically produce systems with such inherent

testability.

In order to reduce system life cycle costs, early planning

for testability is imperative. The virtues of test insertion

early in the system life cycle are well known and are

treated extensively in the literature. However, practical

mech anisms and p rocesses for achieving this goal are less

well known and understood. In particular, the process ofincluding Built-In Self-Test structures during the designprocess poses many challenges. Issues raised include howbest to augment your current design process to deal with a

specific BIST strategy for each level of a system

hierarchy, what tools (if any) can be employed to help

automate the process, and how automation can best be

employ ed to reduce the design cycle time.

This paper discusses the design process and tools

developed to rapidly and effectively include BIST into

ASIC designs. Emphasis is placed on the methodology

behind the BIST strategy, the tools used to synthesize the

BIST architecture, and the overall logic synthesis process

used to produce the gate level implementation of the

design. To date, 15ASIC de signs ranging in gate count

from 60k -170k gates (complexity from controllers to data

processors) have successfully completed this process. A

full set of metrics have been compiled for 6 ASIC designs

and is presented in the results section.

2. Approach

Sanders has developed a design capability which

facilitates the automatic (or highly automated) insertion of

test logic into ASIC designs. This capability can be

broken down into three key elements: ASIC BIST

INTERNATIONAL TEST CONFERENCE

0 - 7 8 0 3 -3 5 4 0 - 6 1 9 6 $ 5 . 0 0 Q 1 9 9 6 IEEE

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architecture, ASIC BIST process, and ASIC BIST tools.Each will be explored in the following paragraphs.

2.1 ASIC BIST Architecture

There are several important factors which led to the

selection of our BIST architecture. These include:

0 High fault detection requirements (>98% of permanent,

0 Minimum test duration times ( 4 0mS for core BIST)

0 Module BIT (hardware/software) support from ASIC

BIST (hardware) to manage as many module BIT

functions as possible. (RAMBIST, interconnect BIST)

Deterministic testability enhancem ent technique to

reduce design cycle time through m inimized design

iterations

the amount of DFT knowledge required by an ASIC

Designer

Compiler, other 3rd party proprietary tools.

single, stuck-at-0 and stuck-at-1)

Design automation approach which significantly reduces

0 D I T Tool availability and capability (Synopsys Test

The resulting architecture includes several BIST functionsfor detecting faults within the ASIC as well as external to

the ASIC. These BIST functions are ASIC CORE BIST,

Memory BIST, and Module Interconnect BIST. Individual

1149.1 instructions initiate these BIST tests with a single

test interrupt pin signaling test completion. The IEEE

1149.1 test bus is used as the interface for boundary scan

testing (mostly fault isolation) and for initiating BIST

tests and retrieving BIST results. A user defined register

interface is available for designs requiring access to

functional circuitry (e.g. calibration data) via the 1149.1

interface.

2.1.1 Core BIST

The “Core” design consists of the application hardware

excluding I/Q and test structures. Figure 1 shows the full

scan BIST architecture (a.k.a. STUMPS) [2] for the ASIC

Core. Key elements of the BIST architecture include the

multiple scan chains formed by stitching scan flip-flops

into scan chains, PRPG (Pseudo Random Pattern

Generator), and MISR (Multiple Input Signature Register)elements. Testability enhancement is performed on the

ASIC Core design to increase the pseudo random

testability of the application hardware. Once the ASIC

Core design has been synthesized into gates, test points(control and observation) [7] are added to the ASIC Core

design followed by scan insertion. Treatment of BIST at

this level of the design is the only non-VHDL aspect of

the ASIC BIST approach; unavoidable since it requires a

scannable (synthesized) core. The number of scan chains

and their length are constrained so as to 1) reduce the

overall test duration time and 2) reduce gate level

simulation time.

Primary

Inputs

I PSeudO Random Pattern Generator (PRPG) I

Primary

outputs

I Multiple Input Signature Register (MISR) I

Figure 1. Scan BIST Architecture

The PRPG is based on a maximum cycle length one-dimensional linear cellular automata (CA) structure [ 5 ] .

The CA structure was selected due to its ability to avoid

bit correlation commonly exhibited by shift register

sequences. The pattern generator is always sized so that a

single stage of PRPG drives a single scan chain in the

ASIC Scancore (e.g. 70 scan chains require a 70-bit CA).

The intent is to decrease structural dependencies due to

multiple chains sharing a common pattern generator

stage.

The data compression of scan chain test results is

accomplished with the MISR structure 121. As with thepattern generator, the signature register is also sized sothat a single stage of the MISR is driven by a single scan

chain of the ASIC Scancore.

2.1.2 Memory BIST

Test structures within the ASIC provide BIST capabilities

for embedded memories (ASIC level) and/or external

memory structures connected to the ASIC (module/PCB

level). Memories are classified into two groups, SRAM

an d FIFO. SRAM’s are further classified as embedded or

external memory as shown in Figure 2. FWQ’s are always

considered external memories. The concept of an “abstract

memory” is introduced as any physical grouping of one ormore “like” memories, meaning a common interface and

common memory depth (widths are allowed to vary).Abstract memories are viewed by the memory BIST

circuitry as a single memory device. For example, two

independent memory arrays (embedded or external),

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during normal system mode, can be combined into a

single abstract memory during memory BIST. This

presumes they both have a common address space and

that their control interface functions the same.

All SRAMmemory (embed ded and external) can be tested

by executing the single 1149.1 instruction “RAMBIS’I”’.

This instruction cycles through each SRAM BIST to

provide a single test mechanism . For diagnostic purposes,a single memory device (or an abstract memory) can be

tested individually by setting a memory ID register and

executing the 1 149.1 instruction “ABSMEM BIST”. Dual

port SR AM ’s are tested by applyin g the same mem ory test

algorithm successively to each memory port. FIFO’s are

tested individually using the ABSMEMBIST instruction

with two se parate memory ID ’S specified for each FIFO .

One ID specifies that the FIFO be filled the other ID

specifies that the FIFO be emptied. Each memory BIST

results in a test interrupt signal indicating the test has

completed. Health status and diagnostic data are

generated and can be retrieved through the 1149.1 test

bus. Off-chip verification is necessary to determine correctoperation.

T h e selection of mem ory BIST alg orithms con sidered the

relative size of ASIC embedded SRAM, compared with

external SRAM , and the tim e necessary to test each class

of memory. Because memory is typically smaller within

an ASIC, a longer more robust test can be afforded. The

SMARCH (Serial MAR CH) algorithm [6] is employed for

all ASIC embedded SRAM. External SRAMs, which are

significantly larger, are less rigorously tested to meet test

duration constraints. The MATS (Modified Algorithmic

Test S equence) algorithm [SI is employed for all external

SRAM.

The memory BIST architecture is partitioned into two test

structures. The first structure is the Test Memory Interface

(“MI) which functions as the memory BIST controller,

implementing all memory test algorithms, 1149.1

instruction decoding and diagnostic register storage. The

second structure is the Physical Memory Interface (PMI)

which provides address/data/control multiplexing, local

results checking, and local readwrite control. Each

abstract memory requires one PMI.

Embedded SRAM Testing. A serial data interface

scheme is employed by the SMARCH algorithm for

testing embedded memories [ 6 ] . This approach was

chosen due to its reduced data path interface (two signals

only) and rigorous test algorithm. An l l n (n=total

number of bits in abstract memory group) serial data path

march algo rithm is implemented in the TM I (Test

Memory Interface) structure.

External SRAM Testing. A parallel data interface

scheme is employed by the MATS algorithm [8] for

testing external m emories. This approach was chosen dueto its simple implementation and minimal test duration

time. A 5n (where n=total number of words in an abstract

memory group) parallel data path readwrite algorithm is

implem ented in the TM I structure.

FIFO Testing. A parallel data interface scheme is

employed for testing external FIFO devices. A separate

memory ID is defined for the FIFO write and FIFO read

functions. In this way, the read and write ports of the

FIFO are treated as unique memories. The writing ASIC

is commanded through the ABSMEMBIST instruction to

fill the FIFO with the test data specified (supports data fill

of all 1’s or all 0’s) and asserts the test interrupt signalupon completion. Flag status is monitored during the

filling of the writing ASIC, if su ch access is provided. An

1149.1 flag status register can be checked after writing to

ensure that all flags functioned correctly. Next, the

reading ASIC is commanded through the ABSM EMBIST

instruction to empty the FIFO and asserts the test interrupt

signal upon completion. During the emptying process the

read data is verified against the expected data and flags

are monitored to ensu re correct operation. Upon signaling

comp letion, an 1149.1 flag and data status registers can be

checked to verify correct FIFO operation.

2.1.3 Module Interconnect BISTmbeddedMemw

Figure 2. RAM BIST A rchitecture

Test structures within the ASIC provide a means of

detecting interconnection faults at the modulePCB level.

This capability is intended to be used w ith a single ASIC

instantiation or coordinated with multiple ASICs on a

single module. Faults detected for a single instantiation of

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an ASIC include (see Figure 3 . ) : ASIC pins shorted to

1/0, shorts between any one pin of an ASIC to any otherpin of the same ASIC and faults within drivedreceiver

elements. In addition, modules with m ore than o ne ASIC

instantiated can detect shorts between any one pin of an

ASIC to any other pin of a different ASIC, and any open

between one ASIC and another. Although this BIST does

a fine job in d etecting the faults mention ed, it provides

little information for isolating these faults.

Several requirements are necessary to support this

approach. These include:

All non-test YO are boundary scan nable

0 All boundary scanned cells are bi-directional

a All boundary scanned cells have a local output enable

0 All boundary scanned cells have a pull-up resistor

(independent of mission operation)

cell

located at the ASIC pin

During interconnect BIST several restrictions are

imposed. As mentioned, all ASIC pins which are

participating in the interconnect BIST are 1/0 regardless

of their mission function. This means that any other

device capable of driving the ASIC must be disabled by

some means. Exceptions include inputs which are hard

wired to a known logic 0 or 1 state (e.g. strap or mode

pin), and inputs which are indeterminate (e.g.

asynchronous clocks/strobes). Both of these exceptions

result in diminished fault detection with the former

accounting for the known steady state and the latter

masked all together. In addition, all ASIC pins enabling

drive-back devices are driven to their disabling values

MultipleASIC Ins ‘7~

0

D n ~ D n n ~ o i Y D D o .

c ,Fimre 3. Interconnect BIST Fault set

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during interconnect BIST (e.g. memory device output

enables).

Interconnect BIST employs two modes to accomplish

modu le self-test. These include:

Send Mode: Initiated by 1149.1 instruction “PBSEND”

(patternshroadcast send). The ASIC executing this

instruction is designated the source (or sender) of drivendata during BIST. In addition, this mode has the ability to

captureheceive it’s own driven data on each pin via the

bi-directional boundary scan cells. Faults detected

include:

1) pins shorted to 1/0

2) shorts between pins of the AS IC

3) faults within driverlreceiver elements

Each ASIC on a module is required to take its turn in

executing the PBSEN D instruction. Only on e ASIC can be

designated a “sender” at a time.

Receive Mode: Initiated by the 1149.1 instruction“PBRECEIVE’ (patterns broadcast receive). The ASIC

executing this instruction is designated the destination (or

receiver) of driven data during BIST. This mode has the

ability to captureheceive data on it’s pins through the

boundary scan register. Faults detected include:

1 ) open circuits between sending ASIC and receiving

ASIC2) shorts between any one pin of the receiving ASIC to

any other pin of the sending ASIC

A separate means (e.g. module BIST controller, 1149.1

master controller, etc.) is necessary to coordinate the

module interconnect BIST. Depending on the number ofASIC instantiations, a series of sub-tests are executed

comprising the module interconnect BIST. A sub-test is

defined as a single ASIC being designated a sender (only

one ASIC can be designated a sender per sub-test) while

the remaining ASICs are designated the receivers. It’s

mentioned that an analysis can be performed, based on

ASIC connectivity, to possibly eliminate some ASICs in

receive mode from one or more sub-tests. The total

number of sub-tests is equal to the total number of ASIC

instantiations for a given module (i.e. each ASIC takingits turn as a sender; round robin). If only a single ASIC

instantiation exists, then only one sub-test is performed

with the ASIC designated as a sender. At the completionof each sub-test, a test interrupt pin signals test

completion. Each ASIC contains a signature which is

verified off-chip by accessing the signature register

through the 1149.1 port. After all sub-tests are complete,

the module interconnect BIST is complete.

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The interconnect BIST scheme is based on Wagner’s [3]

log2(n+2) bridging fault test ge neration exam ple.

However, adaptations have been made to minimize

contention situations within a tri-state environment.

1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4

P reeharge 1 1 1 I 1 I 1 1 1 1 1 I( C Y C i S 1 )

0 1 0 1 0 1 0 1 0 1 0 1

Precharge

0 0 1 1o o i i

0 0 1 1

Precharge0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

t i 1 1 0 0 0 0

C a m p l a m e n t

L a s t P a t t e r n 1 1 1 1 1 1 1 1 0 0 0 0(cycle 10)

The interconnect BIST algorithm for the sending AS IC is

shown below.

3 2 1 0

1 I 1 1

0 1 0 1

0 0 1 1

1 1 1 1

0 0 0 0

1) precharge all I10

2a)shift Os through boundary scan da ta registers

2b) shift binary progression pattern through b oundary scan

enable registers

. € W O 1 2 3 4 5 6 7 8 9 1 0 1 1 ~ 2 1 3 1 4 1 5 1 6 1 7 . ul st cy de 1 0 1 0 1 0 i 0 1 0 1 0 1 0 1 0 1 02ndcycle 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

3dcycle: i 1 I I O 0 0 0 1 1 1 1 0 0 0 0 1 1

3) update boundary scan register

4) captures I/O (expect data =binary progression)

5) repeat steps 1-4 logp

6) invert last binary progression and go through loop

*Pattern set reduces to 2*(log,n) + 2, max

The interconnect BIST algorithm for the receiving ASIC

is the same employed by the sending ASIC. However, the

output enable for all I/O are globally disabled with the

exception of the precharge state. In addition, a common

value of “n”, fo r each module, must be selected where n is

larger than the number of boundary scannable U0 for any

given ASIC. In this way, the same steps, in a sub-test, are

being performed by both sending and receiving ASICs.

A key element of this approach is the ability for an U 0 pin

to be precharged. Precharging is defined as driving an 110pin, which has a resistive pull-up, to a logic 1 . An

assumption is made that the logic 1 value will persist

when the U 0 pin is disabled (assuming a fault free

circuit). This technique avoids contention which occurs

between two nodes if a short exists. Contention is avoided

since all U 0 pins are precharged to a logic 1 value then

selectively enabled (e.g. every other pin) to drive a logic 0.

If a short does exist between two I/O pins, the I/O pin

which is enabled to drive a logic 0 will “pull-down” the

shorted I/O pin.

An example of the modified Wagner algorithm

(w/precharge) for a 16 pin device is shown in Figure 4.Cycle 1 displays the initial precharge cycle of all 1/0pins

being driven to a logic 1. Cycles 2-9 display the binary

progression patterns with precharge cycles interleaved.The logic 1’s shown in the binary progression patternsrepresent a precharged resistive high value for the I/O pin.

Cycle 10 displays the last pattern complement used todetect the S-A-1 fault in the least significant I/Opin.

Figure 4.Pattern Algorithm Example, 16I/O pins

2.2 ASIC BIST Process

The overall ASIC “Chip Finishing” process is a 4 tage

activity interleaved with the logic synthesis process (seeFigure 5) . As will be explained, tasks other than strictlyBIST insertion (e.g. test logic verification, test vector

generation, etc.) which aid in finishing the chip design are

coor dinate d in this pro cess. The pu rpose of this process is

to provide a structured ASIC design flow that includes

BIST insertion (not just practices) which is consistent,

predictable, and repeatable. This process helps identify

DFTBIST-related problems early in the design cycle

through the form alism introduced by the Signal D efining

Entity (SDE). The SDE serves as the repository of unique

test specific characteristics. Creation of the SDE requires

designers to consider the test related aspect of their design

in a structured, comp rehensive manner. In addition,

because the BIST architecture is embedded within VHDL

templates, the amou nt of DF T knowledge required of each

ASIC designer is reduced. Finally, the ASIC BIST

process provides a single point of contact to address

chipkystem-level test issues.

The ASIC BIST process begins with the ASIC designer

having completed initiai VHDL coding, RTL simulation,

and logic synthesis of the ASIC core. At this point the

ASIC chip finishing process begins. In stage 1 an SDE

(Signal Defining Entity) is created by the designer to

identify unique test specific characteristics. The SDE is

the ASIC core VHDL entity decorated with attributes and

constants describing design specific information. TheSDE and I/O pin map files are processe d by the Automatic

ASIC BIST Insertion tool (Chip Assembly); resulting in

the creation of VHDL entities, architectures,configurations, and pa ckages. These VHDL files describe

the ASIC top level hierarchy and test structures

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surrounding the ASIC core: such as the boundary scan

register, 1149.1 interface and TAP controller, RAMBIST

controller, interconnect BIST controller, I/ 0 ring and

drivers, and clock block. In addition, an ASIC-specific

test bench and parameter file is generated for later use

during the test stimulus generation phase.

Upon completion of Chip A ssembly, logic synthesis of the

ASIC Scancore segment is performed. The ASICScancore consists of the ASIC Core, Core U 0 isolation

logic used during Core BIST, and memory BIST logic if

memory structures exists. Thc ASIC Scancore is the level

of the design which scan BIST is applied and is ultimately

tested during C ore BIST.

Stagc 2 in the process involves testability enhalicemerit of

the ASIC Scancore. Test point identification and scan

insertion is performed on the ASIC Scancore hierarchy.

Signature calculation for the core BIST test and final fault

analysis are also accomplished during this step.

Logic synthesis of the remaining top level test functions( I D , boundary scan registcr, TAP interface, core BIST

controller, etc.) is performed next. At the comp letion of

this step the entire ASIC design is syn thesized to the gate

level and the designer can begin functional gate levelsimulations of the application logic.

Stage 3 in this process involves verifying correct assembly

of the test logic and creating all test stimulus required for

gate level simulation of the test logic. The concept of a

“scannable ASIC core” represented in behavioral VHDL

Signal Defining

Entity

has been developed [4] o verify scan BIST structures and

create test stimulus. This “stand-in” for the ASIC

Scancore allows Core BIST and ATPG simulation to be

accomplished at the behavioral level. This works by

leveraging the known good response data created during

the fault simulation analysis of stage 2. This data is used

to construct a pseudo Scancore VHDL architecture that

behaves in the exact same manner as would a fully

synthesized gate level description of the Scancore(containing scan chains) performing Core BIST. This

method results in a significant reduction in simulation

time over gate level simulation due to the elimination of

the “scanning” function necessary to fill a scan chain with

vector data. Exercising other areas of the test logic is

performed using this behavioral model as well.

The final stage of the chip finishing process involves

formatting test vector data to be used during foundry test.

The ASIC designer is required to perform all gate level

simulations as required by the silicon vendor for sign-off.

Stimulus extracted from the behavioral simulation of test

functions, as mentioned above, are used to drive the gatelevel simulations. The results of the gate level simulations

are converted to the silicon vendor’s test format and are

used for foundry test.

The current design process requires the silicon vendor to

provide a path for converting the simulation results database into their own test vector format. To date, the current

process supports Texas Instruments TDL generation

format.

ASIC Specific Signature C alculation,Test BanCh Fault Coverage,ESDL

LI(

e

Pin Map

Codes VHDL Core Function.Core VHDL Simulation* Synthesizes Core Function

-Te st Logic *Tes t LogicSynthesis Synthesis(SCANCORE) WO, BSREG,

ASIC-TEST,etc.)

VendorLayout

4Gate Level Simulation Gate L w ei Simulation

(application logic) (test logic)

Figure 5 . ASIC Chip Finishing Process

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2.3 ASIC BIST Tools

software elements. These include:

The A SIC BIS T insertion tool suite is comprised of three Primary inputs to this the SD E and pin map

files which provide the names of the ASIC pins at the

module level. Primary outputs include all VH DL entities,

architectures, configurations, packages, ASIC specific

parameter file, and M akefiles. This ou tput contains all the

information necessary to describe the ASIC specific BIST

architecture.

build-chip: pe rf om s Chip-Assembly

TEA SIT: Testability Enhanc ement (Testability

auto-test; Test Structure Verification and Test Stim ulus

Enhance ment And S can Insertion Tool)

2.3.2 TEASITeneration

Each of these tools have been developed in house.

How ever, elements of the TEA SIT tool suite use the

Synopsys Test Com piler tool to perform the sca n insertion

function and the S ynopsys Design Compiler tool to

perform the test point insertion function. In addition, scan

design rule che cking, test point identification, and fault

simulation are accom plished with a third party tool set.

2.3.1 Build Chip

The objective of the first tool is to process an ASIC

specific Signal Defining Entity a nd au tomatically producea com pletely assembled, testable ASIC design described in

VHDL.

A novel approach to high level synthesis, known as

“Property-D irected Tem plate Expansion”, h as been

employed to create a chip assembly tool. Property directed

template expa nsion involves three elem ents to successfully

build an ASIC-specific BIST structure. “Properties” are

declared as constants and attributes at the end of the

design’s ASIC Core entity. These properties describeunique features of each ASIC design. These include:

clocking0 special YO equirements

0 embe dded and external memory

RAMBIST

0 1149.1 user instructions and registers

part information

multi-function arrays (multiple functions in a single

package)

“Tem plates” describe the A SIC B IST architecture

symbolically. Templates are VHDL descriptions of the

ASIC BIST architecture that depict both structural and

functional aspects.

“Expansion” maps the symbolic templates to design-

specific VHDL. In a unique way, VHDL simulation

provides the mechanism for the mapping to occur. In

addition, a proprietary interface to a “C” library has

created through the abstraction of a VHDL synthesis

package.

The second tool in the ASIC BIST tool suite analyzes and

improves the pseudorandom testability of the ASIC

Scancore through test point and scan insertion. Final fault

analysis is performed for the core BIST test by using the

fault simulation tool to grade patterns applied to the

Scancore that were generated by em ulating the PRPG

function. In addition, the core BIS T known good

signature is calculated through MISR em ulation using the

expected known good scan data extracted during fault

simulation. ATPG patterns are created for the faults not

detected during core BIST.

Primary inputs to this tool include the ASIC Scancore

design database (gate level design containing the

functional ASIC core, several test structures, and

RA MB IST controller) and “dft-targets”. Th e dft-targets

are user constraints used to control testability

optimization. A brief description of user defined

dft-targets and their default values follow:

dft-final-coverage [99.99]: This variable is used to

control the stoppi ng criteria for the test point

identification step.

dft-min-coverage[96]: Minimum coverage requirementfor core BIST.

dft_max_pat[3500]: The maximum number of patterns

that should be considered when looking for a solution.

dft_max_tp[300]: The maximum number of test points

that should be considered when looking for a solution.

dft-min-tp[l]: The minimum number of test points that

should be considered when looking for a solution.

dft-ident-tp [dft -ma x-tp+lJ]: The initial number of

test points to be identified (should be above dft-max-tp

to provide a pool to select from).

dft_tp_cost[l5]: The relative cost of a test point, used in

rating solution quality.

dft-pat-cost[l]: the relative cost of a core BISTpattern, used in rating solution quality.

dft_aggressive[90]: controls how aggressively the

strategy routine attempts to reduce the solution space.

dft-threshold[dft-max-tp/20]: controls how close theprogram needs to come to the optimal solution.

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Primary outputs of this tool include the ASIC Scancore

design which has been made fully scannable and meets

the desired fault coverage. Other ou tputs include:

0 design specific BSDL file (expanded template)

0 number and length of scan chains

0 exact fault coverage for the core BIST (ignoring

0 exact fault coverage for ATPG tests

0 number of test points

Q patterns required to meet specified fault coverage

Q known g ood MISR signature for the core BIST test.

aliasing)

2.3.3 Auto Test

The final ASIC BIST tool, “Auto Test”, is aimed at

verifying correct test structure implementation andperforming stimulus generation for gate level simulation,

factory diagnostics, integration, and foundry test. This

data hub maximizes data reuse for all ASIC designs and

provides a mechanism for diagnostics traceability during

the system integration process.

The objective of this tool is to automatically perform a

VHDL

I SCANCORE Dummy1149.1 BF MATPG reader

Parameter ASIC top levei

F i i e I

-Test -I

GenerationFile’s

COREB~ST ignaturet *Interconnect BiST

*Integrity test scenario’s I Signature’sBoundary Scan test scenario’s

*Embedded Memory test scenario’s* COREBIST est scenario File’s

COREBIST DIAG test scenarioa PRPG DIAG test scenario’s

CommandTest Segment

- Paameb i c test scenario’s

VHDL behavioral simulation of an ASIC specific test

bench and provide a g oh o-g o result as to whether all tests

functions were performed correctly. This insures chip

assembly has created a testable ASIC the way the designer

intended. Several important byproducts are produced

during this process, these include:

behavioral simulation results saved for gate level

simulation. Gate level results are extracted and

formatted as foundry test v ectors.

0 Auto Test macro files used for board level diagnosis.

These macros em ulate the interconnect BIST test using

simple 1149.1 instructions (SamplePreload, EXTEST,

etc.). This data is used by factory test engineers to

isolate pin failures reported during interconnect BIST.

0 calculation of sender and receiver signatures for each

ASIC in all interconnect BIST sub-tests.

The ASIC specific VHD L test bench is shown in Figure 6.

Auto Test assembles a set of design specific command

files which are used by the test bench to exercise test

logic. The command files contain both test stimulus andexpected data interpreted through the 1149.1 Bus

Functional Model. All TDO data is monitored during test

ASIC Specific VHDL Test BenchPattern

Scan Data Input

I

Scan Data OutputATPG Results

Checker

UStimulus For Gate Level Simulation(Results Data Base)

Figure 6. Design Verification and Stimulus Generation Process

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bench simulation for correct output. The following test

scenarios are created an d simulated:

Integrity test: basic TA P functional tests

0 Boundary Scan test: boundary scan and patterns

Embedded Mem ory test: RAM BIST of internal

0 Flush: scan chain integrityCORE BIST test: BIST of Scancore logic

CORE BIST DIAG test: diagnostic BIST of S cancore

0 PRPG DIAG test: diagnostics for PRPG

Parametric test: parame tric tests using boundary scan

broadcast test

memories

logic

register (VoJVoH, 3-state high-z, output pullup/

pulldown current, input output pullup/pulldow n

current)

0 VIH-VIL: arametric test using boundary scan register

0 ATPG: sequential ATPG to detect remaining CORE

BIST faults

GateTest Structure Count

(SCAN &

3. Results

All processes and tools are in place and being used. A

total of 15 ASIC designs ranging in gate cou nt from 60k-

170k gates (complexity from controllers to data

processors) have com plete d this process.

GateCount(BIST

Results are separated into two areas, test logic resource

requirements and ASIC specific metrics including tool

performance for each A SIC.

lntedaceTest Points 0 1gatesnP

InterconnectElST Controller

Scan flip-flops

Total

Table 1. shows an example gate count for test structures

using the ASIC BIST technology. This particular design

1,300

600

10.000

22,400 12,200

Test Block I 700 IRAMEIST Test Memory Interface I I 2,000

RAMEIST PhvsicalMmow I I 2,000

Table 1. Test S tructure Gate example (lOOk gate

design, 5K flip-flops, 25 6 functional VO).

example is a Texas Instruments TGC2000 ASIC with

approximately lOOk gates of application logic (not

including memory), employing 5k flip-flops, and having

256 functional VO. There are two embedded memories

(dual port) 512x8 , and 1 external memory 2kx16 SRAM.

Test specific details include 80 scan chains, 64 lip-flops

per scan chain and 120 test points required to achieve

98% fault coverage with l k pseudo random vectors (one

vector equals one comp lete fill of ail internal scan chains).

Table 1. has two colum ns depicting gate counts. Colum n 1

includes gates associated with full scan and 1149.1

functions and column 2 depicts gates associated with

BIST specific logic. The intent is to show the additional

logic required to progress from what we believe is

required for a minim um test capability for an ASIC design

of this size and complexity, to a full BIST im plemen tation

as described in the architecture section of this paper.

Rough ly two thirds (-17% of the total ASIC gates) of test

related g ates are used for 114 9.1 and full scan capabilities.

An addition al one third (-9% of the total ASIC ga tes) are

comm itted to BIS T related functions. Although these gatecounts may seem initially high, its important to recall that

BIS T of embedde d/external memories and modu le level

interconnects is being accom plished by logic contained in

the ASIC design.

Table 2. shows ASIC BIST metrics that have been

collected from 6 ASIC designs. A fault detection strategy

was specified through use of the dft-targets targeting 96%

fault coverage with a minimal number of test vectors

using as many test points as required. The remaining 4%

of undetected faults are attacked using traditional ATPG

methods.

* Auto Test run did not include core BIST simulatlon

Table 2. ASIC BIST m etrics

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Tool-related time metrics are reported in wall clock time

for a SPARC 10 with 128Meg memory installed. A brief

description follows:

Chip Assembly: Automatic insertion of‘BIST structures

(TAP , MISR, PRP G, BIST Controller, etc.) described in

VHDL, automatic test bench creation for test structure

verification and foundry test vector generation.

TEASIT: Test point identification and backannotation,

scan chain insertion, fault simulation and analysis, BSDL

generation, and final signature calculation.

Auto-test (post-scan):VHDL behavioral simulation of

ASIC under test (including CORE B IST function).

4. Conclusions

Sanders’ focus is to provide an enabling technology to

meet our customer requirements, win more business, and

provide a simplified and standardized test architecture for

our factory and field. To this end, the design process hasbeen augmented to accommodate a test strategy based onBIST. Specifically, the ASIC level has been addressed to

meet the needs of near term programs and provide a

starting point for a company wide module and system

level test architecture.

In general, we have found no fully automated commercial

solutions providing BIST synthesis for ASIC designs

which consider a company’s existing ASIC design

process. However, Sanders has created an automated

process, with tools based on a structured BIST

methodology, which is repeatable and deterministic in its

ability to meet detection and isolation requirements.

A significant reduction in design cycle time has been

experienced since the inception of the automated ASIC

BIST insertion capability. In the past, at least three man

months were required to hand craft an ad-hoc scan BIST

only implementation which provided no guarantee of

meeting specified fault coverage requirements. Designers

were required to become experts on DFT and BIST,

taking away significant time from their main task of

designing and verifying application design. However,through use of our chip finishing process, ASIC designershave more time to concentrate o n the application function.

Although automated ASIC BIST does not guarantee firstpass success, it clears many impediments which normally

shifts focus away from design implementation and

application verification. It also provides structured design

styles which decrease the proba bility of poorly constructed

designs.

Acknowledgments

There have been may individuals who have contributed to

the success of the automated ASIC BIST tools and

process. The authors would like to thank each for their

hard work and diligence in making A SIC a success. These

include: Jason Boucher, Nancy Fernald, Angela

MacKinnon, Don McManus, Roger Morby, Craig Reiff,

Geoff Saucier, Sean Sweeney, and S teve Tereshko.

References

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