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A~ Efficient SiDgle-Latch Scan-Design Scheme
B:t
Uma R~anda "
Department of Electrical Engineering
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MeGill University
Montréal
@ March 1985
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An Effièient Single-Latch Scan-Design Scheme
By
Uma R. Panda
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A thesis submitted to the Faculty,of Graduate Studies
and Research in partial fulfillment of'
Master of Engineering
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Department of Electrical Engineering
McGill University
Montréal <'1
March 1985
©by Urna R. Eanda ~ ..
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l Abstract
With the increasing complexity of logie implemented on a single Very Large Seale
Integrated (VLSI) circuit chip, there is a growing problem of checking the logical behav·
ior of the chips manufactured. The problem is' particularly acute for sequential circuits,
due to difficulties in initializing, controlling and observing the stat} of the s~btem. A
possible solution to this problem is ta incorp<?rate Scan·Path into the sequential circuits.
One of these Scan-Path designs is Level-Sensitive Scan Design.
c~
A variation of Single-Latch Level-Sem:,itive Scan Design is described in this thesis.
\ The new scheme eliminates the two shift docks, thus considerably reducing the area
ovei-head. A ?wode Control' signal switches the circuit between a 'Scan Mode' and
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a 'Normal Mode'. The same system docks are used III both scan and normal modes.
The system rerformance is not degraded with the use of latches proPQ&ed in this work.
Advantages anq cost impact of this schElril.e are also discussed. Technical details of 1
the proposed shift register latch are documented and performance improvements are l ' •
identifi~d throu~ extensive simulati~n. An estimate of area overhead and performance,
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and a set of design rules that will result in Levet-Sensitive logie are also described.
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Résumé 1 .
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Avec la com'plexité croissante des circuits à haut niveau d'intégration (VLSI), la
vérification du fonctionnement logique des circuits fabriqués devient de plus en plus
problématique. Les circuits séquentiels offrent le plus de difficultés, dû aux prohlèmes
d'initialisation, de commande, et d'observation de l'état du systême. Une solution a~x
probièmes des circUlts séquentiels est un typé de conception appelé "Scan Path'. Un cas
particulier de conception 'Sc,an Path' s'appelle 'Level Sensitive Scan design'. , \
Cette thèse décrit une modificatio,n apportée au type~>appelé 'Single-Latch Level
Sensitive Scan Design'. La modification élimine les deux signaux de commande 'Shift
Clock~' nC?rmalement utilisés avec 'Scan Path', ainsi réduisant la superficie de sjlicium
additionelle reqUise. Un seul signal, '\iode Control', commande le fonctionnement du
circuit (entq~ les m'Odes 'Scan' et 'Normal'). Les mêmes signaux de synchronisation
C'clocks') peuvent donc être utilisés pour les deux différents modes de fonctionnement.
"En utilisant le nouveau type de' 'Latch' ('Shïr't Registe! Latch ') proposé. la performance
d'un circuit n'est pas déteriorée. Cette thèse présente.en details. les avantages et coûts l, '
, de Iii solution proposée, ainsi que les characteristiques techniques concernant le nouveau
type de "Latch'. Les analyses de performances sont appuyées par des résultats de sim-
ulations. Enfin, cette thèse comprend une estimation de l'aire additionelle requise par
la modification propo::;ée, ainsi qu'un ensemble de rè"gles de construction requises si la
sol u tio""pro posée était app 1 iquée aux cirer ts de f~e 'Levél Sensitive Logic':
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Acknow ledgement
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The author expresses sincere thanks to Prof. V.K.Agarwal for his excellent guidance
and' cooperation. Appreciation is also due to Prof. N.Rumin and DII. Janusz Rajski for
their advice a~d help.
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TABLE OF CONTENTS
page
Abstract ....................................................... , ............. . iii
Résumé ........................................................... : .......... . iv
Acknowledgement ....................... ' .................................... " .. v
Table of Contents .... '" ................... , ................................. .' vi -.;
List of Illustrations' .............. ' .... 1 •••.•••..••••.••••...•••••••.•.••.••••.• viii
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1 Introduction ....................................................... . 1 .
2 Review of Existing Schemes ..................................... .' . . . . . . . . . . . .. '5 . '
2.1 Fault Modeling and Analysis ... , ........... , .............. ,.. . . . ... . . . .. .. 5
2.2 Controllability and Observability ........ " .. , ...................... , . . . . . . 7
2.3 . S~ed Design For Testability Methods ........ ~ ................ \. . . .. . . 9
2.3.1 Level-Sensitive Scan Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.2 Scan Path Design ...... " ... " ..... , .......... , ... , ...... , .... " . . . .. 19
( 2.3.3 Scan/Set Technique, ... , ... , .... ,.. . ... . . ........ . ..... .. . . .... . . . . . 21
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2.3.4 Raqdom 'Acce.ss S~an ............................................... . 23 : \,
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2.4 Variations of LSSD Scheme " ........................................... . 26
2.4.1 Sa!uja's Scheme .................................................... . 30
\2.4.2 L2* Scheme ........................................... ; ............ . 33
3 Proposed Scheme. , . , . , ...... , . , ..... , , ............. : .... l ••.•••••••• : ••••••• 39
3.1 Testing of MSRL ....................................................... . 52
3.2 Design Rules . . .. . ................................... ' .................. . 53
3.3 Area and Performance Overhead ............... , ........................ . 55
3.4 Comparison with Other Schemes ........... f •.•......••...•.•.•....•• , •.. 62
.. Simulation ........ . 66
4.1 CMOS Implementation ........................................... ',...... 66
4.2 Physical Design Considerations ................... '" . . . . . . . . . . . .. . . . . . . . 66
4.2.1 Latch Output Considerations ......... '," ................ '............. 69
4.2.3 Latch Scan-Output Considerations .. '" . .. .. ..... . . .. .. . . . . . ... . . . . .. 70 ...
;} Conclusion ... " ........ , ........... '" . . . . . .... . . .. . .... . . . . .. . . . . . .. . . . . . . . 75 1
" References: : .......................... , ., .............. , ........ ~ . . . . . . . . . . . . . . 77
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. A.ppendix A .. . 1 • •••••• , ••••••••••••••••••••••••••••• , '" .................... -. • 81
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LIST OF ILLUSTRATIONS
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1 Fig. 2.1(~) Fault-Free AND Gate .... 1 ............... : ......................... 6
2 Fig. 2.1(b) AND Gate with Signal Stuck-At o ......... : ..................... " 6
3 Fig. 2.2 Sequential Circuit with Clocked D Flip-Flop, ........ ,' ' .... , . , ..... . . 11
4 Fig. 2.3'Modified Sequential Circuit .... , ... , ........ , ... '" . , , .,. . . . . . .... . . 12 t; ~ ,'"
5 Fig. 2.4 Double-Throw SWlt~h ....... , ....... , ......•..•......... :.... ....... 13
. 6 Fig. 2.5 Logic Implementation of Hazard-Free Polarity-Hold Latch . . . . . ..... . 16
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0--- Fig. 2.6 Classical Model of a SequentiaJ Network Modified for Shifting. .... . . . 17
8 Fig. 2.7 LSSD Shift Register Latch .... '" . . . . ...... . . ... .... . . . ... . . . . .... . . 18
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Fig. 2.8 Raceless D-Type Flip-Flop with Scan Path .............. ' ........ ~. . . 20
io Fig. 2.9 Scan/Set Logic ........... : ... '" .. ' .. " .............. , .. ".. . . . . . .... . . 21
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Il Fig. 2.10 Rand~m Access Scan ........... '................... ............... 24'
12 Fig. 2.11 Polarity-Hold Addressable Latch .. ; ............. _ .... " . . . . . .... . . 25 " -
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. Fig. 2.12 LSS~ Doub-Ie-Latch, Design.. . ....... ................ . ....... . .... 27
. 14 Fig. 2.13 Single-Latch LSSD Configuration ..................... '....... . .... 29
15 Fig. 2.14 Polarity-Hold PSRL ., ........... ,' ........... ' ... : .......... : ...... ' 31
'" 16 Fig. 2.15(a) Normal Mo?e ............. ~ .; ."" ....................... ; ......... 32
17 Fig. 2.15(b) Test Mode .......................... : ................... ; ........ 32 1
18 Fig. 2.16 SRL with L2* Latch .......... :....................... ............ 34 '- ... -~-
19 Fig. 2.17 Untestable Configurati?n ........ , ............. " . .. . . . ... . . . . . . . . 35
2Q Fig. 3.1 Latch Structure in L2* Scheme .................. ,.... . . .... . . . ...... 40 0
21 Fig. 3.2 Steady-State Hazard Condition ........... '" . 41
22'> \ .................... 42 Fig. 3.3 Transient Hazard Condition ..... :-.: ......... .
23 Fig. 3.4 Hazard-Free SRL using L2* .................. . 44
24 Fig. -3.5(a) Proposed Scherne (MSRL) .............. ,;-.... ' ...... : .... : ..... ..
25 Fig. 3.5(b) Proposed Scherne (MSRL) ............................. : ...... '"
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Fig. 3.6(a) Truth Table for MSRL ........................... ' ......... .- .... .
27 Fig. 3.6(b) Waveforms for MSRL ........................................ '"
, 28 Fig. 3.7 Single-Latch Structure using MSRL .............................. ..
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30 Fig. 3.9 Polycell Design -~ayout .............................. : ....... ,' ..... .
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- F!g. 3.10 Layout of Scan Circuit .. ' .................................... : .... : - "
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32 Fig. 4.1 CMOS Implementation of MSRL ................. ; .......... ' ...... ~ , ~ 1
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33 Fig. 4.2 Schematic of LI-L2 Latch Pair ............................ " ...... . 68
34 Fig. 4.3 Output Response Time Vs W IL Ratio of Pull-Up Deviee ...... : ... . 72 ,
3S Fig. 4.4 Output Résponse Time Vs W IL Ratio of Pull-Down Deviee ........ , j J
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Tétble 3.2 Comparison of Area Overhéad for MSRL and L2*, .g Varies ...... -.
Table 3.3 Compari~on of MSRL with other Sehemes ............... : ......... .
Table 4.5 Capacitive Load Vs Circuit Response Time ..................... /.
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Introduction
1. Introduction \ t . \
Testing IS one of the mawr techIiical problems encountered while designing
LSI/VL l chips[l, 2, 3! .. This testing problem can be substantially reduced or com-.
pletely olved by adopting a design discipline, such that the chips are designed for
tes'tabili r[4J. In addItion, an appropriate design p.hilosophy can be adopted for the f .
higher 1 veJ machine componentsiS i (e:g., boards. systems).
Testing of chips is carried o~t by applying bit patterns to stlmulate the logic inputs
and by comparing the actual output response to an expected one. which has been
precalculated. Generation of the stimuli and responses ;~ achieved by simulati~g the
function of the chip[2, 6j. Such patterns can be sometimes obtained as a by-product
of design verIfication. General!y such functional test patterns produce only a limited , ,
test coverage, sirice they reftect the designer's objective as simulated against a good
machmeI2]. (
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To àchieve a more complete test coverage, the test patterns must permit ta distin-
guish th.e good machine from al! possible. faulty machines. Such a set of test patterns ..
will guarantee that the machine is free of faults. One model that is widely used ta
represent a faulty machine is the Stuck-At fault modelfl, 2, 3, 71. Test patterns that
can detect such Stuck-At faults can be derived for combinatlonal Clr-cults by using al-
gorithmic methods yielding 100% test coverage However. for sequential circuits, test
pattern generation algorithms are difficuÎt ta appl~, and, in practice. test coverage is
generaUy lowi8:.
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Introduction
[t has been established that test generation for a single Stuck-At fault is NP
complete (9). This means that therf' will be a number of circuits for which test generation
time ~s an exponential function of circuit size. However, the theory seems extremely
pessimistic cornpared with experience' of weil designed algorithms(15, 16, 17]. It has
been observed [9] that the computer run time to do test generation and fault simulation
is approximately proportional to the number of logic gates to the power of 3. Hence,
smalI increases in gate count will yield high-increasing"run times. The following equation '
shows this relationship : ,
W~ere T is the e~pec:ted computer run time, N is the numberof gates, and K is the 1
\ proportionality constant. It has been observed that computer run time just for fault
simulation is proportional to N2 without the test generation phase.
To find tests for sequential circu~ts, the pro!:ù'em that must be solved is determining
a test p'attern sequence whieh brings the memory elements into astate needed for
applying the tests. Historically, designers improved the testability of sequential logie , ~
by practicing different design tricks. These are called the 'Ad Hoc' methods[4]. One of •
, these 'Ad Hoc' methods most commonly practiced provides a corn mon reset inputllOl
for counter or shift register latehes. -The reset input is used to obtain a defined machine
state: Tests could then be designed by stimulating the logic from th,is known state to
a-state needed to apply a test. An obvious disadvantage with this approach is that
long test pattern s~quences are required since many tests originate from -the same reset , '\ ,
state. To overcome this disadvantage, an împrovement to the above approach consists
of breaking counters into ,subsections, each of which can reset individually. This $tilt o
lead to shorter test pattern sequences. In addition to reset inputs, test points can be
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Introduction "' ..
added to the circuit. This will permit to apply tests more readily- and observe tests
results better. Designing with these approaches requires much designer ingenuity and
lacks a general applicability. In addttion, while chip testability may be improved, such
methods often do not assist in card testing.
Another way to tmprove testability, a more structured, approachr Il], is' to design
a chip in a fashion such that the combin-ational clements. and the sequential elements
are partitionable. ln general, this partitioning does require sorne additional circuits "
such that connection of ail latches on a chip to one or more shift registers becomes
possible. This creates access to the combmationaJ logic p'artition and test patterns
can be supplied via the shtft regi::,tC'rs. This structured approach to testable design is
ca lied 'Scan-In, Scan-Out' or more commonly, just 'Scan ': 121. One of these 'Scan' based
designs is 'Lev'el-Sensltive Scan DesIgn' (LSSD) [13:
Ali the testable design methods have the same objective: to reduce the cost of
testing. An empirical teiationshipilli that has been used for estimating the cost of
finding a faulty devlce IS that the cast will increase by a factor of 10 as fault-finding 1
moves from one level to the next, i.e., if it cost $0.'30 ta detect a fault at the chip level,
then it would cost $3 to detcct that sarne fault when It was imbedded at the board level:
and $30 when it was unbedded at the system level, and $300 when it IS Imbedded at the
system level but has to be fOH-Iln in the field. Thus, if a fault can be detected at a chip o
"or board level, then significantly larger costs per fault can be avoided at subsequent
levels of packaging.
In VLSL th~ inadequacy of automaqc test pattern generatton and fault simulation,
makes it dlfficult to obtain a level of testability required to achieve acceptable defect
levels. If the defect level of boards is too high, the cost of field repairs is also too high .
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These costs, and in sorne cases, the inability to obtain a sufficient test, have led to the' , '
,need to have 'De~ign For Testability'.
In this thesls report, Chapter 2 gives a review of existing structured Design For . , "
Testability (D~T) Schemes. Chapter 3 describes the proposed scheme. which is a vari
ation of 'Level-Sensltive Scan Design'. Chapter 4 presents one way of impl~rnentmg a
circuit design of the proposed '~odified Shift Reglster Latch' (MSRL) with detailed
simulation results.
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Review of EXlsting Schemes
2. Review of Existing Schemes c
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With the utilization df LSI and VLSI technology, it has become apparent that \
testability has to be considered as a design parameter[ll]. This has led to rigorous and
highly structured design practices. Most structured design practices are built upon the
concept that if the values in aH the latches can be control/ed to any specifie value, and if
they can be observed wlth a very straight forward operation, then the test generation,
and posslbly the fault simulation task, can be reduced to that of doing test generation
and fault simulation for a combinationallogic, network, A control signal can sWltch the
memory elements From their normal mode of operation to a mode that makes them
control!able and observablei 141, This chapter describes the basIC concepts in testmg,
begmning with the fault models and carrymg through to the different variations of
Level-Sensltive Scan Deslgn,131 which was proposed by IBM.
2.~ Fault Modeling And Analysis
A model of faults which does not take into àccount ail possible defects, but is a
more global type of model, IS the Stuck-At model[l, 2, 3, 71. ThiS is the most widely ..:..
used mode!. The Stuck-At model ~sumes that a logic gate input or output Îs fixed to
either a l~gic 0 or alogie 1.
For,example, consider the fault-free AND gate G shown III fig. 2.1(a). Fig 2.1(b)
shows ,he same gate with its input A stuck at zero. In the presen,~e of a stimulus. A == l
and B=l , the faulty gate output 15 C=O. and the fault-free output IS C= 1. The inputs , .
conditions that cause a faulty circuit to behave differently from a gOQd circuit are
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RWlew of Existmg Schemes -
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, , Fig. 2.1(b) AND Gate with Signal Stuck-At 0
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Review of EXlsting Schemes
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considered to be a test for that particular fault. In this case, the fault (A stuck at zero)
is detected by t~e test A=1. 8=1.
Test generation techniques are availab~e for strictly cornbinational circuits[l]. A
combinational circ.uit containing N inputs can use 2 N patterns, to verify each entry in
the truth table. For larger networks, heuristic or random patterns can produce an ac-
ce~table starting point for test generation. But v~ry large and cornplex designs require a
-deterministic or algorithmic approach. The most widely used test-generation algorithm
is the D-algonthm' 15. This 'à,lgorithm 1S still the basis for rnost of the techniques in
use.today. Many recent algonthrns such as PODEM[16] and FAN[lï:, however seem to
have a better performance than the D-Algonthm.
Unfortunately. c;('qucntlal circuits rapidlv increase the complexity of test generation
and, in VLSI designs, make the test generatlOn nearly useless. :vIany of the approaches ./
that use structu~d testability reduce the test-generation problem by converting ~equen-tial circuits into combinational ones in a 'test' mode.
Finally, several physical circuit failures de pend on the technology used. These
failures often cannot be described by the single Stuck-At model. For example, bridging
faults 18! produce behavlOr that cannot be modeled with a single stuck at model Sorne
failures in CMOS devlces can cause a combinational network to behave like a sequential
elementl191.
2.2 Controllability And Opservability
There are two key concepts III testability: Controllability and Observability. Con
trollability[12] is defined aS th~ e,!-se of setting a particular internallogic no de to either
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Review of Existmg Schemes
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logic 1 or logie O. Observability' 121 is defined to be the ease of observing t'he response
of an internaI logic node. An internai node is conÙolled from the primary inputs and . ' observed at the primary outputs and the process of test-pattern generatlon relies on the --
, ability both to control and to observe each node in the circuit. A measure for nodal
testability can therefore be quantified in ter ms of nodal controllability and nodal ob
servability values. Circuit testability[20) can then l>e d~termined from a knowledge of
the circuit.
Control and observation of network nodes are central to implementing test proce
e dure. For example, considering" the case of fig. 2.1(a), in order "to be able to test the
:\ input Sluck-At 1, it was necessary to control the A input to 0 and the R input to
1 and be able to observe the C O'utput to determine whether a 0 was observed or a l
was observed. The 0 is the result of the good machme, and the l would be the result 'of
faulty machine. If this AND block is embedded into a much larger sequential network,
the requirement of being able to eomrol the A and B inputs to 0 and 1, respectively,
and being able to observe the output C, through sorne other logie blocks, still remains. ,
Therein lies part of the problem of being able to generate tests for a network
In essence, therefore. testability measures based on controllability and obscrvabilit\
features are really only a measure of the ease of generating test pat,terns: Recause of
the need to determine if a network has the attributes of controlla,!?ility and observability -'
that are desired, a number of programs[21, 22, 23] have been wntten whlch essentially
give analytic measures of controllability and observability for different nodes in a given
sequential network. Of neeessity. sueh measures can only produce coarse results since.
in reality, the only real measure of testability is the co~3't of producing an adequate set
of tests for the circuit :\evertheless, there wou Id seem to be many uses, 121 for such
measures, such as:
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(a) Advising on the better of two designs (a revised de~ign may have a higher
testétbility rating than original);
" __ ~ if "(tJ) AlIo~ing a judicious selection of test points (nod~s with low observability are
" obviously good candidates);
(c) Identifying potentially difficult nodes to test (low controllability and observ
ability)
However, to be useful, a testability measure should be inexpensive to compute in
comparlson with the costs of deriving the tests .
. 2.3 Structured Design For Testability Methods
Th~ most widely accepted structured testability technique is -the Level-Sensitive "
Scan Design (LSSD) method proposed by Eichelberger and Williams [131. This method
is actually ~ combina~ion of two separate design strategies. Level Sensitlvltj Implies the
operation of a logical network that is mdependent of interna! circuit delays and pnmary
input skew. Design rules are specified to guarantee this effect. Scan design embodies
two functions for ail sequential circuit elements. An auxiliary mode I!'> avatlable that .
lets all memory devices be connected as a shift reglster vVith thls connection, testmg
the sequential devices becomes a matter of simply shifting alternat mg sequences of
1 's and O's through the register and verifying the patterns at the output stage. One . .
immediate benefit of scan design is that it reduces the testing problem to that of testing
the remaining combinationallogic of the circuit.
The shift register modification approach was first presented by Williams and Angell
in 1973 [14). This approach uses c\ocked D flip-ftops as the storage elements. as shown in
9
,< .j
(
(
\ ,,- .
Review of Existing Schemes
fig. 2.2 .. The structure of 'Shift Register Modification' approach is illustrated in fig. 2.3.
The modification IS do ne by inserting a double-throw switch at each input lead of every ,~
flip-flop, and in the lead that drives one of the primary outputs of the circuit. Each
of the double-throw switches may be implemented as shown in fig. 2.4. The modified
sequential circuit can operat~ either in its normal mode or shift r~gi~ter mode. When..
the mode signal isiset to a O. the circuIt operates in the normal mode, i.e., it behaves
exactly as it tiid before modifications were carried out. When the mode signal is set
to 1, ail flip-flops in the circuIt are connected in a chain and form a shift register. In
this shift register mode, the first flip-Aop can be set directly from a primary input, and
the output of the last Aip-flop can be4.irectly monitored at a primary output. Hence, .
the modifi~d circuit can easdy be set to any desired internai state by supplying the
correspQnding values to the shift register and further the internai state of the circuit
can easdy be ob-:::it~ived by shifting out the contents of the shlft register.
The other widely accepted structured techniques are generally very similar to LSSD . .
Scan Path designf24], proposed by Nippon Electric Company (~EC), implements the
scan register by using D-type Aip-flops. Scan/Set technIque [251, put forth by Sperry
univac has a shift register path, but these shift registers are not In the data path. In
the Random Access Scan[26!, proposed by Fijutsu, shift registers are not employed
but an addressing scheme IS provided which allows each latch to be elther controlled
or observed. This section takes a doser look at ail the above mentioned structured
testability'methods.
2.3.1 Level-Sensitive Scan Design
Level-Sensitive Scan Design (LSSD) introduced by Eichelberger and Williams 13·
ensures race-free system 'operation as weil as race-free testing. To provide reliable
10
---..,.lS!_.JI ____ ..... ~~~"""-.. t""'l .... tU __ _ __ .II
\ -
c
.
LK "
Review o{.Existmg Schemes
)0 - " 0 -7 . 1 /
rl ~ 1
~
1
,
,il ,~
" 1 , -" COMBINATIONAL, 1 1
1 (
, 1
1 ,
LOGIC 1
1 . 1
1 1
1 -" , 1 .
, f
Fig. 2.2 Sequential Circuit with Clocked D Flip-Flop .
11 {
Q~;tau;l $ J, ..
l ,
.-'"
... /
.. /
/
-',..;.-----
.,.
Revlew of EXlsting Scheme,
MODE CONTROL" ~.
. ... , ...,
(' , SW
\ $W ~ 0 ~ D ~
--; 'f--~ 1 ,
1 0
, , p
,
ri ~ ~ " ,
), ,l; CLOCK -
~ ... / ,
SW , '- ... ~~
... " COMBINATIONAL , ....
" LOGIC 1 /
1
• (1 '- 1 t "
1 "-
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Fig. 2.3 Modified Sequential Circuit
, 1 )
12
li
_~G"''''I--~ --..._ . ....,. __ ...... 01 __ """'.!\"""'. ___ 4 _;:;_;_JCI&42!JSif4_"",,*_:e _*_-.... --.. -,.-,--------.. .--...... _ 1 J • op,--'l!
(
(~)
Review 0/ EXlstmg Schemes
A
8
\. 7
\J "1
A--+---"1... ____
8------4 '-----"
,
'""' SW
Fig. 2.4
~
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-PA+ PB
1 •
D'ou ble-Throw Switch
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t ~ t
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Review of Existmg Schemes )
>
operation of. ~ circuit, the, designer must consider testing several ac design parameters
such as rise time, fall time and delay. However, in LSI/VLSI it will become impossible
or impractical to test ail the ac design parameters in each circuit. The LSSD approach
aims at obtaining logic circuits that are insensitive to those ac characteristics. The term , ~ ~
'Level-Sensitive' is defined by Eichelberger and Williamsl13j as follows: ,
'A logic subsystem is Level-Sensitive if and only if the steady-state response to any 1
"allowed input state change is mdependent of the circuit and wire delays within the
subsystem. Also, if an input state change in'volves the ~hanging of more th~n one
-input signal, tpen the response muste be independent of the order in which they
$nge. Steady-state response is the final value of ail lo~ic gate outp'uts after ail
Q change activity has terminated.'
1
It ,is dear from this definition that level-s~nsitive operation Îs dep,endent on having
only 'allowe~' input changes. Thus, a level-sensitive design method will, in general,
include sorne restrictions on input changes and are applied !ll0stly ta ~he dock signais. , ~ "f
Other inp"ut signais have almost no restrictions on when they may change.
A level-sensitivesubsystem is assumed to operate as a result of a sequence of allowed
changes to allow the subsystem to stabilize in the new internai "tate This tinH' duration
is normally ensured by means of dock signaIs that control the dynamic operation of the
logic network.
A principle objective in establishing design constraints is ~o obtain logic subsystems ':; ~~J
that are insensitive ta ac characteristics such as rise time, fall time. and minimum circuit \,.
delay. Consequently. the basic storage element should be a level-sensitive device' that
does not contaln a hazard or race condition.
14 t ' \
.,
"
_._ ...... _-
Review of Existmg Schemes
The polarity-hold latch[13j as shown in fig. 2.5 has two input signaIs. When C=O,
th~ latch cannot change state. When C=l, the internaI state of the latch is set to the
value of the excitation input D. Under normal operatfng conditions, the c10ck 'signa)
C is 0 du ring the time when the excitation signal D may be changed. This prevents
the cha.nging of D from immediately altering the interna:i s~ate of the latch. The clock
signal will normally occur after the excitation has become stable at either a l or a O.
This causes the latch to be set to the new value of the excitation signal when the clock
signal occurs. The correct changing of the latch is dependent not on the rlse or fall time
.>= of the clock signal. but only on the clock signal's being l for a period equal to or greater ~~
\
than TO, where TO is the time required for the signal to propagate through the latch
and stabilize. This polarity-hold latch is further augmented to mclude shift capability.
With the concept that the memory eleinents In an integrated circuit can be threaded
together into a shift register the memoty element values can be both control\ed and o~ /
./
served. Fig. 2.6 shows the familiar generalized sequential circuit model[ Il] modified
to use a shift register. This technique enhances both controllability and observabil,. ity, allowing to augment testing by controlling inputs and internaI states, and easily
examining internai state behavlor.
Fig. 2.7 shows the.latch called the Shift Register Latch (SRL) which IS used in the
LSSD aS the basic rncmoryelement. The polarity-hold SRL~ 13! consists of two latches,
LI and L2, which have the scan input 1, the dati.: inpyt D, the system clock C.and two
shift control inputs, A and B. In the normal operation mode, the shift sIgnais A and B . \
are both set to 0 and the LI latch operates exactly like a polarity-hold latch. The clock
signal C is 0 du ring the time when the data input D may be changed After the data
input has become stable at either a l ?r a O. the clock C will change to L whlch causes 1
the ~'l latch to be set to the value of the data input D.
15
1 1 ; , t l,
...
/
Revlew of EXlstrng Schemes
o . , •
.'
C
• c.
- . ,\
\/ \ L () 7
-, . ,
\ ) ,
, c
'b
Fig.- 2.5 ,
Logic Implementation of Hazard-Free
Polarity-Hold Latch
16
.... -"1ft_. ~. _"' .............. I~""' .. "... ___ • ___ ._ .. ;t ....... u_.""''"_ ..... _ • ...... a_-o\or-·_· ._-- ~J ~~- l'
~ ~ ~ {~
l (
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t t
t t , 1
t .. 1 1 r
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Re~it!w of Exist1'ng Schemes
NPUTS " ;')OUTPUTS l COMBINA-TIONAL SCAN OUT,
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,
~
LOGIC ,
" 7
.- ,
REGIS-
CLOCKS TER
" ,
\ 'r ' SCAN IN
\
\..
Fig. 2.6 Classical Mode} of a Sequential Network
MQdified for Shifting
\
17
,
r
,
. ,
Review of EXIstmg Schemes
o
c
\ A
B
Fig. 2.7
( " , , ,
,// LSSD Shift Register Latch
18 ,
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, 1
1 ~
, 1
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i
Revlew of EXlstmg Schemes "
1
In the shift register mode, the clock C is set ta 0 and both shift signais A and B
are alternately changed to shift data through latches LI and L2. First, by changmg A
to 1, àata from the[ 19apreceding stage can be loaded into the latch LI through the scan
input 1. Then after A has changed back to 0, the B slrift signal ~changes to 1 to load the
data from latch L2. Output L2 of latch L2 is connected to scan input, 'r' of the next
stage SRL.
Eichelber!f.er and Williams[13] presented a set of design rules or c~nstraints that , "
will resu,lt III level-sensitive and scan deSign These rules are glven III Appendix A.
Whether a logic Circuit IS designed in compliance wiJ,h:1hese rules can be automatically ~
checked by a method developed by Godey etct27L ,/
2.3.2 Scan Path Design
,
The objectives of the Scan Path [24] technique are the same as the LSSD approach
which has been described above. The memory elements that are used III the Scan Path
approach are raceless D-type flip-flops and are shown in Fig. 2.8. ln normal mode of
operation, c\ock 2 is at a 10glC 'high' for the entire period. This prevents the test input
from affectlllg the data !fi the first latch. Also. by having clock 2 at alogie ·hlgh'. the
data in latch 2 IS not disturbed. Clock 1 is the sole clock III system operation for this
D-type flip-flop. When dock 1 is at logic :low', the system data input can be loaded
into latch 1. Clock 1 should be 'Iow' for sufficient time to latch up the data. As dock
1 turns 'high', latch 2 is sensitive to the data output of latch 1. As long as clock uliS
'high' so that data can be latched up inta iatch 2, reliable operation Will oceur. This
assumes that the output of latch 2 does not come around and feed the system data,
input to latch 1 and change it during the time that the Inputs to both latch 1 and latch ,
19
o 0' , , ,
; i ,
, 1
,i ,
(
Review of EXlstmg Schemes
CLO 2
SCAN IN
SYS· DATA
CLOCK 1
1 LATCH
, ,
\
a 1 LATCH
Fig. 2.8 ;Raceless D-Type Flip-Flop with Scan Path
. 20 ,\
, /
,.,.~~ Cf- J!< 1--_. ~-~-, ___ . ---------
2
OUTPUl
1
f , , t \
1
, : "
r t' . ~
(
,
r
(
--
) " ReVlew of Existing Schemes
2 are active. The period of time when this can occur is related to the delay of the
inverter for clock I A similar phenomena will occur with dock 2 and its assoclated
inverter. This race condition ,cornes from the ùse of only one system clock. ln the scan
mode of operation, the scan input is ,clocked into the LI latch by clock 2, when clock 2 is l
'low' and the result of the LI latch is clocked into latch 2 when clock 2 is ·high'. Other
than the lack of the Level-Sensitive property, the Scan Path approach is very ,similar to . ~
,
the LSSD technique.
2.3.3 Scan/Set Technique . ,
The basIc concept of the Scan/Set 251 technique is to have shift reglsters, as In
S'can Path qr in LSSD, but these shlft registers are not in the data path Fig 2.9 shows
an example of the Scan/Set logie. The basic concept IS that the sequentlal network can
be sampled at up to 64 points. Thes€' points can be loaded into the 64-bit shift reglster
with a single dock. Once the 64 bits are loaded. a shlfting process will occur, and the
data will be scanned out through the' scan-out pin. In the ca~e of the Set functlOn,
the 64 bits can be transferred into the system loglc, and then the appropriate c10cking
structure required to load data into the system latche'i i::-. requlreu III the S)stf'TlI logle.
An advantage of this technique is that the scan functlon can oecur durmg "ys
tem operati9n, the sampling pulse ta the 64-bit seria] shift regu:iter can occur while
system clocks are being applied to the system sequentlal loglc, ~o that a snapshot of
the sequentiallogic can be obtained and off- loaded without any degradatlon In system
function.
21
, )$« .. __ ~~ __ ~ ___ '_'_CII.*, ~~m " Mf 1 .......... _~ __ ........... ~ ___ ..... __ \
\
'\ (
( 1
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Rev.ew of EXlsting Schemes .
,
S CAN IN PUT
SYSTEM, INPUTSI
, 1
\ l
1
\
64 BIT SERIAL -....'". ' SHIFT REGISTER
\ 1
1 2 - - - -.I~ "'1' :.
SYSTEM SEQUENCE, LOGIC
\.
Fig. 2.9 Scan/Set Logic
22
64 "f"
\
SCAN 0 UTPUT
~- SYSTEM OUTPUTS
(
\ (
Revlew of Existmg Schemes
1 n
2.3.4 l.landom Access Scan
The principle objective of the Random Access Scan [26i design tec~nique is ta allow
each stored-state device ta be separately addressed in order that it can be independently
set or preset, or its output value observed. Fig. 2.10 I1lustrates the principle of the
technique and Fig. 2.11 shows one particular Implementation of the stored-state device.
In Fig 2 10. each latch IS individually selected via the decoded output of the scan-
address register
Fig. 2 11 shows an implementation of an addressable latch for use lU a Random .. Access Scan envlronment. ~ormal operatIOn reqll1res the Scan Clock (SCLK) to be
, held low, m which case changes in System Data (0)' are transferred through ta Q when
the System Clock (CLK) IS low. The last val'ue on D is latch('d a~ CLK goes low"to
high. SCan operation is controlled similarly by the Scan Clock (SCLK) and requires the
SysteI? Clock (CLK) to be held high. When the latch is selected, the latch output can
be set ta the value on Scan Data In (SOI) or the latched value observ('d on Scan Data ."
Out (SDO).
Random Access Scan differs in one respect frorn the basic scan-path philosophy
insofar as it does not contain a scan path as such Indlvidual SDO lineb are normally
high (for non-addressed latches) and can be tied together and. brought out as a single
Scan Output (SO) line. If the selected latch has Q = O. then there is no change in the
observed SO value. If the selected latch has Q = l, then the SDO v.alue will go low,
pulling the mam SO line low. The SDO values of ail latches4 are determmed by cycling
through ail addresses
• "..'l; 23
''''- ' .. ~ __ ~ __ .,,_,_, ~ ___ ~~ ... _____ .. _ .. ___ .. t _t,, _______ ~'"'~ __ ~ .... ~_ ---
,
~' \ ' '
~ , ?
(
Review of Exzstmg Schemes J
LATCH SELECT DECODER .If'
SCAN" 1
ADDRESs----~'~r-~SH~IF~T~-nrRE~G~IS~J~ER~1 SCAN CLOCK ~
2 10 Random Access Scan F-ig. .
; .....
24
--------~---.....-..-..... -If. 1 ,
'.
\ .
() ( t \ r ,
Revlew of EXIsting Schemes
SYS. DATA
SCAN DATA IN
SYS. CLOCK SCAN
CLOO<
SELECT \.
'j
"
\
FI' 2 Il Polarity-Hold Addressa~le Latch g. .
25
Q
---~~10"~ -,..... ... -.-...,.. ... ....-._ .. _a ..... A_,""q;;_c;_· ...... ~_!~_· ___ ,_._, -.--_§ ____ J1l1t __ ~ ..-- .., .. , .......... -n ..... "r.:C _______ t
. Review of EXlsting Schemes
OThe major penalty with the Random Access Scan approach is the amount of time
necessary to set the teJt input values into the latches and subsequently to observe the .
latcheo response. Aiso the overhead in additional gates is relatively high.
y'
2."4 Variations of LSSD Scheme .. f·
In a practical LSSD circuit. the Shift ~egister Latches (SRL) are connected perma-
?int1y to form a scan-path shift registe~ by conry,ecting the L2 output of one SRL to the _~
Scan In (SI) of another SRL.' The two scan docks" A and B. are cornmon to ail SRLs.
Fig. 2.12 shows a general structure for a logic ctrcuit that follows the LSSD rules. The
circuit in fig. 2.12 is called 'double-latch' design, sin'ce both latches are in the system
path.
.. AIl storage elements are implemented as a set of master-slave latches LI and
L2. Each of the master-slave latches is connected in series and c10cked by two non
overlapping docks Cl and C2, where C2 IS equivalent to B. At Cl time, C2 is zëto~ and \ ~"" ....
the inputs and outputs of N are stable. Sorne of the LI latches change their states while . '
Cl is 1. As soon as Cl is changed back to O. the next clock C2 occurs, i.e., C2 changes
to 1. The values of the LI latches are loaded mto the L2 latches while C2 is 1.
In the shift 'register mode, the SRLs are chained to form a sht,ft' register under the
control of clocks A and B. Test patterns are applied to the c'ombinational tlfcuit by 11
scanning them into the shift"'f.egister and applying them at the prirnarx inputs. Then 1
the dock Cl is set to 1 and the response of the cornbinational circuit is captured in the
LI latches and at the primary outputs. The result of the test captured in the register
\
26 a ,
"
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,ct , ,\
? 1
--___ .d�M
Revaew of Exastmg Schemes
(
,
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7 r- - - -... - - - -, >t1 1
\ 1---- . ,
r
1 Ll L2 \
COMBINÀ-J -
1 ~ 1 Tl
TIONAl 1 1
PI SRL , NETWORK 1- - - - - - - .. 1'
" X2 ] . N , ,
\ , 'Ll L2 1 . 0 Jr- Y?' 1 )i , ,
\ " 1 .
• 1 .. , . , r . 1
\ ,
.'
1 ,ri , , \ ' ,J '\ . , l' , . ,
., 1 \ 1
0
0 0 1
>%l "
1
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L2 1 : Ll 10- Y.-
" 0 N . \ , \
Cl , -
"
A \ . 1 1 :', ri 0
IN 1
. . SCAN "
0
. .:. , ."
" B >
SCAN OUT:
, ,
/
\,
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. Fig. 2.12 LSS,i) Double-Latch Design
27
.,.
--_. ~-~ "!; ...... ~--~ -- -- ---~'''''f)-'_'''--'--''''''''<'---~---''''-:-------'----''--'-''''''''''''''-=::!· (JO
St' ,.
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t .' ~ 1 1
f
1 "
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, . ~-,
;;'1< 1
l' , i f
·1 t. ' f
. \
---- --- .... =-----
. .,
Review 0/ Ex,stmg Schemes,
is then scanned out. Race-Iess behavior is therefore guaranteed in eiJmer mode 'of oper-
ation.
Fig. 2.13 shows an alternativ~ way of using SRLs in an LSSD environment, called
the 'Single-Latch' configuration[121. This configuration makes use of the LI output as
the system oûtput and avoids the potential race condition by partitioning the combina-
tional logic into two disjoint sets, denoted N land ;'\;2 in- fig. 2.15. System c10cks into , , 1
the NI and ,N2 SRLs are denoted Ct.,and C2 respectively. The outputs of the SRLs 1
associated wlth Ni become the secondary variable inputs to ~2, and vice versa. System
operation is controlled by the twoosystem clocks, Cl and C2, which operate in such
. a~ay a~ to e~~/ure that onlv one clock is active (high) at any one time, i.e .• Cl and " -~
C2 aÎ'e=not(.overiapping. In this way potential race conditions are avoided: The name
'single-latch' cornes from the fact"that only one latch is used in the system path at,a,
t1me.
Th'e essential difference between the' double-lat.ch and single-latch configuration
lieS""--i1r the speed with '~hich the Circuit primary ~utputs can change as a result of
primary ~nput and c10ck changes. The double-Iatch system requires two independent'
and non-overlapping c\ocks (C and B) to change before signal-value changes can be
propagated through the L land L2 Idtches and hence through the corn binational circuit
N to produce ~ stable pnmary output value. 1 The single-latch configuratIOn on the
• o~her hand only requires the appropriate smgle doçk to change (Cl or C2) to cause
propagation,through the LI latch hefore ~e appropriate combinational ctrcuit outputs (
(NI or N2 respectively) !.=an stabilize. In both cases. the fastest operating speed is . , o
governed by the propagation delay of the combinational logic circuit. If this delay is
denoted by N-delay(max), then the maximum dock rate on the system dock, C for
double-latch and Cl or C2 for single-latch, is given by:
28
\
cl'
"
, ' '
1
! \
.
Revlew of EXlstzng Schemes
L >PO(1) r
-;
Ll L...-
N(1) L2 Il
\ w
PI (1) 1 .. , 1
1 .
.., 1
;t :\ Cl 1
1
-~POI2) , ~ Ll - '--
L2 N(2) -
, \
,~ 1 ,
2) -.. Pl( 1
•
C2
A \
B , SOI
1 Fig. 2.13 Single-Latch LSSD Configuration
,29
r
1 l,
1 1 1
Y(1} 6
, , ,
~
.
.
- --- --,- p--_ .... ~".,~-,---~._"' ...... ~ - ",,,-- .,.-.,,-----_ ....
1 P
-
sc ~ -,
'''1 Y
Q
J J" l'
(2
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l'
li
.
~
,~
,
..
\ .
\
( t
Revlew 0/ Existmg Schemes
C(max) < ~-delay(max)
A disadvantage of the Single-Latch configuration based on the SRL of Fig. 2,13 is
that the L2 lateh has no role to play in system operation, In that sense, the L2 latches >;
are redundant and represent a high overhead for testability. A 'variation to LSSD that
solves the above problem IS presented by Dasgupta etc whlch 15 called L2* Scheme 117l.
This séction descnbes the L2* Scheme and the other variatIons of Single-Latch LSSD
approach.
2.4.1 ,Saluja's Scheme
..., A variation of the SRL \'vas reported by Saluja in 1982[281. Fig. 2.14 shows this
. \
latch called a polarity-hold Parallel and Shift-Register Latch (PSRL). The PSRL has /
two mod~s of oper'ation as shown in Fig. 2.15 and are as follGlws:
1. Mode l (Normal mode of operation): lJnder this mode the two latches LI and .. D
L2 work in parallel an,d accept excitatIOn signal D when the. system c/ock C is at logie
1. In this mode A and B are held at loglc O. This mode IS shown syrnbolically in fig.
2.15(a).
\
2. Mode 2 (Test mode of operation): Under this mode the latches work as shift "
register with IN as input 'and Q2 oùtput of L2 as out~ut (fig. 2.15(b}).
It is interestmg to note that in mode l, the uricornplemented and the complemented
outputs are obtained from two different latches and in mode 2, the PSRL latch behaves
30
, "
'\ " .
\
~
, . ---\
- - ... ~ .. ...- -~"t". ........ _._. ______ "lIi!l'..-w--- ... sws J'~~", __ ... _._. ______________ ....... _ ....... _,. .. _
\
Review of EXlstmg Schemes
~
, L,
. \
L2 ,0('"
/
B ,
, .
Fig. 2.14 Polarity-Hold PSRL
1
\
( .. 31
\
Et > •• '. T ! ... ,,,,,a Il10 .. ___ .. ~ ~"
(
., Rev.ew of EXlsïmg Schemes
D
SCAN IN
A
B
,
"
L,
L, .---
c-'---
L2
Fig. ".z.15(a) Normal Mode
\ ., ,
-. 1--
L2 ,
,
"/
Fig. 2.15(b)' Test Mode •
32
Q
Q
\
SCAN OUT
, '
, __ ~ ~ ."..............-_._ .. ___ ,...-.-,.""!!~~_ .. r_1"I __ 9Ia_. __ ... __ , ---.. -· _____________ f __ ";":'""e--- __
1
(' ,
.. ~J
(
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(
Rev1.ew of EXlstzng Schemes
exactly the same as SRL. Ali the PSRLs are ,înterconnected to form a shift register
similar to LSSD approach. /
, "
1
2.4.2 L2* Scheme /
Fig. 2.16 shows a variation of LSSD proposed by Dasgupta et al [29j. The difference
between the L2 of fig. 2.7 and the L2* of fig. 2.16 is that the L2* latch has two
independent data ports. The first port IS fed by the related LI latch and clocked by
shift dock B. This allows the L2 t latch to perform its traditional role as the slave latch
in the shlft reglster path The second data port serve,> as an tndep(>ndent '3ystem dat.a
port c\ocked hy system dock C < 1,0 permIt different system data to be stored in the L2'
latch durmg S\ ~teIIl operat.lon. . .
From the designer's standpoint, the best feature of the L2* latch is that it requires'
no new design rules. However, one old rule needs greater attention now: , System outputs to a network can be taken from either the LI or L2 latch of an
SRL but not from both.
This rule IS necessary to ensure that whatever test pattern IS generated can actually
be applied. If both latches of SRLs feed cornrnon logic, a situation cou Id anse in which
it might ILot be possible to shift in the required pattern. Fig. 2.17 shows one example.
The LI latches of two successive SRLs in the shift register path are required to have a ...
value of 1, while the L2 latch in between must have th'e opposite value. This pattern
cannot be shifted in
'Jesting of LSSD networks using the L2'" latch. proceeds as f611ows:
33
Revaew of EXIstmg Schemes
(
c •
\
A
l'
B
c* D~
\
..
\
Fig. 2.16 SRL with L2* Latch
34
, . L __
"-~-C''>1Ile;<A_ » .... ~_, __ u_" --- ------------_= __ a_z OWI' _-,'
( !
\
Revtew of Existing Schemes
\ \
\
l
o
Fig. 2.17 Untestable Configuration
THIS 0 CANNOT B~ SHIFTED IN
\ l . 1 , t
,- ~
...
i ~ \ ~
Review of EXlsting Schemes
Step 1: Set up the "mput state ta the combinational lbgic by loading the shift registers and
applmg the desired values at primary inputs.
Step 2: Pulse the proper system clock ta capture the result of the test in the LI latches of
SRLs at the outputs of the logic network.
Step 3: Pulse shlft clock B to transfer the test values ta the L2 latches of the SRLs.
Step 4: Unloa,-~he shift registers by repeatmg the operatio'ns 'Pulse Shift c10ck A, pulse )
shift clock B' and measuring the 'scan-out' primary output.
Step.5: Repeat steps 2, and 4 ,this tlme p~llsing the system clock feeding the L2· latch.
/
We .will nô~\discuss the important question of how much the LSSD and its varta-
tions cost m logie gates and operating speed with level-sensitIve desIgn. The polarity-
ho Id latches In the shift registers are logieally two to three times as complex as simple
latches. The logie gate overheàd for irnplementmg the level-sensitive design ranges be-
tween 4 % to 20% Four additi~al Input/Output pins are requlred for control:;ng the
shift operation This is a senous problem. sinee routing of three addition al signaIs may
add signJfîc~ntly to the area of the chlP' External asynchronou~ iAput signaIs must
not change more than once every clock cycle. This constraint is required so that level-
sensitIve logl\ 5ubsystems will result. Ali timing within the subsystern is controlled by
externally generated clock signais. The overall performance of the ~ubsystem will be
degraded by the clocking requirement The increased clock delay 15 due to the connec-
tlOn of the output of flip-flop to the scan input of the next Hip-flop in the ~can register
chain. This results m extra capacitive loading.
The mam drawbael} of the Sean based designs, ln particular LSSD is large test-1
application tlme The testing strategy for these Scan desIgns requires t he circuit to
cycle from 'Scan' mode to ':\'ormal" mode and back agam as each test lS loaded and
36
...
(
\
Revlt!w of Existing Schemes
, 1
'1 -
applied. The seriai nature 'of the "Scan-In, Scan-Out' mechanism can create long test-
application tlmes. For LSSD. Goel'9] has projected that the total test-application time "
is proportional to G2 where G is the gate count in excess of 100,000 , the total test-
application tlme becomes extremely large.
In the L2 t scheme, the L2 latch is fully used even in the normal operation. This
~tilization of the L2 latch substantially d-ecreases the are a overhead attributed to SRL
'~mplementations. The total number of non-overlapping clocks which are required for
-
the proper functioning of the system using L2'" are same as in systems usmg SRLs. The
overall system performance is not affected. Thus systems using L2* or SRLs can run at
the same speed.
The de'ilgn of latches III Saluja's scheme result in a reduction of effort in test pattern \
generatlOn and provlde a better fault coverage. As mentioned earher, ail Y inpvts to
the' comblllatlOnal logic are obtained from QI outputs -of PSRLs and Q2 outputs of .
PSRL~. For test generation purpose, QI and Q2 are consîdered as mdependent variables. " 0
This pro cess will increase the number of controllable inputs to the combinationallogic.
One of the time consuming operation in D-algorithmII5! is consistency operation. By .c
conSloertng uncomplemen ted ana cornplemented variables as .Illdependent varIables, less
inconslstenCIes result. Also, independence of Y from f- helps sensitize many paths.
There IS a little difference between the total number of gates used in a PSRL[28' and a
SRL. Two additlonal NA~D gates are used in PSRL. However. while using SRLs, sorne
of the L2 latches can be used for other system latches where as in design's using PSRL.
·this cannot be possible. 'As the two sublatches in PSRLs work m parallel the overalJ
system performance is not effetted._ Thus systems using SRLs or PSRLs can run at the
same speed.
37
.. ---,. 'l''~ ... _
"
\
1
(i
1
Rev.ew of EXlstmg Schemes
To summarize, the rriain advantage of the LSSD technique~_ beeause of stan ca-
pability, reduees the sequential test generation problem to a combmationai one and
enables 10~Ical partItion mg of the circuit. Another advantage of the LSS D is that ae
testing as weil as test generation and fault simulation are greatly simplified. smee the
correct operatIon of the [ogie circuit is nearly independent of the ac eharacteristics and
also the polarity-hold latc h is free of hazards and race conditions.
\
38
D
1/ î
\ , (
-,---
Proposed Scheme
3. Proposed' Scheme .
As discussed before, the lèvel-sensitive design introduced by Eichelberger and \
Williams ~ 131 has the drawback that the basic memory °element. the shift register la.tch
(SRL) must have two latches Li and L2, which are connected in master-slave configu
ration. For most of the designs, the master latch Li is sufficient to achieve the required
system function. The functionally idle L2 latch is useful only for sh lftlllg and therefore.
is an overhead for testability in Single-Latch designs A vanation to LSSD that solves
the above probtem is presented by Dasgupta etc '291. This design has the disadvantage
that four dock signais has to be routed ove!." the whole chip Routlng of more than one
dock can Introduce major tayout and timing pr<)btems '3inC(~ routlng of 'l('vpral clocb
c~n introduce tlme skews between the c/ock signais. Hence. [rom d layout point of view
, this sc he me seems to be havmg considerable area overhead and also three additional
input pins are required.
Another important point that should be noted is that the basic latch structure
presented by Dasgupta etc 291 is not completely'hazard-free. To illustrate this point,
. consider the basic latch structure of the SRL usmg L2' as shown in fig 3.1. Refering
to fig 3 1. if we assume that the state of node 'p' changes that of node 'r' in response
to a change of dock C From 1 to O. then steady-state hazard exists as shown in fig. :;.2.
The existence of steady-state hazard can be defined:30j as: If the ctrcuit fails only in
that, immediately after certam input changes, the system enters the wrong stable state, (
then steady-state hazard results. In fig, 3.2, it is assumed that the zero value of 'Y' IS ,:.'
fed bac,k rapidly enough to hold the state node 'r' at value 1.
In fig. ~ 3.3, il is assumed that the state of node or' responds more 'quickty to a
change of input C From 0 to l than does node 'p'. If we consider only gate detays.
39
~ .. _~ _ a::::s~2LO_
0 '\ ' .. ' ,"~ ,
u
., -Proposed Schen1e
. {
o' j j l l ,
" l " «' , 1 4
0 i CI
1 c 1
i f ~
q y , 1
A 1
,
Fig. 3.1 Latch, Structure in L2* Scheme
40
, l'
,l-
. , 1 .
Proposed Scheme . ),
,
\- • - - - - - - - -- ~
C - - - -. , -
- - - -,
~p - - - - - - - ,- - - -........ .
- . - - .... , - - . ,
0
, ,
r - - - ,- - - - - - -. !
~ ,~r.;;;;.· -"
Y - - - - - - - - - - ;/ STEADY - STATE " HAZARD
/'
..
Fig. 3.2" Steady-State Hazard Conditipn
, 41 • \
----------~-----
;. ..
- ":'1 > ,
. ,
0 h
.'
1
- -0
1, ,
- -.0 ,
, r ,- "1 1
0 .
-
\
,.
1
"
... ~ .. ) '\ (
" 0
, . o '.
Proposed Scheme.
-
1
"
C - -- -
p
. " "
r ; - _.
\
'.\y - -\
, .. J_ . ':.:(~-~(-",
\
0 . , -
"'-. .
1 - - - - ,
" , ~
- - .r~ - - - - - - - -0 .1 1 '0 <J, . . .
. -1 - - - - - - - - - -, , . il
r. , ,
- , - - - 0 1
~.
- - - - 1 . 1 . -
- - - - - . -'0 - - - -' -1 - -.
-/-- - - - - . -0 - - - - -•
TRANSIENT ,
HAZARD
~t
-----Fig. 3.3 Transient Hazard Condition
(,,'
Il .. _____ ...-~~ <" ... ,_.,...... __ ._, .... ':w-... __ .., ___ .. _ ............. ..,.*"""'""'!p-"'--+ ... '""!_,.~~ .... e" ..... _'_"'!'p ... 4;_ .... ""._-""', ... - ........ -:""-----~ ... ,,..-<.. .... l·--,,-....-~ .. =r~ .... ·-....:. ._ ... ~""""T'"T-<."'? __
1 1
j ~'
r . \ 1 ,
, , ~
~
~
'-
f·
Proposed Scheme
then this p05sibilityappears unlikely since two gates are involved for node 'r' and orily
one for node 'p'. A transrent hazard results. The existence of transient hazara can be
"defined[30j as: If the circuit fails only in that, immediately afte~ certain input changes.
pairs of false output c~anges occasionally oceur on sorne output leads, then transient
hazards are said to exist.
It is not possible, however, tô hé).ve both types of hazards in a particular circuit
since a given distribution of time delay will result in one form of hazaJd but not both as
an inspection of fig. 3.2 and fig. 3,3 shows. If sufficient tlmely delay is inserted in the \ ~
feedback loop, then the steady-state hazard can be eliminated since the value of node Ir'
will beeome equal to Q before the output can be fed back to'maintam it at the value L. ,',
Another' way of eliminating the staJic hazards is by using redundant gates. Then 'care . .
should be taken to determine that the transitions for ,\hich redundant terms would be
added can actually occur.
, . A hazard-free polarity.!hold SRL using LZ* can be designed wit'h a structu're similar
to that of the original SRL proposed by Eichelberger and Williams and i,s show~ in fig,
1 3.4. It consists of two latches, LI and L2l<. Âs long as the shift signaIs A and B are
both 0, the "'Li and L2 t latches operate exactly like a polarity-hold latch. Terminal [
is the input to the shtft register. and L2 is the output W hen the Idtch is operatlIlg
as a shift register, data from the preceding stage are gated into the polari tv-hold Ia:tch
LI via l, by a cha,nge of the A shift signal to 1. After A has changed back to 0, the E}
shift signal gates the data in the latch LI into the output latch connected to the output
, terminal L2. Clearly, A and 8 çan never be l at the same time if the shift reglsters are ~. ~
to operate properly. When the latch is operating in the normal mode. data are gated
into the polarity-hold latch LI via D. by a change of the C clock signal to 1. :\.fter C 1
~3
\
! 1 ...
, " t • \, f
t
/
(
Proposed Scheme
\
-c
lA
ltl':4?--"'" ---______
----------- \
Fig. 3.4 Hazard-Free SRL using L2*
\
)
Proposed'Schen1e
has changed back to 0, the C ~ dock signal gates the system data int'o the L21< latch via
D*.
As discussed above, the L2* de'sign has the disadvantage that four c10ck signais
have to be routed over the whole chip. This is important ·in chip layouts. since routing
of several docks can introduce time skews between the dock slgndols In an attempt to
solve the routing 'and timing problems, a modification of the L2 r latch will be dlscussed
in this sectIOn. This modIfication is shown in fig. 3.5(( a) and (b)). We shall cal! this
MSRL (Modified Shift Register Latch). A '\1ode-Switch' Input selects the normal or •
scan shift mode (Mode switch = l for normal mode). The same ~ystem clocks C and
C* are used in both scan and normal modes. In the normal operation, inputs C and C'
are used as system clocks, while the input MS is helcl 'hlgh' For the scan operation,
the two docks C and C* are used as scan docks, while the mode-swltch '\[S is held"low'
to detach the normal data lines 0 and D'. Hence, in thls scheme two clock signais and
a mode-switch have to be routed over the whole chip. Whereas in the L2* sçheme, tw0c! " system docks C and C*, and two scan docks A and B need to be routed.
1 ~ l,
An important characteristic of this latch (MSRL) is that no race or hazard con-. '
ditions are present during normal operatIon. In ottler words, the latch can be used as
a levet-sensitive latch. As shown in fig. :~ S((a) and (b)), the \-lSRL consists of two
latches LI and L2. Latch L1. using clo~k C, gates sy5tem data 'n' Slmt/arly, L2 operates
,r independently of Ll, using D ~ and C·. When the SRL is operating as a snift register, , - . the mode~swltch (MS) -is -reset to zero, mput from SI is gated into latch LI when the
.,. shift signal C cnanges from 0 to 1. When.latch LI Îs stable and C Îs changing b,ack to
'" 0, the C* shift signal gaiès the LI data mto L2 by ch';lnging from 0 to 1. The two-phase ~
shifting operation is a characteristlc of LSSD. It is important ta p{operly control the
fout mg delays of C and C* signaIs to preserve thelr nonoverlapping nature. An overlap
of these l oC?
l -45
\
\ \
Proposed Schen1e
/
0 "
C L, SI MS' r
\, --
c* 0--
-o,c
-... ,-- ~-....:..:..
/
"
-
.
Fig. 3.5(a)
\
0
\
1
L2
~ Proposed Scheme (MSRL)
\ 46
,
___ A_.-...... __ ... ,'f.'Ot ..... -· ... n------...... ---------..::
" 'r
/ ;
~
~ , -1 1-
" ~ ~
" ;
Ll , ~ , {
l
"
/
1
,
,
, -----_....,.jl~'-....
Proposed Scheme
c*
~D*
(
r )
\
\
Fig. 3.5(b) Proposed Scheme (MSRL)
,
\ 47
._._--------_ .. _ ...... _-----_-.-. .--~ -----
r,' ';
, y
, ,
(
Proposed Scheme
\ signaIs (i.e., C and C +: being high simultaneously) can cause incorrect operation. The
truth table(shown m Fig. 3 6(a)) and the suggested waveforms for ~fS, C and C' are
illustrated in fig. 3.6(b).
Thus, designing with MSRL would result in saving oPme input pm and t~e routmg
which would ptherwise have to connect this pin to aIl flip-ftop, thus decrea5lng the area.
It is weil recognized that ln VLSI cIrcuits, long routing path~ are more {''(pensive in ,
terms of chip area than a few devices which are locally connected.
A logic subsystem using MSRL will have the structure shown m fig :3.7 As shown
in the figure, the two dock signaIs partition the logic subsystem into two parts. each
c'omposed of a combmational network and a set of MSRLs. E:ach of the cornbinatlOnal
networks, NI and ~2, is a multIple-output logIc network Pl and P2 are primary lllputs
to the network, and ZI and Z2 are for primary outputs. C and C' are the two s!stern
dock signaIs. The operation of the subsystem is controlled by the dock signaIs. At C
tim~\C* is zero and the. inputs and outputs of NI ~re stable (assuming that the external
inputs Pl are also stable). The dock signal C is then allowed to pass ta the \fSRL 1
system clock input. The system clock C may be gated by sigr,tals from network ~ 1 such
that C reache!lthe MSRL if and anly if the gate is active. Thus some of the latches may
change at C time. These signal changes immedlately propagate through network :\"2
As soon as C is changed back to 0 and aIl LI signais have finished propagatlOg, the next
dock signal, C* may occur. For correct opera'tion of the subsystem. ail that is needed is \
for the dock signais to be long ~nough to 'allow ail latch changes to ~nish propagating.
This structure meets- the requirements for level~sensitive operàtion and ensures that '. \ , \
there is little or no dependence on ac circuit parameters. [t'or proper operation of the
logic subsystem, aIl that is needed is that the delay through the éombinatlonal networks
~'l and N2 be less than the cortesponding time between the c10ck signais.
-t8
- ...... - "·--""'--~~1-!'f~t. ~ ..... ~ 'fiô4kj""IltI~lIil'~.r. , .a.; &Clqll,_"'" .....
<" 0
f -
-l,
\
1
( 1
Proposed Scheme
MS
1 1
1 1
0,
0
0
0
. .. '.
C
0 T
0 l
0 1
0
1
< ... ''i'
,.1 r' .~ .. 'il
~ 0
0
l l
0 0
1
1
-
i
\' ~' »,
NONE ACTIVE LOAD Ll WITH SYS. DATA D NORMAL ~
LOAD L2 WITH SYS. DATA cf MODE NOT ALLOWED
NONE ACTIVE SCAN LOAD L, WITH SCAN DATA SI MODE
LOAD L2 WITH, J SCAN DATA FROM Ll 1
NOT A Lt.OWED J
,
~ig. 3.6(a) Truth Table for MSRL
• 1
-t9
{
(, '.
Proposed Scheme
1 MS
\ \
c
c*
MS
C
'C* r,
NORMAL MODE ~
1- - - -r-------_ -_ _ 1- - - -. o. L----- -- -- . 1 -
1
- - - - - -"
0 - -
1 - .' - - ...... - - - - - ,------,
0-------'[ SCAN MODE~
1
1 a-
l- - - -
0 1
/ /
1- - - -
0 \ 1
- - - -4 1
- '----. -
\ Fig. 3.6(b) Waveforms for MSRL
.50
\.
, , ,
J
\ t , , ~
~ J ,
.. ! • ~I
Pro~sed Scherne o
w
Z, " ~ , -
Y27 L, ,'cl, \ 1
1 1 \ N, 1 1
J>-
Pl 1 - 1
, , . 1 1 , \ , 1 "
t' , 1
1 1Y1N L, • " -,
C
..
- Z2 ~ , -
L2 ,
Y, 121 1 ......
1 N2 1
r J 1-
P2 1 1 ,
1 u
1 1 ~ 1
1 ~ L2 -
,
C*' - • . <--.-
MS . SCAN IN SCAN OUT'
Fig: 3.1 Single-Latch Structure using MSRL
51
. (
. '
(.
Proposed Scheme
3.1 Testing The MSRL
< [n general, in sequential circuits, the future state of the stored-state tlevices depends , , .
on both the prjmary mputs a nif the current' recorded state of the stored-state devices / , ,
thernselves. It is this dependency of the future state on the present state that causes
ail the problems III test generation. The pri~ary Inputs are the only lnplIlS over which . _~~
the test programmer has direct control. Sirndarly, the primary outputs are the only/
outputs that 'can be observed diCcctly, Control and observation of the storcd-stt '
devices is indirect through the combinational section of the circuIt. The problern is
- which section do we test first given that nelther section is dlrectly control/able or
observable and that the sections are mutuell/)' dependent on t'ach ot'hf'f for correcr.
operation The scan-design technique provides a solution to this problem by reduClng
the complexity of th~ cirCUit structure. The testing strategy for the .\IS RJL and ail the
scan methods described in chapter 2 is now as follows. v
STEP 1: Select the scan mode, i.e .. alllatches are reconfigured into a shift reglster. Test
the status and operation of each latch using the Scan In, L2 output and system ,(
dock facihties. A suitable test for the shift register IS as follows:
...... ----\ ~
(a) Shift test. [n this test, the ~equence OUllOOl VIS shlfted t hrough the reglster
/' , This sequence exercises each latch thro1,l'gh ail combinatlons ot present state
1 / ' and future state. J
STEP 2: Determine a set of tests for the two combinationallogic black_s. assuming
\
(a)
(b)
total ~ontrol of ail inputs (primary and from the latches): \ '
direct observability of ail outputs (primary' and to the latches). ~ ~
STEP 3: Apply each test m the following way: Î
\ 52 \
t
i
l ~ .... ..,~--_. ____ ~ • ..., ...... i. _,. -
(
\
\
(
----,,---
Proposed Scheme
(a) Select scan mode. Preload the latches with test i,nput values and establish
\ additional test input values on the primary Inputs.
(b) Select normal mode. The steady-state output response of one combinational
logic block can now be c10cked into the corresponding lat.ch (LI or L2).
(c) Return to scan mode and dock out the contents of the latche~. Compare these
values, plus the values directly observable on the primary outputs, with the 'Î
e~pected fault .. 'free response.
STEP 4: Repeat step 3 for the other combinationallogic block.
The 'divide-and-conquer' phdosophy of the scan design approach can now be seen
more clearly. Rather then test the circuit as a smgle entity, the dddltion of the .;;Idt
path allows each major segment to be tested ... eparately and in d procedural manner.
Furthermore, if we assume a standard test for the latches (Step 1 above), the only .test \
generation probl~m is to g~nerate 'tests for the combi~ational segment. This problem
has been weil researched and a variety of programmable procedures exist ~ 8 i.
, \
. 3.2 Design Rules
1
A sp~cific set of design rules will be described below, that will result in a design
suitable for sc~n Implementation with MSRL. The rules are simple to follow and can be
chec~ed automatically by a CAD too\. These rules result in a hazard-free and rac..e-free
sequential design and still provide considerable fl~xibility to the designer These rules
are designed to preserve the level-sensitive pro pert y and the scan property.
~: Ail internai memory eiem:~ts must be implemented in MSR~~type flip-flop.
.=)3
\ o
, "
t , ~ j
l t
"l' 1
"
''j ~~ j
• 't> 1~ • -.;:...,......,...r.."r_ ......... ~.r~" r' - - --~""""~"",~~~~~,,,,,,, _; il,..' - __ ., ... , ....... , ... "'* ... t. ____ ._ ... _. ___ ... ..,..._~, _"_~ ... ~
•
. t t
1
(" -
-.
1
Propost!d Scheme
Rule 2: MSRLs are controlled by two non-overlapping clocks such that :
~"
(a) the LI or L2 output of YISRL(l) can be used to gate a clock C to!produce a '"
gated dock, C(G). C(G)\an then be used to clock another latch. YISRL(2).
provided MSRL(l) is not being clocked by C:
(h) subject to this restriction. the outputs of ~[SRL(l) may feed the data inputs -
of MSRL(2).
11
Rule 3: It must be possible to identify a, set of MSRL that are directly controllable.
This means that:
(a) aIl dock inputs can he held inactive independently; •• (h) any single dock can be made active while the others are 'maintained in t.heif
inactive state.
Rule 4: Clock primary inputs c:tÏn only be connecte-d to MSRL dock inputs. They \
cannat be connected to MSRL data inputs, eithf!r directly or through the
combinational logic èircuit.
Rule 5: System outputs to a network can be taken from elther the LI or L2 latch of 0
l' an MSRL network but not from both.
This rule needs greater attention for a single-latch design. Since in a single-latch
design both the latches are used for system function" extra care should be taken to
ensure that bath LI and L2 -outputs of the MSRL do not feed common loglc. This also
enspres that no hazards or races occur in the circuit. Rules 1-5 constitute a check for
the property of level sensitivity. Rules 6-8 are for the scan mode verification.
)
/ _ •• - ........ ~~ .< -_ ..... ......-.... ... ..,...".. ...... T,·_c..,... ... <-~-JIIn,.WI. tA'.,Q4.,d'-~~~' __ "".~\"I_('I_~_""'_A"""_' ___________ .:..-. __ ....... _.....,..,.,... .... = ..,.c -"_,"""'.
r :1)J. .... ~ " , '{ ;,.
... ~ \-..
.' ~
t.
, t o~
1
, , . ,
,
1 .
t
_._--
\
.. r .
, '-
Proposed Scheme , '.
Rule 6: AIl :VISRLs are permanently co~nected to form a shift register with, a sca~-In
primary input, scan-out primary output and accessible control clocks.
Rule 7: There must exist a circuit configur~tion state, .directly controllable from the'
primary inputs called the 'scan" state. One primary mput pin must be allocated
for specifying the mode (scan oç normél-I mo~e).
Rule 8: When the mode specification line is in scan mode then the output of a flip-fiop -, ,
or scan-out primary output should be a \unction of only the pre~eqJf~ flip-flop \ " ~ ~ /'"
output or scan-in primary input of the shift register.
3.3 Area And Performance Ove9Iead
It i~ evident that' ail the advantages which apply to, LSS ~ re also 'applicable to
designs using MSRL. SysteI11 performance ispot dependent'on hard-to-control'ac circuit
parameters such as rise time, fall time, or minimum delay. Test generation and testing , ' -
are simplified to the weil understood method of combinatiof.lal logic network te'5tmg.
,/
As pointed out earlier, the speed of the system is not degraded"smce the ad'clttional ~ /
. gates added to thélatch are not m }he data path. The area ov{'rhf'dd for the ~can deSIgn
depends very m~ch on the circuIt str~eture. ~ther factor~ are "the probortion of fiip-,
flops of the whole circuit and their distribution over the chip. As ,>uggested earlier. the , ,
proposed scheme reduces the required routing area in eomparison to the L2 ~ sdieme, at"'\
the expense of sorne additional logie (1 inverter) in each fiip-fiop. In the polycell layont
of the chip, the area is divided bètween the cell rows and the routmg channels as sho~~'n
,/ in fig. 3.8. An estimate of are a overhead is given below since a ehip design u::,ing ~lSRL
has not been completed.
[
C)
•
__ .... ...-_~""". ___ < .... __ -,,_ ...... __ ............ ,_p ... 1 ________ --'---..;.,1. ~
, 1
\
()
\ l'.
Proposed ~cheme / ~
----~~ - ~ /
,/ \ (
STANDARD CELL'
\
... ..
- 't<:..
\ "
Fig. 3.8 '\>
,.
J ..
\ ' \
,'" - ~,~ .. ---, ~-----'
- , ---~--
,<
, .
" ~ROUTING - CHANNELS
'\
\
Polyeell Design Layout .
1.
i
1 -i ~ t f
! 1 i
1 ,
-(
\
\
Proposed Scheme <.
- - ---~I
Theoretical Calculation of Area Overhead:
The polycell layout style consists of standard eells plaeed on grids in the rows of
the layout as shown in fig. 3.9. The polycells contain simple boolean or memory célls.
One dimension (height) of the cells is fixed to allow for an arrangement in rows. The
width'of the polycells varies. The ro~s of polycell are separateJ by routing sp'ace.Î1le
routing space consists of routing cha"nnels. Routing is mainly dDne in channels between
the adjacent rows of cells. f. !
The implementation of scan design inereases the area of the chip in two waysi3ti.
First, the width of the scan ftip-ftop is larger than th~t of ordinary Hip-flop (height of . . ' J -
.both ftip-ftops remain the same). Th~ lar~ flip-ftop sizë is reftected by rhe increase in ' -[/, '
width of polycell row. Seeondly, the scan design requires at least t'wo drfditional routing
channels per pair of polyeell rows. One of these channels ·is for mode specification line
and' the other channel is for scan data line. This is shown in Fig. :~.lO.
The increase in area, due to larger scan ftip-Hops, is dependent on the fraction of
chip area that is oecupied by the flip-ftops. The total increase III area can be theoretically
calculated as follows:
Let
'c' be the number of eombinational ce Ils per row )
'S~ be the number of sequential cells per row
'N' be the number of p·olycell rows
'nt' be the number of control lines per polycell<row witha,ut scan
'nz' be the number of control lines per polyeell row with scan 1
\
'h' be the heigh~ of the pre-sca~ cell
57
Proposed Scheme
• r
0_
lC ;- S) CELLo/ROW
\ J 1 1 1 1 1 1 1 1 1 1 IL
f 1 1 1 / 1 1 / 1 -1 1 ..L. ~~
\/ N ROWS "', ~-
1 1 l 1 1 1 1 / 1 1 / /11...i. ,
1/ 1 -1 1 -1 1 1 1 -1 1.L
1 1 1 1 fIl 1 1 J 111.L
-' -'
<Fig. 3.9 Polycell Design Layout
-----... _-~- ,
/'
j \ " , \
()
1 l ~ l j ~ ~
-~ ~ ; ~
.~ ~ -"
.~
~ ... -1 -\ ~ 1: i
Proposed Scheme
(
\
"
./
\ \
\ \
\ f •
\
Fig. 3.10 Layout of Scan 6rcuit
\
\
1 ___ - __ "~ 1 "~""T_~""_""".<>,,,,,,,_~~~~ , ;;ee'RiiiC...-wt/t#&~~_, .... __ a _____ "'~""J""''''' ___ ''''' ___ _
.\
\
Proposed Scheme
\..
,- 'w' be the~ width of the pre-scafil cell
'\8' be the helght of the_~can cel!
'Wa" be the width of the scan cell
'kh' be the height of each routing track for sorne 0 < k < l'
Ass~rnPtions made
, \ \
,--- -
1. AlI standard cells ?n the chip are of same héÎ'ght and width (for simplic5ty)
2. Ail standard cells are square 1 e h = w. Also, hejght of pre-scan FF and scan FF , )
remams same. h = h3
Total chtp area wlthout .<;can ~ ..t l
Area of the scan register' ceH,
~~ .......
~\~
"
,.. -i)
h( -w) 3
'-
= Area of polyceLl rows -r Are a of routmg chanTlrels
= Nh(C + S)w + Nn1kh(C S)w
= JWt2fl . + nlkl[C + Si
'5 h 2 [' - • 1 .) ,J
') [ncrea . .,e ln wldth - 18 due to 8can lOyle; --
:~ ~"
Chip area usmg !vIS RL '= A2
\
1
,Vh2C + ~Nh2S + .Vn2khl.C 3
5 S'! 1 T - 1 ., , d
60
\...
\
~~----~~ - ....... ;:ç:;::1I;' --=-------.. -.... , ---------
,.
(
\
\
, . '
,
Proposed Scheme
(,42 - At) Area overhead =
Al Nh 2 :C
l + ~S:[1 T n2 k ! - Nh 2f 1 ntk,[C S~ l
Nh 2 [1 -+- ntki;C -+- S1
(C + ~S)(1 + n2 k ) - (1 - ntk)(C ~ S) (1 + n1k)(C - S)
[( 1 + ~f.)(l --1- n2 k )) - (1 - n[k)(l - f-) 0'
(1 --1- n~k)(l T f)
For de,szgns usmg l\1 S RL, n2 = ni - 2"
(ni -+- 2)kJ: - l(1 +- n 1k)(1 T ~)I
(L - ntk)(l + ~)
=
Let, ni = 30 (the no. of routmg lracks- per polycell)
k = 0.1 (hetght of eac~ routmg track tS 1/10 of hezght of bastc cell)
S
C O.S(Jractwn of sequentzal'cells 6it the ChIP)
Therefore, (A2.--;-Ad 0.2 + ~ ~0.5 -r % ~30*0,1.j:O.S...( l~) -0.1 ~0.5
= Ai (1 + 30" 0.1)(1 + 0.5)
28.33 %
Table 3.1 and Table 3.2 show a comparison of area overhead fôr .\I[~RL and L2'
Scheme. From the two tables, it is c1early shown that designs using :\rSRLs wdl reduce ,
area overhead by 2 - 8% when compared to designs using L2* Scheme.
61 " 'a
. ,
i "
\
(
l
\
\ Proposed Scheme
\
3.4 Comparison With Other Schemes \
As discussed earlier, designs using \1SRLs can reduce area overhead by 2 - 8 %
when, cornpared to designs using L2* scheme. With Saluja's Scheme, it is evident from
the logic diagrams for \1SRL and PSRL that there is little difference in the cost of - .
the two designs. However, while using PSRLs, the L2 latches cannot be used for other
system latches unless Q2 output is not to be uttllzed., ~\t hereas, ~o such restrictions
exist for designs using .\1SRLs. In Saluja's scheme, as pointed out earlier. a better test
coverage is possIble with reduced test generatlon effort. \Vhereas, practlcal systems
using MSRLs need to be investlgated to determlne fault coverage. The number of
additional .lnput/ output pins requlred for MSRL and PS RI, Mt'\':L for L:.! < ".herne 1
additional input pins are required: The speed of operation of the three systems is
identical. Table. 3.3 lists the important features 'Of \ISRL and other eXlsting systems.
, \
, Q 0
\
\
o
62
D
\
1 j l
1 li: 4
1 \j
...
. , ,
\
i"
: ( !
..
--,--
\ Proposed Scheme
<\
nl
-.)
"" 10 20 30 40
k ('
S
C
0.1
0.5
MSRL
')8 50i .j • /0
34.4% ')0 ?Oi " ..) • .J 10
28 ?ot . ..., / 0
27.2%
\ \
L2*
(}-f . .t6.6 /0
-tO.5% F'
.) -t .t ~ .J . • û
?1 -ot .J .::> /0
29.5%
1
Table 3.1 Comparison of Area Overhead fOT ylSRL and L2*
.'5 /'
Constant, . c nt varIes
\
~.,
"
\ if
1:" .~
,,,, .
\ .
\
~- ....... - -X--.;"~~""'Q III'WilI) ..... i!!I'--, .... fl.J:.:I"""~~~~~ .... ", ---"'""'"""'zn ... ",.,---n·-------.=--..--=_=-__ 1 ___ , _ "', ' 'i
· .
Proposed 8cheme (
.or v;,~
k a.1
nI - 30 -~
'u
s MSRL L2* c
0.10 11.3% l'P ·)G'-f ,j.... 0
0.20 16.5% 19.4% ~
0.30 21.1 % 24.0?Q 0.40 25.0% 27.9% 0.50 28.3% 31.5% 0.60 31.2% 34.3% 0.70 , 33.8% 37.0% ,
~\ 0.80 36.1% 39.3%
Table 3.2 Comparison of Are~ Overhead f~r MSRL an·d i;Q*
nI Constant, ~ Varies
\ \
(
64
.. J \ 1 ._--_ ... --
~ \
'-\
"
Proposed Scherne
Schemes
Characteristics
Latch Type
No. of Clock Lines
,
No. of Additional
Lines due to Scan :;
Race-Free
Hazard-Free
Level-Sensitive
\ \
Performance
(Clock Speed)
Design Rules
Other
ConstraÎnts
\
\
\ \
LSSD
Single
4 (C1.C2,A,8)
3 (SI,A,8)
Yes
Yes
Normal and
Scan Mode
No
Degradation
Comb. has to
be partitioned J
None
L2>1o Scheme Saluja's
Scheme
Single Single
4 (C,C'" ,A,B) 3 (C,A,B)
3 (SI,A,B) 3 (SI,A,B)
Yes Yes
No Yes
None ~ormal and
Scan Mode
No No
Degradation Degradation
Comb. has ,to Comb. has ta
\e partitioned be partitionè~
None L2 Output
can be only
~ \used for
Comp lernen ted
Value
Table 3.3 Comparison of ~SRL ~ith other Sc~emes
65
\
Proposed o
Scheme
.'
,
Single i .(.
"
2 (C"C*)
2 (SI, .vIS)
Yes
Yes
Normal and
Scan Mode
~ ~
Degradation
Comb. has to l {
o~
be partitioned -
~one 1,
)
',1*-
SimulatIOn '\ \
4. Simulation
\ ,4 There are rn~ design consider~tions relating to ,the design of a level-sensitive
polarity-hold shift register latch pair. High performance, low power dissipation, small
size and stability are sorne of the major requlrements for ,a good design . .'~s with any
design, there are engineering trade-offs whlch need to be taken info account to ensure \
a successful design, 1rhe technlcal details assoclated with the design of MSRL are ~
documented In thlS section.
4.1 CMOS Implementation
The MSRL cell IS implemented in :3tatic CMOS technology, The circuit was im-
plemented without transrOlssion gates. Since, the logical behavior and faults for the
transmission gates are generally not treated by existent Automatic Test Patteql Gen
erators[15, 16, 17). Furthermore, the failure modes of circUlts with such devices can
introduce non-'classic logic faultsiI9). '
Fig. 4.1 shows a MSRL irnplemented with 62 transistors. The LI and L2 latches
are constructed using 30 transistors each. MS= 1 feeds normal data and MS=O fee~
scan data to t'he LI latch. C= 1 actlvates th(' L Uatch and the L2 latch Îs activated by
C~=l. TIJe two t'ransistors which are encircled in the fig -l l represent the additional
overhead of the proposed design, The waveforms for this latch are thê sarne as shown
in fig. 3.6.
1 q
(
4.2 PhysicaI Design C,onsiderations
The basic latch pair is made of two similar latches. EaGh latch output utiliz~s an
buffer to elirni~ate latch:deg~datlon due to loading. ~he latdi. pair schematic design is
,/,/
66
1
!
\ "
~ -.:;-
~ , x..
L ') '.
,:\ <
l, .< ,
" î } 1
z , \
Q 0,
' Q
"~ ,
o~ /
z /
W r,-'"
~ w EC...J ~~
, . en ~ ~4- ),
uO )/!' .tJ -. V
-s.,2 IL. a
t •
0 )
'1 '
ï
./ .
J i i
"
'\ .. ...
* J Ih;: ~ • - !' J2l œil.
... ' ... '!l' ..... I .... ~··~r~~" ~ ..... , .... '1' ...... r"' ~., .... ~
, ....... l '
"-o.,.-w,,_1
,..
./' v j~ VPO -- - - - - - -
1
1 5"1., M
MS~
~-~ I j -a1 -
~ C 15 Q'
'-r--
.. Al ,
, . 0) :MS-i 00 ~ 1 3
6 - ~
.. y ~ ~~ 2 4
~
" 1
--1 5
=< '- ,
~ ___ ,.., _r..,._ _" ~ ~ ~ _ ... --""~ _ _~~~..I.~ .. ~.....-.-~~ .. ~t:11.,. .. ;.;;: V~lf;;t ('ol\:fJ~l~t'l·!:I~~''1'"; -r- ,-, >-~ .... ~;. .. _~..,~~'v~17
-'~ - -
,
,
,
r-- ~ 12 --
*
e
< .. ---
- -
'--
, - -
....
------.# '-
~ - -.
'"
'-
j -~
,-
- - - ---;:"'" - - ---
S~, M~ Al~-'-;- ~ ~. MS" D. C _ 16 ' ,
1.--...--
IB1
, r - -1
-
~ rs:- 151 L 7 9
,SI '-2. 1 SAME
"
~: AS Ll
~ • 't'-)
8 ._-- " 10
1 1'1 - ,
.. -
-1 11
~
,_.
\l'j ~.
~ .... .... C ;:$-
j
- - - - " 1
1 r-- 13
q
1
1
YI" IV
LI
1
L-- 14 1
-' - ~- - J
.
Y2 l2 ~ . -
"
~
FIG 4·2 SCHEMATfC OF U -:-l2 LATCH 'PAIR ~O.~ICE?
"
1
" "", f " af ~
t . ~
1
l t F i • i f r \ 1
~
il t r.-
i l ( 1
! / 1 " ,
i C t
t
l l ~ , ,
(
----
.1
!
.< ,"""-
. Simulation
shown in fig. 4.2: With respect to ,figure, the application of dock 'c' signal allows data
present on the data input of the LI to be Intched. The scan' input port is held inactive
during no.rmal op,eration and is utilized only during testing.
....
4.2.1 Lat~h Output Considerations
. Thr~ugh extensive circuit simulations, using SPICE[34j, perfot
ta the basic latch structure are identified while minimizin , \
selected for the latch implernenta~ion must provid
power level apd be insensitlve to process
isolation to the latch, thereby improving latch'set up time and vutput respon \
the buffer isolates the capacitive load, the power of the latch internai stages can be , .
redùced while the overall performance is irnpro~ed. The internai nodes of the latch
"'have relatively low values of capacitance(less' than O.2pf) and hence h'igh power circuits
are no~ required. 6r such low-power latch inter~al stages the maxim~m LI and L2
(Node A and N:ode B in Fig. 4.2) "externàl capacitance should be timited to O.lpf. Since
this internai no de is used only for scan out to an adjacent~~tch and f~r driving th:' output buffer. the above restriction is easily ::,atisfied . ..
The characteristics of the latch output versus output device Slzes are illustrated in ri' J 1 _
• •
• v
,-
/
\
fig. 4.3 and fig. 4.4. Here, Ton 15 defined as the delay for the output to fall to 2.5 volts
with respect to the dock rising to the 2.5-volt level., 1'.0 11 is' de~ned as the delay for the
output to rise to 2.5 volts with respect to the clock rising- to the·2.5-volt le~el. Trtse . - -~-
and Tlall' are delay~ of the output rising from 1 volt to 3 volts and falling From 3 yolts
to 1 volt, respectively. Tavg IS defined as (Ton + Toi 1) /2. Fig. 4.3 shows' the delay and
output rise time 'Of the \atch· output as a functlon' of the. output pull-up device( deviçe
69
, \
f
1 -
;11;
1 } , 1 L , ,
j \ <&"
\ i ~
1 ~ , ? !
l 1 ~
1 .
{ - ( i .
/
,"
" ,
_1<c .. - ;;-or- • , ~ . .-. '> ,
-'
Simulation
~J,
13 in Fig. 4.2) .W IL ratio for a fixeœcapaeitive load of 2.0 pF-;--The odevice W4/L ratio .,/' ,
'~elected ,was 8. This selection provides perform~nce which is optimized. -Fig. 4.4 shQWS . lJ" __ \
the delay and output faU time as a function of the output pull-down device( dev\ce 14 in
Fig. \4.2) W IL "ratio for the same capacitive load. Thë device W/L ratio selected was 3. 1 • , .
This~vice ~ize "results in an output fall time' which is nearly optimum. Fig, 4.5 shows
output performance of the latch versus capacitive load. The delays assume data valid
~rior to the arrivai of the dock sig~al. ,
\ .' , .' "' \
4".2.2 Latch Scan-Output Co~siderations
\
The LI output t6 the L2 latch can be taken from either the Al or BI nodes in
Fig. 4.2, both of which are internai LI latch nodes. The Al-node transfer' results in ~ 1
- \ noninverted data to the L2, whereas the Bl-node transfer results in out-of-phase data
o
"-
to the L2. To obtain an L2 output which is noninverting, the Bl~node of the LI is used
for transferring data to the '{.,2. For an inverting L2 output. the LI latch Al-node is \
used for transfer to the L2 latch. For MSRL, the scan-output is taken from Bl-node
instead of From Yt. The speed of the shiftlIlg operation Ois increased by by,-pas~ing the , ,
v ~
large output buffer by 3.4LQ. At 2pf load. the output response tlnle tS 28 nano-seconds
when the Scan-Output is taken frqm YI. \Whereas the output response tipl€ tS oniy 21
n~o-seconds when the Scan-Output is taken from Bl-node. It shoulâ be noted that
scan-output no de has a very limlted'drive capability, since it is arrÎnt~rnal latçh nodë.
It is intended to drive the scan-input of an adjacent LI-L2 latch pair only. Therefore. , \ -
Jor hea~oading,' the L2 latch output Y2 (figA.2) should be utilized as the LSSD ,.
scan-output.
\ . \ . ="'--'-- _::
\
;:'0
\ , ____ - .. .r'";. ~ 10"''' ~~ .. , ___ +'~,"*_(."'_"",,""'R~q,~~>-J.>_. ___ ,.., .... ___ _
" ,
,
(
l i
j
J , '<. \ \
!
} J,
! r f 1
(
1
t 1 ..
'0
\~
, \
.
"
o = Simulation _
This section has described many design considerations of a MSRL latch pair. The " \ J
original design goals of good performance, low power dissipation, and small size were
met by using high-performance output buffers. Performance characteristics, along with
device size selection of the latch, were also presented.
\ ~ \
\
l' o •
.\
\ t ....}
\
.... '\
t 1 \
.:;~~ ~ 1
\ "
) 1 \
cIf 'l,
) <,
0 '-..,.61
e
\
s,
\
,\ \ 1 0
71
.... ,
-~~---- --~ ..... -_ .... ~ .. ~_,.'_l! ..... il_ .... --.... " .... r;:re,.,.~-.---,-' ... , ·\~-----"_ .. _-_·~ü -_.::.. .. ~--....... - .... ~ -............,..,.......,. ... (::;w:u ........
. /
,\
\ ,
Sirriulation l '
--.. .
\ \
" \
\ o \
\ 50
\ \
Cl
45, •
c ,
\ Cf) 40 Z
\ \
z 35 - 3'2-·5
W\ 30 "- ~
25 t-
.0: \
w ,20 'Cf) , \ z 15 0 , Cl..
10 Cf) W tO·~ 0::
,
5 /"
0 1 3 14 5
D
\ W/L RATIO OF PULL\~UP DEVieE
\
OUTPUT RESPONSE TIME VS . ~L RATIO OF
( ,OUTPUT PULL-UP 'DEVieE
f 72 o \
",. " - ~~- k ~'f"'-.. _ ... _ .. ~ _n.~ .. ~"-"""""" .. ....-J ~"'_~'"''''1'1t'~_jl.,._.~~,e......,....,...,. ,,~_, ..... .......--..... _ ._. _
\, .\ ~-
f \
" \ ,-
r~ ilS ~. - ~ " ~1 , ~
\ ~-~ ~;
Simulatwn ~ ~- , ?
~ (~-~ '1,.1 \ .. :~
i' 1
\
1
Î ../ /
f \ 0
0
50 9<çr<!:./
./ i:: ,-
'\ t.: '45 ~ \ l
\ \ ~
~ tA 40 \ Z
0
z 35
w 30 \ '"
IAVG' <l
~ 25.9 \-
25 \
;\
20 Cf) z 15 0 a... Cf) la 0 I FALL w ,.1-et:: 5 ,~.
, \
0 1.0 2.0 3·0 - 4.0 5.0
\ \ ,0
W/L RATIO OF PULL-DaWN DEVieE ',- '
\ \
./ \ ./
\ \
\
FIG. 4.4 OUTPUT,RESPONSE TIME VS o/L RAilÇ) , OF
( >- OUTPUT PULl- DaWN DEVieE
\'
\
1 ""'"-- ~1 .. • Witt. t;tM~"""~~._. _.. .... ~ __
- cœ e ,
(]
f . ~
l 1
~' t: \ ~ l· ~ - Simulation
" . ~. "
t
1 f;
i f ~ 1
. f
" , , .' . , l' ,
\ CL Ton Tof! Tfall T rzse ,
"')
\ O.25Pf 18.3ns 12.7ns 2.1ns 2.1ns ,
3Ans O.50Pf 20.0ns 15.0ns 3.4ns , \ l.OOPf 22.5ns 17.1ns 5.0ns 5.0ns 2.00Pf 27.3ns 21.7ns 8.2ns
-, g'') , .... ns
3.00Pf 31.5ns 26.3ns 12.3ns 12.3ns 1
0
Table 4.5 Capacitive Load Vs Clrcuit Response Tirrle
\ . , \
.\ r
\ .'
( , \
~\ 74 \ \
o r~ _ , 1 .. ; Il
1 , ,
. ,
-
\
( \ \
\ \
\ \ \ ~\
... Conclusion
\
5. Conclusion
In thl'~' thesis, a modifi~d la'tch was proposed and a study wa~\ made of the us~f modified latch for designmg logic circuits. The latch design proposed is a variation of
'the existing L2~ scheme used ln LSSD environment. It was shown that the proposed •
design reduces the silicon cost of implementing the scan design.
In the proposed latch àll~d MSRL, a 'Mode-Swit:h' input selects the 'Normal':r
'Scan' mode. The same system c\ocks C and C* are used in both 'Scan' and '~ormal'
modes, thereby redueing area ove,rhead conslderably. The reduetion of are a overhead is
due to the ellrnlnaLlon of t he scan c\ocks :\. and B from the shlft reglster lateh of the \
L2' scherne, at the expense of sorne additlOnal logic( l inverter per latch pair) in each
flip-flop. Henee, in the proI?osed scheme two clock sign~ls and a rnode-switch have to
~ be routed over the whole ehip. Whereas m the L2* scherne, two syste~ clocks C and
C*, and two scan docks A and B need to be- routed. Typieally, in LSI/VLSI circuits, ,
long routing p\ths are considered more expensive compared to the addItion of a Fe:
local loglc gates. An exarnple of a scan register flip-flop is given to dlustrate that the
" (J,
additional logic can be implemented with just lwo' extra transistors.
,\n Important characteristl~- of the ~1SRL IS tha..t no race Cor hazard conditions •
are present durmg normal operation. The lateh is Level-Sensl{j've.' Also. the system
performance IS \not degraded with the use of :\-ISRLs. Advantages and cost Impact of
this scheme were discussed and a comparison was made with other existing systems. A.
set of deSIgn rules that "Yill result ln Level-~ensitive logie were also described
The technlcal details assoclated with the deSIgn of the shlft reg~ter latdi were
\
documented and performance improvements were identified through extensive circuit \ '. \ \
75
, \ ,
__ ~_~._ ... \ .. (( ..... """", ... ~~"",,,_-n.~~-'!.
\
\
\
\
\
\ Concluswn
\ simulations. The design goals of good performance, low power dissipation, and small
slze were met by usmg high performance output buffers. Sinece the latch is used as
a storage element whose output performance is essentially determined by its output
buffer, the power of the latch internai stages is reduced while the overall perfqrmance
is i\roved. Performance characteristlcs, along with deviè\ size selection of the latch
were also ·presented. Q
\ \
D
\ o \ \
\
'~ a \ -\
. \ \
\ \
\ \
\ 76
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Appendix A
Eichelberger and Williams[l~) presênted a set of design rul~s or constraints tha~
will result if! Level-Sensitiye and Scan Design:
Rule 1: Ali internai storage is implemented in hazard-free polarity-hold latches. \
tRuie 2:
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The latches are çontrolled by two or more non-overlapping\clocks such that:
(a) A latch, X, may feed the data port of another latch, Y, if and only if the dock" 0
that sets the data In ta latc h Y'does not dock latch X. \,
(b-l A latch, X, may gat~ a dock Ci to produce a gated dock Cig which drives'
another latch, Y, if and only if dock Cig do es not dock latch X. where Cig is"
any ciock derived from Ci.
\ \ Rule 3: It must be-possible ta identlfy a set of dock primary inputs from which the dock
p
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inputs to SRLs are control/ed either through simple powering trees Of through logic ~ ,~" \ ~ ,'\
that is gated by SRLs and/or non-dock primary Inputs. Giv.en this structure. the
following ru1es must hold :
, \.
( a) Ali dock inputs ta ail SRLs must be at their 'off' states when ail dock prirnary
in~uts are helcl ta thelr 'off' state \
(b) The dock signal that appea-rs at any dock input of an SRL must be control/able
from one or more dock PIs such that it is possible to set the dock input of the l
\ SRL ta an 'on' s~~te by tur~ing any one of the correspondi~g dock PIs to its
'on' state and also setting the required\gating conditions from §RLs and/or ,
non-floc.k PIs. \
(c) No dock can b\ ,ANDed with either ~~e tru~ or comp-lernent value of an~thër
dock.
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Rule 4: Clock primary inputs may not feed-the dat~ inputs to latches either' d~rectly or -" \ .
through combinational logic, but may oniy f~ed the dock input to the latches o~-
primary outputs.
Rule 5: Ail SRLs must be interconnected into one or more shift registers, each of whic~ has
an input, an output and shift ê40cks available at the terminais of the .package. l'
Rule 6: There must exist sorne primary input sensitizing condition (referred..to as the scan
."
state) such that:
(a) Each \SRL or scan-out PO is a func'tion of only the smgle preceding SRL or 1
scan-in ' PI in its shift register during the shifting operation. ( 1
(b) Ali docks except the shift docks are held 'off' at the SRL inputs
(c) Any shift dock to an SRL may be turned 'on' and 'off' bX changing the corre
spondin, \Iock primary -input for each dock.
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