© February 8, 2009 Dr. Lynn Fuller Canon 4X1 Mask Stepper Jobs Page 1 Rochester Institute of...

© February 8, 2009 Dr. Lynn Fuller

Canon 4X1 Mask Stepper Jobs

Rochester Institute of TechnologyMicroelectronic Engineering

ROCHESTER INSTITUTE OF TECHNOLOGYMICROELECTRONIC ENGINEERING

Canon Four Levels per Mask Plate Stepper Jobs

Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee

Microelectronic Engineering Rochester Institute of Technology

82 Lomb Memorial Drive Rochester, NY 14623-5604

Tel (585) 475-2035 Fax (585) 475-5041

Email: [email protected] Department webpage: http://www.microe.rit.edu

2-8-2009 Canon_4X1_Masks.ppt




OUTLINE

IntroductionChip DesignCalculationsMask ExampleApproachLevel 1 DetailsLevel 2,3,4,5,6,7,8,9,10,11,12 DetailsResults




INTRODUCTION

Placing four photo levels on one mask plate can reduce the number of mask plates by a factor of four. This saves time, costs and inventory of masks needed for projects. For example a 12 level mask set for CMOS will require only 3 mask plates.

The disadvantage of this approach is that the chip size is limited to 10mm by 10mm compared to 20mm by 20mm for 1 level per plate masks.

The stepper jobs are slightly more complicated but once created provide the same overlay and resolution.




CALCULATING SHIFTS TO OVER LAY LEVELS 2,3,4,5

The first layer is placed on the wafer with no alignment. Lets use an example where a chip has its TVPA marks in the center of the chip and the B scope multi-marks are slightly above, and C scope multi-marks are slightly to the left.

The Mask from non chrome sideEach level is centered +/- 20 mm from the center of the plate

Level 1

Level 2

Level 4

Level 3

Wafer after 1st exposure with blades wide open

1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3

Center of shot is placed under the center of the optical column




The Mask from non chrome side

Level 1

Level 2

Level 4

Level 3

CALCULATING SHIFTS TO OVER LAY LEVEL 2

1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3


1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3

The subsequent layers are aligned by locating the center of the TVPA and multi-marks from the first layer. Then calculating the center of the chip and moving it under the center of the optical column and make the shot. If in the stepper job the TVPA mark is given as X=0 and Y=0 the shot will be made with the 1st level TVPA under the center of the optical column resulting in exposure as shown. To get level 2 (red) to overlay level 1(green) we give x = -4mm and y = -4mm for the TVPA mark location in the stepper job. The stepper will shift the wafer -4 mm in x and -4mm in y when moving the wafer under the center of the optical column. Thus placing the 3rd quadrant (level 2) over the 2nd quadrant (level 1) as desired.





Level 1

Level 2

Level 4

Level 3

CALCULATING SHIFTS TO OVER LAY LEVELS 3

To get level 3 to overlay level 1(green) we give x = -4mm and y = +4mm for the TVPA mark location in the stepper job. The stepper will shift the wafer -4 mm in x and +4mm in y when moving the wafer under the center of the optical column. Thus placing the 4 th quadrant (level 3) over the 2nd quadrant (level 1) as desired.

1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3






Level 1

Level 2

Level 4

Level 3



1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3

To get level 4 to overlay level 1(green) we give x = +4mm and y = +4mm for the TVPA mark location in the stepper job. The stepper will shift the wafer +4 mm in x and +4mm in y when moving the wafer under the center of the optical column. Thus placing the 1 st quadrant (level 4) over the 2nd quadrant (level 1) as desired.





Level 5

Level 6

Level 8

Level 7



1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3

1

2

4

3

To get level 5 to overlay level 1(green) we give x = -4mm and y = +4mm for the TVPA mark location in the stepper job. The stepper will shift the wafer -4 mm in x and +4mm in y when moving the wafer under the center of the optical column. Thus placing the 2 st quadrant (level 5) over the 2nd quadrant (level 1) as desired.




MIXED SUB-CMOS CHIP DESIGN

(0,0)

(Xur,Yur)(X,Y) (X,Y)

(X,Y)

(X,Y)(X,Y)

Alignment Keys




SMALL CMOS MASK EXAMPLE 8mmX8mm

Level 1 nwell

Fiducial Mark

Alignment Keys

Level 2 active

Fiducial Mark

Level 4 PVt

Level 3 stop0,0

Level- 4Center at

20,20

Level- 1Center at

-20,20

Level- 3Center at

20,-20

Level- 2Center at-20,-20

View from Non-Chrome Side

Keys




LARGE CMOS MASK EXAMPLE 10mmX10mm

Level 1 nwell

Fiducial Mark

Alignment Keys

Level 2 active

Fiducial Mark

Level 4 Vt

Level 3 stop0,0

Level- 4Center at

25,25

Level- 1Center at

-25,25

View from Non-Chrome Side




CALCULATIONS FOR MIXED SUB-CMOS




CALCULATIONS FOR PMOS (SHORTCOURSE)




CALCULATIONS FOR LARGE CMOS TEMPLATE




APPROACH

First Level Exposure – cover the 1st, 3rd and 4th quadrants of the mask using the blade position in the shot file.- In the layout file create a block and shift the block CQ/5 mm in X and –CQ/5 mm in Y to center the array on the wafer.- In the process file select 1st Level – no alignment

Second level Exposure – cover the 1st, 2nd and 4th quadrants of the mask using the blade position in the shot file.

-no shift in the layout file (Otherwise same as level 1)- Shift the PA and Fine Alignment Mark positions on page 4 and 13 of the process file

Third level Exposure – cover the 1st, 2nd and 3rd quadrants of the mask using the blade position in the shot file.

-no shift in the layout file- Shift the PA and Fine Alignment Mark positions on page 4 and 13 of the process file




BLADE POSITIONS FOR SHOT FILES

LEVEL 1

2nd Quadrant

LEVEL 2

3nd Quadrant

LEVEL 3

4nd Quadrant

LEVEL 4

1st Quadrant

BL -10mm -10mm 0 0

BR 0 0 10mm 10mm

BU 10mm 0 0 10mm

BD 0 -10mm -10mm 0

(0,0)

Br = 0 mmBl = -10 mm

Bu = +10 mm

Bd = 0 mm

Blade positions are in mm referenced at the wafer.

Level 1




1st LEVEL LAYOUT FILE

#### LAYOUT EDITOR (File ID)### (page-1)File name; 1. Comment;

#### LAYOUT EDITOR (File ID)### (page-2)1. Matrix Invalid Area: 2. Step Size; Sx = Sy = 3. Matrix; Clm = Row = 4. Origin; X= Y=5. Reticle Table Name ;

Lmixed4X1_nwell

13 mm

anything you want

8.2 mm 8.2 mm

14 140 mm 0 mm

RF012subcmos

On page 2 you can create and shift blocks




1ST LEVEL LAYOUT CREATE AND SHIFT BLOCK

Select Function Key “Modify”Select Function Key “Other Menu”Select Function Key “Shift Copy Block”Select Function Key “Add Block”

Row *Column *

GoGo Sure? 1 = Yes

Select Function Key “Shift Block”X = 4mmY = -4mm

Clear Block 1 = YesExitExitSave




1st LEVEL - PROCESS FILE

#### PROCESS EDITOR (File ID)### (page-1)File name; 1. Comment; 2. Alignment Sequence: 1st Mask or AGA ….3. TTL Alignment Mode (none, I-line or HeNe/B2)4. TV PA Measurement Mode;#### PROCESS EDITOR (Reticle ID)### (page-2)1. Reticle ID#### PROCESS EDITOR (Fine Reticle Alignment)### (page-3)1. Fine Align Tol xy = Theta =

Lmixed4X_nwell/PFmixed4X_nwell

anything you want, like: second level active

The Process file has 36 pages, only highlighted pages can be accessed, if AGA in item 2 page 2 is selected then page 4 is highlighted and gives row and column and x,y location of the prealignment marks. If alignment mode HeNe is selected page 13 gives the x&y coordinates of the fine alignment marks, if I-line was selected then pg 10&11give fine alignment mark locations, if 1st Mask is selected page 4 to 36 are bypassed.

HeNe/B2

Nwell

0.03 µm0.03 µm

1st Mask

PA




2ND 3RD 4TH LEVEL PROCESS FILE

Page –1 Alignment Mode2. Alignment Sequence Mode; AGA3. TTL Alignment mode. ; HeNe-TV4. TV PA Measurement Mode ; PAPage –4 1. L) Shot : clm= ? row= ?

PA Mark Position; Xlp=QPAX mm Ylp= QPAY mm2. R) Shot : clm= ? row= ?

PA Mark Position; Xrp=QPAX mm Yrp= QPAY mmPage –131. AA Mark Position; B: X=BF2X mm Y = BF2Y mm

C: X=CF2X mm Y = CF2Y mm Brot

X=0Y=0

2. AA Mark Pattern ; 20P-4F3. Mark Condition ; Island4. Wafer Surface Condition ; 0Page –151. AA illumination Mode ; Mode-3

This process file does alignment to 2 TVPA marks and then looks at 4 locations for fine alignment. It uses Broad-Band illumination and 20P-4F multi-marks.

Page –171. Number of sample shots (2,4,6,8,12,16) Main; 4 Preliminary ; 42. AGA for first wafer ; AGA AGA for 2nd and more wafer ; AGAPage –19 1. Limit of x or y difference ; 0.5µm

(default=0.2µm, can be as large as 9µm)C1….R

1….




2ND LEVEL OVERLAY VERIFICATION

Mixed Sub-CMOS Product




OVERLAY VERIFICATION FOR BIG CMOS

Level 4 VTLevel 3 StopLevel 2 Active




EXAMPLE FILE NAMES

Stepper Job Layout File Shot File Process File Reticle Table

Reticle ID

mixed4x1_nwell Lmixed4x1_nwell Smixed4x1_nwell Pmixed4x1_nwell Rmixed4x Mixed4x1

Mixed4x1_act Lmixed4x1_act Smixed4x1_act Pmixed4x1_act Rmixed4x Mixed4x1

Mixed4x1_stop Lmixed4x1_stop Smixed4x1_stop Pmixed4x1_stop Rmixed4x Mixed4x1

Mixed4x1_vt Lmixed4x1_vt Smixed4x1_vt Pmixed4x1_vt Rmixed4x Mixed4x1

Mixed4x1_poly Lmixed4x1_poly Smixed4x1_poly Pmixed4x1_poly Rmixed4x Mixed4x1

Note: mixed4x1_nwell is 1st level no alignment, quadrant 2and Mixed4x1_poly is level 5, 9 etc., with alignment, quadrant 2

Small (< 8mm) CMOS Chips




EXAMPLE FILE NAMES


Reticle ID

L082SHORT4X_DIFF L082SHORT4X_DIFF S082SHORT4X_DIFF P082SHORT4X_DIFF

Rmixed4x Mixed4x1

L082SHORT4X_OX L082SHORT4X_OX S082SHORT4X_OX P082SHORT4X_OX Rmixed4x Mixed4x2

L082SHORT4X_CC L082SHORT4X_CC S082SHORT4X_CC P082SHORT4X_CC Rmixed4x Mixed4x3

L082SHORT4X_M L082SHORT4X_M S082SHORT4X_M P082SHORT4X_M Rmixed4x Mixed4x4

END

Note: L082SHORT4X_DIFF is 1st level no alignment, quadrant 2

Metal Gate PMOS and Shortcourse Jobs




EXAMPLE FILE NAMES


Reticle ID

F083ADC_nwell LF083ADC_nwell SF083ADC_nwell PF083ADC_nwell Rmixed4x Mixed4x1

F083ADC_act LF083ADC_act SF083ADC_act PF083ADC_act Rmixed4x Mixed4x2

F083ADC_stop LF083ADC_stop SF083ADC_stop PF083ADC_stop Rmixed4x Mixed4x3

F083ADC_vt LF083ADC_vt SF083ADC_vt PF083ADC_vt Rmixed4x Mixed4x4

F083ADC_poly LF083ADC_poly SF083ADC_poly PF083ADC_poly Rmixed4x Mixed4x1

Note: F083ADC _nwell is 1st level no alignment, quadrant 2and F083ADC _poly is level 5, 9 etc., with alignment, quadrant 2

Large (< 10mm) CMOS Chips




9.8mm X 9.8mm CHIP TEMPLATE

/shared/cmostestchip2007/CMOS4XTEMPLATE

Template for CMOS4Xdesigns

Each cell is 800 µm x 800µmEntire Chip is 9800µm x 9800µm

Lower Half has Process Verification Test Structures.

There is a 200µm street between quadrants on the testchip

This is the largest chip that can have 4 masks per plate.




EXAMPLE OF A MEBES PLOT JOB

2/25/09 9:12:23 MEBES 967REV, 4.6SPECIFICATION FILE: JOB:SHORT.JBDTITLE: CMOS FOUR LEVELS / PLATEITITLE: BARCODEMTITLE: LEVELS 1,2,3,4CASSETTE TYPE ID:14LEVEL PLOTTED: 1JOB SCALE: 1JOB SCALE: 1.000000ADDRESSING: 0.500000 MICRONSPLOT SCALE: 1.00 TO 1 CM

ID PATTERN X DIMENSION Y DIMENSION PLACEMENT ORIENTATION TONE1. NWELL.01 25000.00 25000.00 UNMIRROR UNMIRROR NORMAL2. ACTIVE.01 25000.00 25000.00 UNMIRROR UNMIRROR NORMAL3. STOP.05 25000.00 25000.00 UNMIRROR UNMIRROR NORMAL4. VT 25000.00 25000.00 UNMIRROR UNMIRROR NORMAL

LAYER 1,2,3,4 CMOS 4 LEVELS / PLATE

BA

RC

OD

E

LVL4

12 cm

12 cm

0.0

0.0

LVL1

LVL3

LVL2

X Axis

Y A

xis




CREATE A MEBES JOB DECK

SLICE EDIT, 1414 means 5” by 5” glass

OPTICON AA=0.5, BA=0.5, PA, SA=40, VA=10 AA means address all levels = 0.5 µmBA means beam size all levels = 0.5 µmPA means all levels positive resistSA means all levels spot current 40 nAVA means all levels acceleration = 10KV

MTITLE 1, ADV-CMOS STIDTITLE A, RIT EMCR650ITITLE A, BARCODEORIENT A, ITITLE, TITLEROT=90, LOC=

CHIP1, (1,cmostestchip-LVL-01, RC=15),first level of cmostestchip maskset

END

SLICE EDIT,14OPTION AA=0.5, BA=0.5, PA, SA=250, VA=10REPEAT A, 10STITLE A, 10000, 10000, MEBES III SN @SMTITLE 1, NWELLMTITLE 2, ACTIVEMTITLE 3, STOPMTITLE 4, PMOS VTMTITLE 5, POLYMTITLE 6, LDD NMTITLE 7, LDD PMTITLE 8, N DSMTITLE 9, P DSMTITLE 10, CONTACTMTITLE 11, METALDTITLE A, SUBMICRON CMOSCHIP 1,(A,RITLOGO-50-01)ROWS 10000/63500CHIP 2,(A,FIDUCIA-LS-01)ROWS 63500/63500CHIP 3,$ (1R,EMCR650-01-01),$ (2,EMCR650-01-02),$ (3,EMCR650-01-03),$ (4,EMCR650-01-04),$ (5,EMCR650-01-05),$ (6,EMCR650-01-06),$ (7,EMCR650-01-07),$ (8,EMCR650-01-08),$ (9,EMCR650-01-09),$ (10,EMCR650-01-10),$ (11,EMCR650-01-11)ROWS 63500/63500END




REFERENCES

1. Robert Manley process improvement project.2. Germain Fenger process improvement project.3. Fuller, Lynn Introduction to Reduction Steppers. Rochester

Institute of Technology, 20024. FPA-200i1 Maintenance Training: Basic Operations Manual,

Canon USA5. Chuck Smith, MicroE Alumni 1987, Applications Engineer, Canon USA, Inc. 804-328-6620x203, [email protected]. Bill Cooman, Canon Equipment Engineer, Maintains the RIT Canon FPA 2000-i1

© February 8, 2009 Dr. Lynn Fuller Canon 4X1 Mask Stepper Jobs Page 1 Rochester Institute of...

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