Activation et transfert de licence SolidWorks - cadware-utilities
™ CADware s.r.o. Prezentuje ve spolupráci s firmou ModelSim DE.
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Transcript of ™ CADware s.r.o. Prezentuje ve spolupráci s firmou ModelSim DE.
![Page 1: ™ CADware s.r.o. Prezentuje ve spolupráci s firmou ModelSim DE.](https://reader035.fdocuments.in/reader035/viewer/2022062409/56649e9e5503460f94ba08b3/html5/thumbnails/1.jpg)
™
CADware s.r.o.
Prezentuje ve spolupráci s firmou
ModelSim DE
![Page 2: ™ CADware s.r.o. Prezentuje ve spolupráci s firmou ModelSim DE.](https://reader035.fdocuments.in/reader035/viewer/2022062409/56649e9e5503460f94ba08b3/html5/thumbnails/2.jpg)
Mentor Graphics ModelSim DE 6.5
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ModelSim DE Leading Single & Mixed Language Simulation
Native single kernel verification environment— Verilog 1995, 2001, 2005— VHDL 1987/1993/2002/2008— SystemVerilog for design— SystemVerilog and PSL assertions— SystemC with SCV and TLM, C, C++ (option)
Broadest type support at language boundaries— Component/module instantiation— SignalSpy™— SC control, observe and connect methods— Only simulator able to share type definitions written in one
package in both VHDL and SystemVerilog Preserving full benefits of strong type checking
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ModelSim DE Leading Single & Mixed Language Simulation
Integrated debug and analysis capabilities— Comprehensive root cause analysis— Coverage analysis and reporting— Commands/GUI consistent across languages, HW platforms
and abstraction levels
SecureIP support— Higher performance Xilinx IP— Native support for VHDL and Verilog
Linux and Windows support
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Mentor Graphics ModelSim DE 6.5
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ModelSim DE Leading Assertion and Coverage technology
SVA and PSL assertions— Improved verification effectiveness— Improved time to debug
Identify failures as they occur ModelSim DE advanced assertion debugging
— Assertion browsing
OVL assertion library ready
Code Coverage— Efficient coverage collection
Unified Coverage Database (UCDB)— Improve verification test productivity
Ranking and Merging
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Agenda
Assertions
Debug & Analysis
Coverage
![Page 6: ™ CADware s.r.o. Prezentuje ve spolupráci s firmou ModelSim DE.](https://reader035.fdocuments.in/reader035/viewer/2022062409/56649e9e5503460f94ba08b3/html5/thumbnails/6.jpg)
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Reference Model
Assertion Based Verification Improves Time-To-Bug
ABV detects bugs at the source, saving valuable debug time ABV detects bugs missed by top-level test benches
==== Lurking bugs:found late in the
design cycle
Lurking bugs:found late in the
design cycle
Design Under Test
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What is an Assertion?
A concise description of [un]desired behavior
“After the request signal is asserted, theacknowledge signal must come 1 to 3 cycles later”
0 1 2 3 4 5
req
ack
Example intended behavior
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Who Uses Assertions?
Must remember…This is a 1-hot state
machine
Must remember…This is a 1-hot state
machine
Hmm.. I assume the CS inputs are
mutually exclusive
Hmm.. I assume the CS inputs are
mutually exclusive
Better warn others about those
checksum gotchas
Better warn others about those
checksum gotchas
Functional spec says ACK will follow REQ
within 7-12 clock cycles
Functional spec says ACK will follow REQ
within 7-12 clock cycles
Spec. says that REQ must not drop before
ACK is received.
Spec. says that REQ must not drop before
ACK is received.
What I really need to know is how many times
a transfer DOESN’T complete
What I really need to know is how many times
a transfer DOESN’T complete
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SVA Assertion property req_ack; @(posedge clk) $rose(req) |-> ##[1:3] $rose(ack);endpropertyas_req_ack: assert property(req_ack);
always @(posedge req) begin repeat (1) @(posedge clk); fork: pos_pos begin @(posedge ack) $display("Assertion Success",$time);
disable pos_pos; end begin repeat (2) @(posedge clk); $display("Assertion Failure",$time); disable pos_pos; end join end // always
Verilog
HDL Assertion
req
ack
0 1 2 3 4 5
Example intended behavior
Concise and Expressive
SystemVerilog
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Reference Model
ABV Improves Time-To-Coverage
ABV reveals internal structural coverage ABV produces actionable metrics to improve coverage
?
Design Under Test
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Best Time To Bug Resolution Assertions identify failure closest to design failure
— Need ability to visualize the assertion— Need ability for root cause analysis
ModelSim DE has the best visualization and debug tools— Language neutral debug suite— Assertion Analysis
Lists all assertions at current hierarchy— Waveform Viewing
S/W logic analyzer View assertion and it’s signals Clear indication of assertion status: active/inactive/pass/fail
— Assertion animation Decomposes assertion for best understanding
— Complete user interface tools for root cause analysis Source code and graphical dataflow
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Viewing Assertions in the Wave
Green mid-line indicates assertion is active
Blue low-line indicates assertion is inactive
Simply D&D Assertions from Assertion Browser into Wave Window to view assertionsAssertions can be expanded to view all signals associated with the assertion
Red inverted triangleindicates assertionfailure
Green triangleindicates assertionpassed
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View Multiple Assertion Threads
Automatic Thread count
integer
Expand to see
individual thread
RMC on start of thread box invokes ATV
Blue box above thread
indicates start of new
thread
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Failure ResolutionAssertion Thread Viewer
Root cause analysis— Source code— Wave window— Visualize in assertion thread window
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Strategies for Adopting ABV Specify design intent
— What I thought I designed Identify high-level elements in your blocks:
— FIFOs, Arbiters, Memories, FSMs Declarations Key Operations
— Put arithmetic overflow on arithmetic ops— Guard all module I/O
— Corner cases Make sure test exercises difficult scenarios Make sure illegal situations are handled correctly
Specify environment assumptions— What other blocks are doing— Input assumptions— What the testbench should be doing— Avoid debugging false-negative testbench problems
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Agenda
Assertions
Debug & Analysis
Coverage
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Debug All Languages And Analyze CoverageCommon control & behavior for all windows
Any window can form a tab group with any
other window
Consistent look and feel for all languages
Root cause isolation
Coverage analysis and reporting
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Enhanced Wave Window Full capabilities
— HDL, SystemC, TLM and Assertion Debug
Cross linked with entire debug environment
Waveform Compare— Identify first failure
Logical Views— Virtual Objects
Signals, Functions and regions
Waveform management— Dataset snapshot, subset,
clear, save, stats
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Wave Window Delta ViewingToolbar to control delta viewing
Wave window expanded to show delta changes
Same information in list form
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User Defined Radix
radix define States { 11'b00000000000 "NOPUSH", 11'b00000000001 "PUSH1", 11'b00000000010 "PUSH2", …
11'b10000000000 "PUSH11", -default hex}
Tcl command defines radix
New radix appears in pick list
“push” signals with & without radix
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Wave Window Create multiple panes and drag and drop signals from one pane
to the other. Powerful Edit and Search Capabilities under the Edit Menu. Cursors - multiple, jump to edge and measurement. Bookmarks for marking multiple waveform views. Balloon popup to display values
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Wave Window Analog Display Improved analog wave display
— add wave -min and –max Example of signal with values between 0 and 5
add wave –analog –min 0 –max 5 –height 100 <my_signal>
— Clamp display to min/max values add wave –clampanalog {0|1}
— Save with write format wave <file.do>
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Source Annotation
Annotation can be linked to active cursor
Signal transitions
Steady state values
Hover over signal to get full path & value
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Textual Dataflow: Tracing Signals
Find reader of strb_r
Select Signal then RMB
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Textual Dataflow: Tracing Signals
Find driver(s) of prdy_r
Select Signal then RMB
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Graphical Dataflow: Tracing SignalsFind Cause of Unknown with ChaseX
Users can also direct dataflow window to compute and draw paths between one point and another
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Easing Causality TracingSource Code Hyperlinking
Enable source code hyperlinking
Hyperlinked variables
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Jump to source window and Jump to source window and highlight variable declarationhighlight variable declaration
Easing Causality TracingSource Code Hyperlinking
Jump through hierarchyJump through hierarchy
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Expanded Data requires Data Management Message Viewer
Organize all simulation messages Sort by severity or type Cross links to other windows for quick isolation of
problems
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Agenda
Assertions
Debug & Analysis
Coverage
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Code Coverage Measures language coverage
— Have you executed each: Statement Branch Condition Expression Or Toggled each bit
Best used at block level— Easier to exercise code
aspects— Ensures blocks are tested &
ready for integration Built-in
— Low overhead— Easy to use— High capacity and performance
UCDB Improve verification throughput
— Rank UCDB test files and eliminate regression tests that do not contribute to coverage metrics
— Comprehensive coverage exclusion support
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CodeCoverage
FunctionalCoverage
AssertionEngine
UCDB
VerificationCoverage
Analysis &Reporting
3rd Party, Other Mentor Tools &
UserData
Database Toolset, load, copy, merge, rank, report, analyze
Best capacity and performance
Most comprehensive Base technology for
Questa Verification Management
Unified Coverage DataBase (UCDB)
0-inFormal
UserCoverage
TestSpecific
Test
Plan
ModelSim
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Ranking Coverage Results
Per Instance or DU
Include Time based goals
Merge and analyze regression suite results Identify highest yield coverage regression tests
— Eliminate non-contributing tests
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HTML Coverage Viewing
For details click on specific Item
Specify design Hierarchy
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Code Coverage Reporting Efficiencies
UCDB/Simulation Details
Coverage Totals
Includes complete coverage result details Easy reporting to management
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ModelSim DE 6.5 Functional Verification
The best execution— Integrated platform available today
The best technology— Improve verification effectiveness with assertions
The right strategy— Make every verification cycle count!
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Additional Mentor Products
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Processor-driven Verification
Allows test efforts to span multiple stages of the design - test reuse across the project
Questa Codelink provides the critical features to support processor-driven, including multi-core verification
Testbench-based tests
Processor-Driven C test
High-LevelSimulation
RTL/GateSimulation
Emulation Prototypeor FPGAs
Post-Fabrication
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Hardware/Software Correlation
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Multi-Core Processor Debug Environment
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Mentor’s 0-In® Formal Verification Solution Delivers …
Highest capacity and performance
Extensive Design Style Support
Smart integration of formal verification with simulation
The largest library of assertion IP in the industry Intuitive graphical analysis and debug Questa Coverage database enabled
The ‘proven’ formal verification solutionThe ‘proven’ formal verification solution
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0-In® CDC Verificaton
Structural CDC verification— Automatically identifies all clocks and
clock-domain crossings (CDCs)
Verification of CDC protocols — Automatically proves CDC Protocols — Simulate CDC protocol assertions
Silicon-accurate RTL simulation— Mimics the metastability effects in
synchronizers
Accurate Coverage metrics— Provides a measure of completeness for
the testbench as related to metastability issues
0-In® CDC – The Benchmark in CDC verification0-In® CDC – The Benchmark in CDC verification
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