© 2011 IBM Corporation1 Grzegorz T. Kolecki Senior Client Technical Specialist Nowe oblicze...

© 2011 IBM Corporation1

Grzegorz T. KoleckiSenior Client Technical Specialist

Nowe oblicze mainframe’azEnterprise: z114 i z196


Trademarks

Notes:

Performance is in Internal Throughput Rate (ITR) ratio based on measurements and projections using standard IBM benchmarks in a controlled environment. The actual throughput that any user will experience will vary depending upon considerations such as the amount of multiprogramming in the user's job stream, the I/O configuration, the storage configuration, and the workload processed. Therefore, no assurance can be given that an individual user will achieve throughput improvements equivalent to the performance ratios stated here.

IBM hardware products are manufactured from new parts, or new and serviceable used parts. Regardless, our warranty terms apply.

All customer examples cited or described in this presentation are presented as illustrations of the manner in which some customers have used IBM products and the results they may have achieved. Actual environmental costs and performance characteristics will vary depending on individual customer configurations and conditions.

This publication was produced in the United States. IBM may not offer the products, services or features discussed in this document in other countries, and the information may be subject to change without notice. Consult your local IBM business contact for information on the product or services available in your area.

All statements regarding IBM's future direction and intent are subject to change or withdrawal without notice, and represent goals and objectives only.

Information about non-IBM products is obtained from the manufacturers of those products or their published announcements. IBM has not tested those products and cannot confirm the performance, compatibility, or any other claims related to non-IBM products. Questions on the capabilities of non-IBM products should be addressed to the suppliers of those products.

Prices subject to change without notice. Contact your IBM representative or Business Partner for the most current pricing in your geography.

* Registered trademarks of IBM Corporation

The following are trademarks or registered trademarks of other companies.

* All other products may be trademarks or registered trademarks of their respective companies.

Adobe, the Adobe logo, PostScript, and the PostScript logo are either registered trademarks or trademarks of Adobe Systems Incorporated in the United States, and/or other countries.Cell Broadband Engine is a trademark of Sony Computer Entertainment, Inc. in the United States, other countries, or both and is used under license there from. Java and all Java-based trademarks are trademarks of Sun Microsystems, Inc. in the United States, other countries, or both. Microsoft, Windows, Windows NT, and the Windows logo are trademarks of Microsoft Corporation in the United States, other countries, or both.InfiniBand is a trademark and service mark of the InfiniBand Trade Association.Intel, Intel logo, Intel Inside, Intel Inside logo, Intel Centrino, Intel Centrino logo, Celeron, Intel Xeon, Intel SpeedStep, Itanium, and Pentium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.UNIX is a registered trademark of The Open Group in the United States and other countries. Linux is a registered trademark of Linus Torvalds in the United States, other countries, or both. ITIL is a registered trademark, and a registered community trademark of the Office of Government Commerce, and is registered in the U.S. Patent and Trademark Office.IT Infrastructure Library is a registered trademark of the Central Computer and Telecommunications Agency, which is now part of the Office of Government Commerce.

The following are trademarks of the International Business Machines Corporation in the United States and/or other countries.

AIX*BladeCenter*CICS*DataPower*DB2*DFSMSDS8000*ESCON*

IBM*IBM eServerIBM (logo)*IMSParallel Sysplex*POWER*POWER7*

POWER*POWER7*PR/SMSystem x*System z*System z9*System z10*System z10 Business Class

VSE/ESAWebSphere*XIV*z9*z10 BCz10 ECzEnterprise

z/OS*zSeries*z/VM*z/VSE*

FICON*GDPS*HiperSocketsIBM*IBM eServerIBM (logo)*IMSParallel Sysplex*


Business processes and the applications that support them are becoming more service oriented, modular in their construction, and integrated.

The components of these services are implemented on a variety of architectures and hosted on heterogeneous IT infrastructures.

Approaches to managing these infrastructures along the lines of platform architecture boundaries cannot optimize: alignment of IT with business objectives; responsiveness to change; resource utilization; business resiliency; or overall cost of ownership.

Customers need better approach: The ability to manage the IT infrastructure and Business Application as an integrated whole.

Information technology today is limited by the technology and architecture configurations available.

Information technology today is limited by the technology and architecture configurations available.

DS Servers

LAN Servers

SSL/XMLAppliances

CachingAppliances

RoutersSwitches

FirewallServers

File/Print ServersBusiness Intelligence

Servers

Security/Directory Servers

Web Servers

Application Servers

System z

Information technology today: Limitations


In July 2010, the IBM zEnterprise system introduced the first hybrid computing technology enabling clients to:

Central Processing

Complex

Central Processing

Complex

IBM zEnterprise™

Unified Resource Manager

IBM zEnterprise™

Unified Resource Manager

IBM zEnterprise BladeCenter®

Extension (zBX)

IBM zEnterprise BladeCenter®

Extension (zBX)

Optimize the deployment of workloads by utilizing the best fit technology and operating environment

Deploy enterprise private clouds that are ready for mission critical applications

Establish a common management infrastructure for both mainframe and distributed-systems

Take actionable insight based upon real time analytics


zEnterprise Unified Resource Manager

zEnterprise Unified Resource Manager

Application interfaces that allow access to Unified Resource Manager data by customer and applications (such as Tivoli, System Director, ISVs…)

Application interface to allow an alternative hardware console for GDPS

Dynamic discovery of storage resources by hypervisors New I/O subsystem that improves

robustness, resiliency and performance

Improvements to parallel sysplex coupling technology with lower overhead and improved performance at extended distances

Cryptography updates to adhere to various industry standards

Multiple usability improvements through TKE (Trusted Key Entry) updates

zEnterprise BladeCenter® Extension (zBX)

zEnterprise BladeCenter® Extension (zBX)

The IBM zEnterprise System:Continuing the evolution

IBM zEnterprise 196 (z196)IBM zEnterprise 196 (z196)

IBM System x – Linux

IBM System x – Windows*

*All statements regarding IBM future direction and intent are subject to change or withdrawal without notice, and represents goals and objectives only.

IBM zEnterprise 114 (z114)IBM zEnterprise 114 (z114)

New mid-range Mainframe based offering bringing zEnteprise technology advantage to small and medium businesses.

What’s New!What’s New!


zEnterprise 114 (z114)Machine Type: 2818

2 Models: M05 & M10

zEnterprise technology designed for small and mid-sized businesses The Value Begins At the Heart with the z114 …

Improvement for traditional z/OS workloads 1

Improvement in CPU intensive workloads via compiler enhancements2

18%

12%

Up to

Up to

Total capacity improvement 1

Up to an ADDITIONAL

25%

26 - 3100 MIPS

0-2 IBM provided spare cores

256 GB RAIM fault tolerant memory

From

Up to

130 available capacity settings

Scales From

Up to

Fully Upgradeable from the IBM System z10 Business Class™ (z10 BC) & IBM System z9® Business Class (z9 BC); and to the z196 M15

1-10 configurable cores for client use includes CPs, IFL, zIIP, zAAP, and ICFs

From

New technology in a new package ► Modular 2 drawer design for lower cost of entry► Granularity for right-sizing your system► Additional Scale for consolidation and growth► Improved data center efficiency► Same Qualities of Service as the z196 ► Hybrid enabled to drive workload integration and

management

Improved Platform Economics► New Software Curve► Lower Hardware Maintenance► Lower specialty engine and memory prices► Upgradeability for investment protection

1Relative capacity and performance compares at equal software levels as measured by IBM Large System Performance Reference (LSPR) workloads using z/OS® 1.11, Results may vary2The z114 will exhibit up to 25% increase for CPU intensive workload as provided by multiple C/C++ compiler level improvements when going from z/OS 1.09 to z/OS 1.12


Machine Type– 2818

2 Models– M05 and M10– Single frame, air cooled– Non-raised floor option available– Overhead Cabling and DC Power Options

Processor Units (PUs)– 7 PU cores per processor drawer (One for M05 and two for M10)– Up to 2 SAPs per system, standard– 2 spares designated for Model M10– Dependant on the H/W model - up to 5 or 10 PU cores available for characterization

• Central Processors (CPs), Integrated Facility for Linux (IFLs), Internal Coupling Facility (ICFs), System z Application Assist Processors (zAAPs), System z Integrated Information Processor (zIIP), optional - additional System Assist Processors (SAPs)

• 130 capacity settings Memory

– Up to 256 GB for System including HSA• System minimum = 8 GB (Model M05), 16 GB (Model M10)• 8 GB HSA separately managed• RAIM standard• Maximum for customer use 248 GB (Model M10)• Increments of 8 or 32 GB

I/O– Support for non-PCIe Channel Cards– Introduction of PCIe channel subsystem

– Up to 64 PCIe Channel Cards – Up to 2 Logical Channel Subsystems (LCSSs)

STP - optional (No ETR)

z114 Overview


Two hardware models

Up to 10 processors configurable as CPs, zAAPs, zIIPs, IFLs, ICFs, or optional SAPs

Up to 26 subcapacity settings across a maximum of 5 CPs

Up to 256 GB of Redundant Array of Independent Memory (RAIM) for System

Dedicated Spares on the Model M10

Increased capacity processors

Out of order instruction execution

Improved processor cache design

New and additional instructions

On Demand enhancements

CFCC Level 17 enhancements

Cryptographic enhancements

6 and 8 GBps interconnects

STP enhancements

Doubled HiperSockets™ to 32

Doubled Coupling CHPIDs to 128

New 32 slot PCIe Based I/O Drawer

Increased granularity of I/O adapters

New form factor I/O adapters i.e FICON® Express8S and OSA-Expres4S

Improved PSIFB Coupling Link

Physical Coupling Links increased to 72

Optional High Voltage DC power

Optional overhead I/O cable exit

NRF Support with either top exit or bottom exit I/O and power

zBX Model 002 with ISAOPT, POWER7, DataPower and IBM System x Blades

Platform Management from HMC

z114

Blue items denote common features between z114 and z196

zEnterprise 114 Functions and Features (GA Driver 93 – September, 2011)


z114 – Under the covers

InternalBatteries(optional)

PowerSupplies

I/O Drawer

2 x Processor Drawers, Memory

& HCAs

FICON & ESCON® FQC

Ethernet cables for internal System LAN connecting Flexible Service Processor

(FSP) cage controller cards (not shown)PCIe I/O

drawers

Rear View Front View

2 x SupportElements


z114 continues the CMOS Mainframe heritage

0

500

1000

1500

2000

2500

3000

3500

1997Multiprise®

2000

1999Multiprise

3000

2002z800

2004z890

2006z9 BC

2008z10 BC

MH

z

139MHz

413 MHz

625 MHz

1.0 GHz

1.4 GHz

z800 - Full 64-bit z/Architecture®

z890 - Superscalar CISC pipeline z9 BC - System level scaling

3.5 GHz

z10 BC - Architectural extensions Higher frequency CPU

z114 – Additional Architectural extensions and new cache structure

Multiprise 2000 – 1st full-custom Mid-range CMOS S/390

Multiprise 3000 – Internal disk, IFL introduced on midrange

2011z114

3.8 GHz

4000


z114 Sub-capacity Processor Granularity

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

The z114 has 26 CP capacity levels (26 x 5 = 130)– Up to 5 CPs at any capacity level

• All CPs must be the same capacity level The one for one entitlement to purchase one zAAP

and/or one zIIP for each CP purchased is the same for CPs of any speed.

– All specialty engines run at full speed– Processor Unit Value for IFL = 100

Number of z114 CPs

Base Ratio Ratio z114 to

z10 BC1 CP z10 BC Z01 1.18

2 CPs z10 BC Z02 1.16

3 CPs z10 BC Z03 1.14

4 CPs z10 BC Z04 1.13

5 CPs z10 BC Z05 1.12

Capacity level # Engines

PCI – Processor Capacity IndexPCI – Processor Capacity Index

5-Way4-Way

3-Way2-Way

1-Way

1-way(sub-capacity

26 PCIs)

5-way 3139 PCIs

FULL sizeSpecialty Engine

1-way782 PCIs


z114 – IBM Leadership Technology At the Core

3.8 GHz Superscalar Processor Chip boosts hardware price/performance – 100 new instructions – improvements for CPU intensive,

Java™, and C++ applications– New on-chip cache structure to help optimize data

serving environment– Out-of-order execution sequence gives significant

performance boost for compute intensive applications– Significant improvement for floating point workloads

Data compression and cryptographic processors right on the chip

Over 18 percent performance improvement per core and 12% improvement in total system scalability over the z10 BC.

Compiler related enhancements help drive gains of up to 25% improvement in throughput for CPU/Numeric intensive workloads.


z114 PU Chip Details

12S0 45nm SOI Technology

► 13 layers of metal

Chip Area – 512.3mm^2

► 23.5mm x 21.8mm

► 8093 Power C4’s

► 1134 signal C4’s

1.4 Billion Transistors

4 Core Design

► 3.8 GHz

► Full out-of-order capability

► 1.5MB L2 cache

► 12MB shared L3 cache

Two Co-Processors

► Data Compression & encryption

Memory controller

► Supports 5-channel DDR3 RAIM

GX Controller

3 PLLs, 5+ frequency domains

5 unique chip voltage supplies

z114TLLB15

L2(1.5MB)

CoPMCU

L2(1.5MB)

L2(1.5MB)

CoP GX

L2(1.5MB)

L3_0 Controller

L3_1 Controller

L3B

L3B

Core 0

Core 1

Core 2

Core 3

MCIOs

MCIOs

GXIOs

GXIOs

L3 Cache(12MB)

L3 Cache(12MB)


z114 SC Chip Details

z114TLLB16

L4 Cache(24MB)

Perv

ClkRepower

PLLL4 Controller

Fabric

IOsDataBit-

Stack

ETR/TOD

L4 Cache(24MB)

L4 Cache(24MB)

L4 Cache(24MB)

Fabric

IOs

DataBit-

Stack Perv Perv

12S0 45nm SOI Technology– 13 layers of metal

Chip Area – 478.8mm^2 – 24.4mm x 19.6mm– 7100 Power C4’s– 1819 signal C4’s

1.5 Billion Transistors– 1 Billion cells for eDRAM

eDRAM Shared L4 Cache– 96 MB per SC chip

6 CP chip interfaces– 2 used

3 Fabric interfaces– 1 used

2 clock domains



One z10 BC Drawer Two z114 Drawers (Model M10)

System resources split between 2 drawers (Model M10)

Second CEC drawer (Model 10) for:– Increased specialty engine capability– Increased memory capability– Increased I/O capability

• More coupling links than z10 BC• More I/O features than z10 BC

Processor / Memory Subsystem Drawers (Model M05 and M10)


Machine Type– 2817

5 Models– M15, M32, M49, M66 and M80

Processor Units (PUs)– 20 (24 for M80) PU cores per book– Up to 14 SAPs per system, standard– 2 spares designated per system– Dependant on the H/W model - up to 15,32,49,66 or 80 PU

cores available for characterization• Central Processors (CPs), Integrated Facility for Linux (IFLs),

Internal Coupling Facility (ICFs), System z Application Assist Processors (zAAPs), System z Integrated Information Processor (zIIP), optional - additional System Assist Processors (SAPs)

– Sub-capacity available for up to 15 CPs• 3 sub-capacity points

Memory– System Minimum of 32 GB– Up to 768 GB per book– Up to 3 TB for System and up to 1 TB per LPAR

• Fixed HSA, standard • 32/64/96/112/128/256 GB increments

I/O– Up to 48 Infiniband I/O Interconnects per System @ 6 GBps

each– Up to 48 PCIe interconnects per System @ 8 GBps each – Up to 4 Logical Channel Subsystems (LCSSs)

– Up to 3 Sub-channel sets per LCSS STP - optional (No ETR)

z196 Overview


zEnterprise 196 Functions and Features (GA Driver 86 – August, 2010)

z196

Five hardware models

Quad core PU chip

Up to 80 processors configurable as CPs, zAAPs, zIIPs, IFLs, ICFs, or optional SAPs

Increased capacity processors

Out of order instruction execution

Over 100 new and enhanced instructions

Improved processor cache design

Up to 15 subcapacity CPs at capacity settings 4, 5, or 6

Up to 3 TB of Redundant Array of Independent Memory (RAIM)

Unified Resource Manager suites

Cryptographic enhancements

On Demand enhancements

Energy efficiencies

2 New OSA CHPIDs – OSX and OSM

Three subchannel sets per LCSS

8 slot, 2 domain I/O drawer

Concurrent I/O drawer add, remove, replace

FICON discovery and autoconfiguration

Doubled HiperSockets to 32



CFCC Level 17

Optional water cooling

Optional High Voltage DC power

Static Power Save Mode

Optional Top Exist I/O cable exit

STP enhancements

zBX-002 with IBM Smart Analytics Optimizer, IBM Blades


zEnterprise 196 Functions and Features (GA Driver 93 – Sept 2011)

Additional Cryptographic enhancements

8 GBps PCIe interconnects

Additional STP enhancements


Improved PSIFB Coupling Link


New 32 slot PCIe Based I/O Drawer

Increased granularity of I/O adapters

New form factor I/O adapters i.e FICON Express8S and OSA-

Expres4S


z196 Air cooled – Under the covers (Model M66 or M80) Front view


PowerSupplies

I/O cage

Processor Books, Memory, MBA and

HCA cards

2 x CoolingUnits (MRUs)

InfiniBand I/O Interconnects

2 x SupportElements

Optional FICON & ESCON FQC – not shown


(FSP) cage controller cards

PCIe I/O drawers


z196 Water cooled – Under the covers (Model M66 or M80) front view


PowerSupplies

I/O cage

Processor Books, Memory, MBA and

HCA cards

2 x Water Cooling

Units

InfiniBand I/O Interconnects

SupportElements


(FSP) cage controller cards

I/O drawers


0

1000

2000

3000

4000

5000

1997G4

1998G5

1999G6

2000z900

2003z990

2005z9 EC

2008z10 EC

2010z196

300MHz

420 MHz

550 MHz

770 MHz

1.2 GHz

1.7 GHz

4.4 GHz

5.2 GHz

G4 – 1st full-custom CMOS S/390®

G5 – IEEE-standard BFP; branch target prediction G6 – Copper Technology (Cu BEOL)

z900 – Full 64-bit z/Architecture z990 – Superscalar CISC pipeline z9 EC – System level scaling

z10 EC – Architectural extensions z196 – Additional Architectural

extensions and new cache structure

MH

z

z196 Continues the CMOS Mainframe Heritage


7xx

6xx

5xx

4xx

CP MSU Capacity Relative to Full Capacity

7xx = 100% 6xx 64% 5xx 49% 4xx 20%

xx = 01 Through 15

MSU Sub Capacity

Subcapacity CPs may be ordered on ANY z196 model with 1 to 15 CPs. If 16 or more CPs are ordered all must be full 7xx capacity

All CPs on a z196 CPC must be the same capacity All specialty engines run at full capacity. The one for one entitlement to purchase one

zAAP and one zIIP for each CP purchased is the same for CPs of any capacity. Only 15 CPs can have granular capacity but other PU cores may be characterized as full

capacity specialty engines The z196 is capable of over 2 million 4k byte read I/O operations per second. This

measurement was done using a z196 4 book 14 SAP configuration with 104 FICON Express8 channels connected to 11 DS8000 ®Storage systems using zHPF protocols.

Processor Unit Value (PUV) for z196 is 120

z196 Full and Sub-Capacity CP Offerings

M15 M32 M49 M66 M80

4xx

MSU Sub Capacity


z196 Quad Core PU Chip Detail

Up to Four active cores per chip

– 5.2 GHz – L1 cache/ core

• 64 KB I-cache• 128 KB D-cache

– 1.5 MB private L2 cache/ core Two Co-processors (COP)

– Crypto & compression accelerators

– Includes 16KB cache

– Shared by two cores 24MB eDRAM L3 Cache

– Shared by all four cores Interface to SC chip / L4 cache

– 41.6 GB/sec to each of 2 SCs I/O Bus Controller (GX)

– Interface to Host Channel Adapter (HCA) Memory Controller (MC)

– Interface to controller on memory DIMMs

– Supports RAIM design

Chip Area – 512.3mm2 – 23.5mm x 21.8mm– 8093 Power C4’s– 1134 signal C4’s


– 13 layers of metal– 3.5 km wire

1.4 Billion Transistors


L4 Cache(24MB)

Perv

ClkRepower

PLL

L4 ControllerFabric

IOsDataBit-

Stack

ETR/TOD

L4 Cache(24MB)

L4 Cache(24MB)

L4 Cache(24MB)

Fabric

IOs

DataBit-

Stack Perv Perv

z196 SC Chip Detail


► 13 layers of metal

Chip Area – 478.8mm^2► 24.4mm x 19.6mm

► 7100 Power C4’s

► 1819 signal C4’s

1.5 Billion Transistors► 1 Billion cells for eDRAM

eDRAM Shared L4 Cache

► 96 MB per SC chip

► 192 MB per Book

6 CP chip interfaces

3 Fabric interfaces

2 clock domains



z196 Multi-Chip Module (MCM) Packaging

96mm x 96mm MCM►103 Glass Ceramic layers►8 chip sites►7356 LGA connections►20 and 24 way MCMs►Maximum power used by MCM is 1800W

CMOS 12s chip Technology

► PU, SC, S chips, 45 nm

► 6 PU chips/MCM – Each up to 4 cores ● One memory control (MC) per PU chip● 23.498 mm x 21.797 mm ● 1.4 billion transistors/PU chip● L1 cache/PU core

– 64 KB I-cache– 128 KB D-cache

● L2 cache/PU core– 1.5 MB

● L3 cache shared by 4 PUs per chip – 24 MB

● 5.2 GHz

► 2 Storage Control (SC) chip● 24.427 mm x 19.604 mm● 1.5 billion transistors/SC chip● L4 Cache 96 MB per SC chip (192 MB/Book)● L4 access to/from other MCMs

► 4 SEEPROM (S) chips● 2 x active and 2 x redundant● Product data for MCM, chips and other engineering information

► Clock Functions – distributed across PU and SC chips● Master Time-of-Day (TOD) function is on the SC

PU 0PU 2

SC 0SC 1

PU 1

S00

S01

PU 5PU 3 PU 4

S10

S11


z114 SCM Vs z196 MCM Comparison – Same PU and SC Chip

Single PU Chip

without heatsink

MCM– 96mm x 96mm in size– 6 PU chips per MCM

• Quad core chips with 3 or 4 active cores• PU Chip size 23.498 mm x 21.797 mm

– 2 SC chips per MCM• 96 MB L4 cache per chip • SC Chip size 24.427 mm x 19.604 mm

– Up to 4 MCMs for System

z196 Multi Chip Module (MCM) PU SCM

– 50mm x 50mm in size – fully assembled– Quad core chip with 3 and 4 active cores– 2 PU SCMs for M05 and 4 PU SCMS for M10– PU Chip size 23.498 mm x 21.797 mm

SC SCM– 61mm x 61mm in size – fully assembled– 1 SC SCM for M05, 2 SC SCMs for M10– 96 MB L4 cache per chip – SC Chip size 24.427 mm x 19.604 mm

z114 SCMs

Single SC Chip

without heatsinkPU 0PU 2

SC 0SC 1

PU 1

S00

S01

PU 5PU 3 PU 4

S10

S11

z114TLLB28


z196 PU chip, SC chip and MCM

z196Quad Core PU CHIP

MCM

BOOK 96 MB

SC CHIPFront View

Front ViewFanouts


z196 Book LayoutMCM @ 1800W

Refrigeration Cooled orWater Cooled

Backup Air Plenum

8 I/O FAN OUT 2 FSP

3x DCA 14X DIMMs100mm High

16X DIMMs100mm High

11 VTM Card Assemblies8 Vertical3 Horizontal

RearFront

DCA Power Supplies

Fanout

Cards

Coolingfrom/to MRU

MCM

Memory

Memory


z196/z114 PU core

Each core is a superscalar, out of order processor with these characteristics:► Six execution units

● 2 fixed point (integer), 2 load/store, 1 binary floating point, 1 decimal floating point► Up to three instructions decoded per cycle (vs. 2 in z10)

► 211 complex instructions cracked into multiple internal operations

● 246 of the most complex z/Architecture instructions are implemented via millicode► Up to five instructions/operations executed per cycle (vs. 2 in z10)

► Execution can occur out of (program) order

● Memory address generation and memory accesses can occur out of (program) order● Special circuitry to make execution and memory accesses appear in order to

software► Each core has 3 private caches

● 64KB 1st level cache for instructions, 128KB 1st level cache of data● 1.5MB L2 cache containing both instructions and data


z196 New Instruction Set Architecture

Re-compiled code/apps get further performance gains through 100+ new instructions

High-Word Facility (30 new instructions)

► Independent addressing to high word of 64-bit GPRs

► Effectively provides compiler/ software with 16 additional 32-bit registers

Interlocked-Access Facility (12 new instructions)

► Interlocked (atomic) load, value update and store operation in a single instruction

► Immediate exploitation by Java

Load/Store-on-Condition Facility (6 new instructions)

► Load or store conditionally executed based on condition code

► Dramatic improvement in certain codes with highly unpredictable branches

Distinct-Operands Facility (22 new instructions)

► Independent specification of result register (different than either source register)

► Reduces register value copying

Population-Count Facility (1 new instruction)

► Hardware implementation of bit counting ~5x faster than prior software implementations

Integer to/from Floating point converts (21 new instructions)


OOO yields significant performance benefit for compute intensive apps through►Re-ordering instruction execution

● Later (younger) instructions can execute ahead of an older stalled instruction►Re-ordering storage accesses and parallel storage accesses

OOO maintains good performance growth for traditional apps

z196 Out of Order (OOO) Value

L1 miss

Instrs

1

2

3

4

5

Time

In-order core execution Out-of-order core execution

L1 miss

TimeExecution

Storage access


z196 Out of Order Detail

Out of order yields significant performance benefit through► Re-ordering instruction execution

● Instructions stall in a pipeline because they are waiting for results from a previous instruction or the execution resource they require is busy

● In an in-order core, this stalled instruction stalls all later instructions in the code stream ● In an out-of-order core, later instructions are allowed to execute ahead of the stalled instruction

► Re-ordering storage accesses● Instructions which access storage can stall because they are waiting on results needed to compute

storage address ● In an in-order core, later instructions are stalled● In an out-of-order core, later storage-accessing instructions which can compute their storage address

are allowed to execute

► Hiding storage access latency● Many instructions access data from storage ● Storage accesses can miss the L1 and require 10 to 500 additional cycles to retrieve the storage data● In an in-order core, later instructions in the code stream are stalled● In an out-of-order core, later instructions which are not dependent on this storage data are allowed to

execute


z196 Redundant Array of Independent Memory (RAIM)

System z10 EC memory design:► Four Memory Controllers (MCUs) organized in two pairs, each MCU with four channels

► DIMM technology is Nova x4, 16 to 48 DIMMs per book, plugged in groups of 8

► 8 DIMMs (4 or 8 GB) per feature – 32 or 64 GB physical memory per featureEquals 32 or 64 GB for HSA and customer purchase per feature

► 64 to 384 GB physical memory per book = 64 to 384 GB for use (HSA and customer)

z196 memory design:► Three MCUs, each with five channels. The fifth channel in each z196 MCU is required to implement memory

as a Redundant Array of Independent Memory (RAIM). This technology adds significant error detection and correction capabilities. Bit, lane, DRAM, DIMM, socket, and complete memory channel failures can be detected and corrected, including many types of multiple failures.

► DIMM technology is SuperNova x81, 10 to 30 DIMMs per book, plugged in groups of 5 5 DIMMs (4, 16 or 32 GB) per feature – 20, 80 or 160 GB physical RAIM per featureEquals 16, 64 or 128 GB for use per feature. RAIM takes 20%. (There is no non-RAIM option.)

► 40 to 960 GB RAIM memory per book = 32 to 768 GB of memory for use (Minimum RAIM for the M15 is 60 GB = 48 GB = 16 GB HSA plus 32 GB customer memory)

For both z196 and z10► The Hardware System Area (HSA) is 16 GB fixed, outside customer memory

► In some cases, offering granularity can prevent purchase of all available memory in a book


Ch4Ch3

Ch2Ch1

AS

IC

AS

IC

Ch0

DIMM

CLKDiff

CLKDiff

CRC

CRC

DRAM

X

X

X

X

Layers of Memory Recovery

ECC Powerful 90B/64B Reed Solomon code

DRAM Failure Marking technology; no half sparing

needed 2 DRAM can be marked Call for replacement on third DRAM

Lane Failure CRC with Retry Data – lane sparing CLK – RAIM with lane sparing

DIMM Failure (discrete components, VTT Reg.)

CRC with Retry Data – lane sparing CLK – RAIM with lane sparing

DIMM Controller ASIC Failure RAIM Recovery

Channel Failure RAIM Recovery

MCU0

EC

C

RAIM

XX

X

2- Deep Cascade Using Quad High DIMMs

z196 RAIM Memory Controller Overview


STIz990/z890

STIz9

InfiniBandz10/z196/z114

STIz900/z800

STI: Self-Timed Interconnect

6 GBps

2.7 GBps

2 GBps

1 GBps

System z I/O Subsystem Internal Bus Interconnect Speeds (GBps)

PCIez196/z114Sep 2011

8 GBps


For Clustering

* I/O cage for z196 only

Within z196/z114 and to zBX PCIe I/O Infrastructure I/O Drawer and I/O Cage1 Intraensemble data network (IEDN) Intranode management network (INMN)

To the Data

HCA-3 InfiniBand® Coupling Links– 12x InfiniBand (improved

performance with 12x IFB3 protocol)

– 1x InfiniBand (4 ports) ISC-3 (peer mode only) IC (define only) STP

– Improved time coordination for zBX components

HMC Location to run Unified Resource Manager – including

monitoring CPU, energy, workload performance Host of the ensemble – controlling all functions of

the ensemble Primary with Alternate needed for DR

FICON Express8S (PCIe-based) ESCON

– Up to 240 maximum

Connectivity Enhancements New features with big performance boost

To the Network OSA-Express4S (PCIe-based)

– 10 Gigabit Ethernet LR and SR– 1 Gigabit Ethernet SX and LX

OSA-Express3– 1000BASE-T Ethernet


ISC-3, 2 GbpsUp to 100 km

IBM eserver™ zSeries® 800, 900, 890 and 990, (z800, z900 z890,z990)

Not supported!

z10 EC and z10 BC IFB, ISC-3,

12x IFB, 3 GBpsUp to 150 meters

12x IFB, 6 GBps150 meters

IFB z9-to-z9 NOT supported

z9 EC and z9 BC S07 IFB, ISC-3

1x IFB, 5 Gbps10/100 km

ISC-3, 2 GbpsUp to 100 km

ISC-3Up to 100 km

1x IFB, 5 Gbps10/100 km

12x IFB 6 GBps

150 meters

Note: ICB-4s and ETRNOT supported on z114 or z196

z196

12x IFB3 6 GBps

150 meters

z114

Increased linkcapabilities

Parallel Sysplex coexistence of Servers/CFs and coupling connectivity


Cryptographic enhancements on zEnterprise► Cryptography is in the “DNA” of System z hardware with Processor and

Coprocessor based encryption capabilities

● Processor Clear Key for bulk encryption – key material visible in storage

● System z exclusive Protected Key CPACF helps to protect sensitive keys from inadvertent disclosure -- not visible to application or OS

► Crypto Express3 enhanced to support key ANSI and ISO standards for the banking, finance and payment card industry.

► Enhanced display of cryptographic cards and simplified card configuration and management capabilities via the Trusted Key Entry workstation (TKE).

► Simplified master key management with ICSF enhancements providing a single point of administration within an z/OS Sysplex.

► Continued support for the next generation of public key technologies , ECC support is ideal for constrained environments such as mobile devices.

► Crypto Express3 Coprocessor FIPS 140-2 Level 4 hardware evaluation.

PR/SM™ designed for EAL5 certification.

Policy driven flexibility to add capacity to real or virtual processors.

High Availability, Backup and Disaster Recovery solutions► Leverage z114 and z196 as part of the new GDPS®/ active-active

continuous availability solution

Enhancing System z world-class security and business resiliency


Top Exit cabling is designed to provide an additional option and increased flexibility to help increase air flow in a raised-floor environment

– For I/O cabling only (ESCON, FICON and Ethernet).

– Not used for power cables– Increases width of System by 15.2 cm (6

inches) – Overhead cabling feature adds 43.13 Kg (95

lbs) to the frame weight

I/O Cabling Raceways

Overhead I/O Cabling Option


Top ExitI/O

And Top ExitPower

Floor Type Independent

Bottom cover

Top ExitI/O and

PowerUnder

TheFloor

RF Tailgate

I/O and

PowerUnder The Floor

RF Tailgate

Power and I/OBottom,

but Above

The Floor

NRF Tailgate

Raised FloorRaised FloorNon-Raised FloorNon-Raised Floor

OverheadCable Tray System

Power Cords

I/O Cables

1 2 54

Floor Independent(Raised or Non-Raised)

Top ExitPowerand I/OUnder The Floor

RF Tailgate

3

Preferred in Non-Raised Floor environments

Floor and Cabling Configurations options


System ComparisonsSystem I/O Bandwidth

MemoryPCI for 1-Way

Engines

782256 GB

128 GB/Sec

5-Way

256 GB

72 GB/Sec

5-Way

67364 GB

4-Way

47434417032 GB

21.6 GB/Sec

16 GB/Sec

6 GB/Sec

z114

z10 BC

z9 BC

z890

z800

Notes:1. Capacity shown is for CPs only2. z9, z10 and z114 have additional PUs

which can be used as Speciality Engines


Balanced SystemCPU, nWay, Memory,

I/O Bandwidth*

Memory

3 TB**

System I/O Bandwidth384 GB/Sec*

PCI for1-way

12021.5 TB**

64-way

920

80-wayProcessors

288 GB/sec*

600512 GB

54-way

96 GB/sec

450256 GB

32-way

24 GB/sec

30064 GB

16-way

* Servers exploit a subset of its designed I/O capability** Up to 1 TB per LPARPCI – Processor Capacity Index

172.8 GB/sec*

z10 EC

z9 EC

zSeries 990

zSeries 900

z196 - 2011

IBM System z: - Design Comparison for High End Systems


z9 EC

z196

z10 EC™

z10 BC™

z9® BC Continuing to protect your investment with two generation upgrades

Full upgradeability within each server family

Temporary or permanent growth when you need it

z114 offers two models:

► M05 and M10.

► M05 is upgradeable to M10

z114 (M10) is upgradeable to the z196 (M15 Air cooled only)

z114

Providing investment protection while enabling growth


Operating System Support

Currency is key to operating system support and exploitation of future servers

The following are the minimum operating systems planned to run on z114 aand z196

Operating System

Supported levels

z/OS • V1.11, 1.12, 1.13 or higher

• V1.10* (requires Lifecycle Extension after September 30, 2011)

• V1.8 and 1.9, in Lifecycle Extension

• zBX Ensemble support: z/OS V1.10* or higher

Linux • Red Hat RHEL 5

• Novell SUSE SLES 11

z/VM • V5.4

• zBX Ensemble support: V6.1

z/VSE • V4.2

• zBX Ensemble support V4.3 or higher

z/TPF • V1.1 or higher

* z/OS 1.10 support ends Sept. 30, 2011, and Lifecycle Extension is required after that date.


Introducing New Hybrid Capabilities

To integrate, support and manage an expanding portfolio of operating environments and workloads


2458-002

Fibre ChannelDisk Storage

Machine Type/Model 2458-002– One Model with 5 configurations for IBM Smart Analytics Optimizer

Racks – Up to 4 (B, C, D and E)– 42U Enterprise, (36u height reduction option)– 4 maximum, 2 chassis/rack– 2-4 power line cords/rack – Non-acoustic doors as standard– Optional Rear Acoustic Door– Optional Rear Door Heat Exchanger (conditioned water required)

Chassis – Up to 2 per rack– 9U BladeCenter – Redundant Power, cooling and management modules– Network Modules– I/O Modules

Blades (Maximum 112 in 4 racks)– IBM Smart Analytics Optimizer Blades (0 to 7 to 56)

– Can not mix other Blades in the same Chassis– Customer supplied POWER7 Blades (0 to 112)– Customer supplied IBM System x Blades* (0 to 28)– IBM WebSphere DataPower Integration Appliance XI50 for zEnterprise, M/T 2462-

4BX (up to 28 – double width)– Non-IBM Smart Analytics Optimizer Blades can be mixed in the same chassis

Management Firmware– Unified Resource Manager

Top of Rack (TOR) Switches - 4– 1000BASE-T intranode management network (INMN)– 10 GbE intraensemble data network (IEDN)

I/O – 8 Gb Fibre Channel (FC) connected to customer supplied disks– IBM Smart Analytics Optimizer uses DS5020 disks

– DS5020s not shared with Customer supplied Blades


zBX Overview


IBM zEnterprise family

Announced 7/10 – Server w/ up to 96 PU cores5 models – Up to 80-wayGranular Offerings for up to 15 CPsPU (Engine) Characterization

– CP, SAP, IFL, ICF, zAAP, zIIPOn Demand Capabilities

– CoD, CIU, CBU, On/Off CoD, CPEMemory – up to 3 TB for Server and up to 1 TB per LPAR

– 16 GB Fixed HSAChannels

– Four LCSSs– 3 Subchannel Sets– MIDAW facility– Up to 240 ESCON channels– Up to 288 FICON channels– FICON Express8 and 8S– zHPF– OSA 10 GbE, GbE, 1000BASE-T– InfiniBand Coupling Links

Configurable Crypto Express3Parallel Sysplex clusteringHiperSockets – up to 32Up to 60 logical partitionsEnhanced AvailabilityUnified Resource ManagerOperating Systems

– z/OS, z/VM, z/VSE, z/TPF, Linux on System z

Announced 7/10Model 002 for z196 or z114zBX Racks with:

– BladeCenter Chassis– N + 1 components– Blades– Top of Rack Switches– 8 Gb FC Switches– Power Units– Advance Management Modules

Up to 112 Blades– IBM Smart Analytics Optimizer Solution– POWER7 Blades– IBM System x Blades– IBM WebSphere DataPower Integration

Appliance XI50 for zEnterprise (M/T 2462-4BX)

–Operating Systems– AIX 5.3 and higher– Linux for x Blades– Microsoft Windows for x Blades*

–Hypervisors– PowerVM Enterprise Edition– Integrated Hypervisor for System x


IBM zEnterprise 196 (2817) IBM zEnterprise Blade Extension (2458)

IBM zEnterprise 114 (2818)

Announced 07/11 2 models – M05 and M10

Up to 5 CPsHigh levels of Granularity available

– 130 Capacity IndicatorsPU (Engine) Characterization

– CP, SAP, IFL, ICF, zAAP, zIIPOn Demand Capabilities

– CoD, CIU, CBU, On/Off CoD. CPEMemory – up to 256 GB for Server

– 8 GB Fixed HSAChannels

– Two LCSSs– 2 Subchannel Sets– MIDAW facility– Up to 240 ESCON channels– Up to 128 FICON channels– FICON Express8 and 8S – zHPF– OSA 10 GbE, GbE, 1000BASE-T– InfiniBand Coupling Links

Configurable Crypto Express3Parallel Sysplex clusteringHiperSockets – up to 32Up to 30 logical partitionsUnified Resource ManagerOperating Systems

– z/OS, z/VM, z/VSE, TPF, z/TPF, Linux on System z


If you …

…want the flexibility to manage across heterogeneous platform – including z/OS,

AIX, Linux on System x, Windows on System x1

…are looking for an entry level mainframe with options for traditional

capacity settings

… need a smaller mix of special engines (*zAAP on zIIP great option here!)

… have smaller Coupling and/or I/O attachment requirements

… need the lowest cost application development environment.

If you …

…want the flexibility to manage across a heterogeneous platform

…want to replace your server with one that has the same number of engines –

but would like more IFLs, zAAPs or zIIPs

… want to replace your standalone coupling facility or Linux only server with a machine that provides engine, memory and I/O scale out capabilities

… have future growth needs, but prefer grow in smaller increments and want to avoid disruptive outage during upgrade

If you …

…want the flexibility to manage across a heterogeneous platform

… have a large mainframe capacity requirement or desire for massive

consolidation – scale to over 52,000 MIPS in one footprint

… have a large disk installment so in turn have large I/O requirements

… need new ways to address your ‘green’ requirements – like water cooling

and static power save mode

… have a large CBU requirement – and like the control of having your disaster recovery site right in your own shop.

A zEnterprise for EveryoneFreedom to choose the “right sized” mainframe to fit your needs.

The z114 M05 may be the perfect option.

The z114 M10 is just what you need.

The enhanced z196 is right for you.


44%lower cost per credit card transaction

20% lower cost per airline passenger

31%lower IT spend per consumer loan

26%

lower cost per new vehicle

25%

lower cost per mega watt hour produced

25% lower cost perretail store

24% lower cost per hospital bed

23% lower cost per barrel of oil*Based on Dr. Howard Rubin Study*Based on Dr. Howard Rubin Study

System z improves IT efficiency across industries.*


Thank you!ibm.com/systems/z

© 2011 IBM Corporation1 Grzegorz T. Kolecki Senior Client Technical Specialist Nowe oblicze...

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Transcript of © 2011 IBM Corporation1 Grzegorz T. Kolecki Senior Client Technical Specialist Nowe oblicze...