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2011 Altera CorporationPublic The Trends in Programmable Solutions SoC FPGAs for Embedded Applications and Hardware-Software Co-Design Misha Burich Senior VP & CTO Altera Corporation June 8, 2012 Slide 2 2011 Altera CorporationPublic Agenda Market Drivers and Technology Enablers Embedded Computing & FPGAs The emergence of SoC FPGAs Hardware-Software Programmability Summary 2 Slide 3 2011 Altera CorporationPublic Market Drivers and Enabling Embedded Technologies 3 Slide 4 2011 Altera CorporationPublic 4 Most Markets Rely on Embedded Processing Communications and Broadcast Consumer and Automotive Test and Medical Computer and Storage Military and Industrial Slide 5 2011 Altera CorporationPublic Enabling Technologies: 200X-201X Moores law enabled high density programmable platforms 5 Fine-Grained Massively Parallel Heterogeneous Arrays FPGAs DSPs CPUs Single Cores Coarse-Grained Massively Parallel Processor Arrays Multi-Cores Coarse-Grained CPUs and DSPs Multi-Cores Arrays Slide 6 2011 Altera CorporationPublic The Age of Systems-On-Chip ARM based SoCs by Apple, Nvidia, Qualcomm, TI, others 6 SoC FPGAs by Altera, Xilinx, others Slide 7 2011 Altera CorporationPublic Also, There Is More-Than-Moore System-in-package multi-die integration POP, 2.5D, 3D, micro-bumps, through-silicon-vias (TSV) Example: Intels integration of Atom processor with Alteras FPGA E600C 7 Slide 8 2011 Altera CorporationPublic Embedded Computing on FPGAs 8 Source: Gartner Sept 2010 50% FPGA Design Starts Soon, a majority of FPGA designs will feature an embedded processor Slide 9 2011 Altera CorporationPublic Alteras Embedded Initiative 9 Cortex-M1MP32Cortex A9 Single FPGA Design Flow for a Broad Array of Industry- Leading Embedded Processors ColdFire V1 Atom E6XXC FPGA Design Software System Integration Tool SOFT CORE PROCESSORS SoC (PiP) SoC FPGA Slide 10 2011 Altera CorporationPublic Modern FPGA: Massively Parallel 10 Million + Logic Elements Multi-billion Transistors Thousands of 20-Kbit Memory Blocks Thousands of MAC DSP Blocks Many External Memory, LVDS, And Transceivers IO Blocks Slide 11 2011 Altera CorporationPublic FPGA : Ultimately Configurable Multicore 11 Processor Memory Processor Memory Processor Memory Can implement many coarse- grained processors Exploiting the fine grained parallelism of the FPGA for acceleration Possibly heterogeneous Optimized for different tasks Customizable to suit the needs of a particular application Slide 12 2011 Altera CorporationPublic An Example: Crescendo Networks A Programmable Eight-Processor Architecture Using Embedded Soft Processor Nios II On a Single FPGA For Layer 4/7 Applications 12 Slide 13 2011 Altera CorporationPublic Hardware-Software Co-Design for SoC FPGAs 13 Slide 14 2011 Altera CorporationPublic SoC FPGA Programming Models Traditional FPGAs programming model is RTL State machines, datapaths, arbitration, buffering, etc. Also need a programming model that represents an FPGA as: Processor with hardware accelerators Configurable multi-core device 14 Slide 15 2011 Altera CorporationPublic C/C++ Compilers for FPGAs Several commercial offerings C/C++/System C High-Level-Synthesis to RTL C-to-Silicon Compiler (Cadence) Impulse C (Impulse Accelerated Technologies) Catapult C (Mentor) SynphonyC (Synopsys) AutoESL (now Xilinx) Cynthesizer (Forte), NEC 15 Synthesized blocks Slide 16 2011 Altera CorporationPublic Integration of Embedded Processors and Hardware Accelerators in FPGAs: C2H 16 Program Memory Processor: Nios II, ARM DMA Accelerator DMA Data Memory Arbiter Data Memory Arbiter Qsys Slide 17 2011 Altera CorporationPublic Identify the Software Bottleneck main () { variable declarations init(); while (!error && got_data()) { do_user_interface(); gather_statistics(); if (got_new_data()) d_transform(in_buf, out_buf); check_for_errors(); } cleanup(); } 17 Execution Time Slide 18 2011 Altera CorporationPublic Compile C Function Into Hardware d_transform (int *t, int *p) { setup code for (i = 0; i < Buf_Size; i++) { loop overhead *t = transform (*p); t++; p++; } exit code } 18 Hardware Accelerator Hardware Accelerator Use HLS Compiler Or, Write the Function in HDL Slide 19 2011 Altera CorporationPublic The Result main () { variable declarations init(); while (!error && got_data()) { do_user_interface(); gather_statistics(); if (got_new_data()) d_transform(in_buf, out_buf); check_for_errors(); } cleanup(); } 19 Execution Time d_transform Slide 20 2011 Altera CorporationPublic OpenCL Approach to SoC FPGA Programming 20 Slide 21 2011 Altera CorporationPublic What is OpenCL OpenCL is a programming model developed by the Khronos group to support multi-core programming and silicon acceleration An industry consortium creating open API standards Commitment to royalty-free standards 21 Slide 22 2011 Altera CorporationPublic OpenCL Portability 22 Source: RapidMind Slide 23 2011 Altera CorporationPublic OpenCL Structure Natural separation between the code that runs on accelerators and the code that manages those accelerators The host code is pure software that can be executed on any sort of conventional microprocessor Soft processor, Embedded hard processor, external x86 processor The kernel code is C with a minimal set of extensions that allows for the specification of parallelism and memory hierarchy 23 Slide 24 2011 Altera CorporationPublic OpenCL Host Program Pure software written in standard C Communicates with the Accelerator Device via a set of library routines which abstract the communication between the host processor and the kernels 24 main() { read_data_from_file( ); maninpulate_data( ); clEnqueueWriteBuffer( ); clEnqueueTask(, my_kernel, ); clEnqueueReadBuffer( ); display_result_to_user( ); } Copy data from Host to FPGA Ask the FPGA to run a particular kernel Copy data from FPGA to Host Slide 25 2011 Altera CorporationPublic OpenCL SoC FPGA Target 25 DDR* Interface IP Application Specific External Protocols Accelerator / Datatapath Computation Accelerator / Datatapath Computation Host Program Kernels Processor Memory Processor Memory Processor Memory Slide 26 2011 Altera CorporationPublic Summary 26 The era of SoC programmable solutions The age of SoC FPGAs The era of innovation Massively parallel embedded programmable solutions The new embedded software era Embedded hardware-software co-design and parallel programming Slide 27 2011 Altera CorporationPublic ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the United States and are trademarks or registered trademarks in other countries. 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