© 2009 Xilinx, Inc. All Rights Reserved Part 2 Virtex-6 and Spartan-6 HDL Coding Techniques.

© 2009 Xilinx, Inc. All Rights Reserved

Part 2

Virtex-6 and Spartan-6 HDL Coding Techniques

Copyright 2009 Xilinx

Welcome

If you are new to FPGA design, this module will help you code properly for Spartan-6 and Virtex-6 register resources

These design techniques promote fast and efficient FPGA designs


After completing this module, you will able to:

Code your design so you can infer more of the dedicated hardware resources

Avoid the most common coding mistakes which hurt device utilization

Reduce your dependence on global resets by taking advantage of the Global Set/Reset net (GSR)


Tactics to Meet Timing

Use as many of the dedicated resources as possible (SRLs, DSP slices, and block RAMs)– Understanding the features of the resource is essential if

you are going to infer the resource

– This is critical to reducing the number of LUTs and registers in your FPGA design and increasing the amount of dedicated hardware you infer

One of the most effective ways to reduce power in FPGAs is to reduce the number of LUTs and FFs– One of the side benefits of these techniques is that they

will allow you to improve performance and device utilization


DSP Slice Uses a Synchronous Reset

Each DSP slice effectively has more than 250 registers– None have an asynchronous reset

The DSP slice is more versatile than most realize– It can be used for multipliers, add/sub, MACC, counters (with

programmable terminal count), comparators, shifters, multiplexer, pattern match, and many other logic functions

Many designs that run out of slices are not fully utilizing their DSP slice resources– Synthesis tools will infer the DSP slice resources for multipliers, but

they are not smart enough to infer other functions•Can control synthesis use with attributes, but NOT if an asynchronous reset

is used


BRAM Uses a Synchronous Reset

Block RAMs obtain minimum clock-to-output time by using their output register– Output registers only have synchronous resets

Unused block RAMs can be used for many alternative purposes– ROMs, large LUTs, complex logic, state machines, deep-shift registers,

etc.

Using unused block RAMs for other purposes can free up hundreds of flip-flops– Using the block RAM in dual-port mode allows for greater utilization of

this resource

Many designs that run out of slices are not fully utilizing the block RAM resources– Synthesis tools are not yet smart enough to infer less obvious functions


Synchronous Sets/Resets

Synchronous Sets and Resets give the tools more flexibility– Can improve timing and device utilization

Synthesis could choose to move low-fanout synchronous resets from a control signal to the datapath to free up more registers– Synthesis tools can do this, but it may depend on synthesis settings

and may not be on by default• XST has a Use Synchronous Reset synthesis option (on by default)

– The Xilinx implementation tools cannot change what is synthesized

This could allow packing of a register into a slice previously not possible

D

S

Low Fanout


Synchronous Sets/Resets

Synchronous sets/resets make FPGA designs more reliable

Synchronous sets/resets are automatically timed– Do not need any special timing constraints

– Do not need special switches or setting to analyze timing

– Synchronous reset nets are often the most critical net in a design

Synchronous sets/resets are inherently more predictable – Less susceptible to accidentally missing timing, runt pulses, or other

phenomenon from upsetting logical functionality

– Less prone to a race condition• Release of an asynchronous signal may not always have predictable results

Tip: Synchronous resets enable your design to require minimal testing


Caveats to Synchronous Sets/Resets Synchronous resets increase the number of constrained

paths, may make timing more difficult, the design larger, and result in longer run times

Why?– The implementation tools automatically time synchronous reset paths

– This can result in• More timing paths to analyze and meet timing

• On average ~five percent increase in the number of timing paths

• More replication of design resources

• With some synthesis tools this will use fewer SRLs, block RAM, DSP slices, and other dedicated hardware


Changing to Synchronous Resets

All new code should use synchronous resets when a reset is necessary

For existing code, you have three choices– Leave alone

• Acknowledge the possible critical drawbacks of asynchronous resets

– Use synthesis switch (dangerous!)

• Not the same as changing to synchronous reset• This can make the synthesis result different from the behavioral simulation

– Recommended: manually (or use a script) to change the asynchronous reset to synchronous

• Removing the top-level reset port does not get the same result as removing the reset from your code

Synplify:syn_clean_reset

XST:-async_to_sync YES


Resets

Two kinds of resets – Global and LocalGlobal…usually used to reset after configuration

• This is done by default after configuration of the FPGA and does not need to be coded into the design

– Access to this net is done with the GSR port from the Startup component (only necessary if you wish to perform a global reset s second time)

– Note…if you are coding in a global reset into your HDL you are actually coding in a second reset

• Some ASIC technologies require at most an initialization when they power up. But FPGAs do not require a reset.

Local…used as a standard part of some components behavior

• FSM, counters, etc


Getting By

Some designs can get away without any resets but many designs need some resets– Very few designs require resets on all registers, but most designers

want a global reset after initialization• Most ASIC emulation also requires a described reset on every register.

• Implement this global reset with the built-in Global Set/Reset (GSR) GSR is good for initializing the values of your synchronous elements (FFs,

Block RAMs)

Delay of GSR is slow (3 clock cycles after configuration) so use it after configuration, but don’t reset again unless you can tolerate the entire design being reset


Global Reset Net

The GSR input is an active-high global set/reset net that is active at the end of configuration– It uses a dedicated routing resource for signal

distribution• Saves general interconnect

– It can also be used to restore the initial state of the FFs in the FPGA at any time

• The intial state is communicated with an INIT attribute• It drives the output FFs for each block RAM, but does not

affect the contents of each memory or SRL

– It is connected to all synchronous elements through a wired OR gate

• This allows a local reset to also drive the FF’s set/reset port


Startup Instantiation (VHDL)

VHDL and Verilog instantiations are available from the Xilinx Unified Libraries Guide

Library UNISIM;use UNISIM.vcomponents.all;-- STARTUP_VIRTEX6: Virtex-6 Configuration Start-Up Sequence Interface-- Virtex-6-- Xilinx HDL Libraries Guide, version 12.1STARTUP_VIRTEX6_inst : STARTUP_VIRTEX6generic map (PROG_USR=>"FALSE“) -- Activate program event security featureport map (…

CLK => CLK, -- 1-bit User start-up clockGSR => GSR, -- 1-bit Active high Global Set/Reset signalGTS => GTS, -- 1-bit Active high Global 3-State signal…);

-- End of STARTUP_VIRTEX6_inst instantiation


Inferring an Initialization (XST only)

If you have a reset, you can initialize all registers in VHDL / Verilog code

SR will cause the flip-flop to be set to the state inferred here– Inference is supported only for data types std_logic, bit_vector, bit, but

NOT integer

This is helpful for RTL simulation of the design– If it functions during simulation, it should function on the FPGA

– Note…if you design without a reset in your design, you still get a free global reset

VHDL:

signal my_regsiter : std_logic_vector (7 downto 0) := (others <= ‘0’);

Verilog:

reg [7:0] my_register = 8’h00;


No Reset is Best

Synthesis can infer SRL-based shift registers– But only if no resets are used (otherwise flip-flops are wasted)

– Or, the synthesis tool can emulate the reset• This will uses extra resources and take extra clock cycles to set up (not what

you want)


No Reset is Best

Designs without resets have fewer timing paths– By an average of 18 percent fewer timing paths

Results in less run time

Improved performance

Less memory necessary during PAR

Tip: NO reset builds a faster design and saves run time


Use the GSR

Routing can be considered one of the most valuable resources

Resets compete for the same resources as the rest of the active signals of the design – Including timing-critical paths

– More available routing gives the tools a better chance to meet your timing objectives

Tip: Using the GSR saves routing and improves design speed


Block RAM

Avoid “read before write” mode for fastest performance by instantiating your memory with the CORE Generator™ tool

Synplify and other third-party synthesis tools can insert bypass logic to prevent a possible mismatch error between your RTL and hardware behavior– Intended to force RAM outputs to a known value when read and

write operations occur on the same memory cell

– If you know this will never happen you can prevent this logic from being added and damaging your performance with an attribute

• Attribute syn_ramstyle of mem : signal is “no_rw_check”;


Clock Enable

Control the use of clock enables from the code– Code them only when needed

– If a low-fanout CE is necessary, use synthesis attributes to control the use of control signals at the signal or module level

• Do not use global switches to turn off the use of CEs Results in an average of 25-percent LUT increase

– Consider using alternative coding methods for low-fanout clock enables

VHDL: Q <= ((not CE) AND A) OR (CE AND Q);

Verilog: Q <= (~CE & A) | (CE & Q);

VHDL:if (CE=‘1’) then Q <= A;

Verilog:if (CE=‘1’) Q <= A;

This will map the CE

to the control port

This will map the CE to a

LUT input


Global Clock Enable

To gate entire clock domains for power reduction, use the clock-enabled global buffer resource BUGCE or the BUFHCE– For applications that only pause the clock on small areas of the

design, use the clock enable pin of the FPGA register

Tip: This will save general routing resources


DSP Slice

Use adder chains instead of adder trees– Adder trees tend to have varying size

• This usually makes larger adders in the last stages, which increases logic levels

– Spartan-6 and Virtex-6 FPGAs uses adder chains which obtain peak performance and use minimal power

• Requires pipelining• Adds latency

Adder Tree

Adder Tree

Adder ChainAdder Chain


Synthesis Options

Over-constraining during synthesis can significantly increase register use– Seen as an average increase from 1–5 percent

– Do NOT over-constrain during synthesis

Global optimization can lead to mixed results– Can achieve ~10 percent flip-flop reduction

• Gives back much of the utilization benefits (and sometimes more) due to control signals

FSM optimization– Turning off FSM optimization can yield a small flip-flop savings

– One-hot encoding is not as useful

Do NOT use slice or LUT compression switches– In some cases, latch-thrus are used and consume registers


Synthesis Options

Replicate registers with high fan-out– This allows high fan-out logic to be moved closer to destinations

– This can be determined from a timing report

– Manual duplication or replication constraints with the synthesis tools should be applied

Retiming option should be used, especially if design has been pipelined– Pipelining is still encouraged


I/O Registers

IOB registers provide fixed setup and clock-to-output times– Fastest way to capture input data and clock data off the

device

IOB register can make it difficult to meet internal timing– Their use can lengthen route delays to internal logic

– Only use IOB registers when it is necessary to meet I/O timing• It is best to allow your synthesis tool to put registers into

IOBs based on timing constraints (if your tool supports this).

• Otherwise complete the following steps…

1) Disable global I/O register usage in your synthesis tool

2) Disable the Map option to pack registers into IOBs (PAR)

3) Selectively move registers into IOB with a UCF attribute

Tip: Use IOB registers when necessary to meet I/O timing


Summary

Avoid asynchronous resets on block RAMs (the block RAM’s output register only supports a synchronous reset)

Avoid asynchronous resets on DSP slice resources (their flip-flops only support a synchronous reset)

IOB registers can make it more difficult to meet internal timing– Use IOB registers only for improving IO timing

Xilinx recommends NOT using the synthesis option to convert asynchronous resets to synchronous


Summary

Synthesis tools can move synchronous resets from control ports to the data path

Avoid the use of global resets– Initialize all registers from your HDL

– If you need a global reset use the Startup_Virtex6 or the Startup_Spartan6 primitive to access the GSR net

– If you can remove a global reset, you will save a lot of routing and build a faster design

Avoid resets on SRLs (no reset functionality)


Where Can I Learn More?

Software Manuals– Start Xilinx ISE Design Suite 12.1 ISE Design Tools

Documentation Software Manuals

– This includes the Synthesis & Simulation Design Guide• This guide has example inferences of many architectural resources

– XST User Guide• HDL language constructs and coding recommendations

– Software User Guides and software tutorials

Xilinx Training– www.xilinx.com/training

• Xilinx tools and architecture courses

• Hardware description language courses

• Basic FPGA architecture, Basic HDL Coding Techniques, and other Free training videos!


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© 2009 Xilinx, Inc. All Rights Reserved Part 2 Virtex-6 and Spartan-6 HDL Coding Techniques.

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Transcript of © 2009 Xilinx, Inc. All Rights Reserved Part 2 Virtex-6 and Spartan-6 HDL Coding Techniques.