© 2008, Renesas Technology America, Inc., All Rights Reserved 1 Module Introduction Purpose This...

1© 2008, Renesas Technology America, Inc., All Rights Reserved

Module Introduction

Purpose This training module provides an overview of the different timers

that H8S MCUs provide for tasks such as counting, input capture, output compare, PWM output, etc.

Objective Understand the design, features and operation of the 8-bit timer,

Watchdog Timer (WDT), 16-bit timer pulse unit (TPU), programmable pulse generator (PPG), and motor management timer (MMT).

Content 24 pages

4 questions

Learning Time 45 minutes


8-bit Timer

Up to four channels of 8-bit timer

Uses internal or external clock

Provides two compare-match signals

Two channels can be cascaded to get a 16-bit timer

Can generate A/D converter conversion-start trigger

Can be put into Module Stop mode to save power

Applications

Generate counter reset, interrupt requests

Generate pulse output with an arbitrary duty cycle

using compare-match signal with two registers


8-Bit Timer Circuit

Clock Select

Control Logic

Comparator A0 Comparator A1

TCNT0 TCNT1

Comparator B0 Comparator B1

TCORA0 TCORA1

TCORB0 TCORB1

TCSR0 TCSR1

TCR1

TCLKATCLKC

f/8f/64

f/8192

Timer I/OTCLKATCLKC

Interrupt SignalsCMIA0CMIB0

CMIA1 / CMIB1OVI0 / OVI1

Clock 1

Clock 0

TCR0


Examples of Timer Operation

Free-Running Timer

PWMPulseOutput


Watchdog Timer

Generates an internal reset signal or an internal NMI interrupt signal if a system crash occurs

Has security feature that minimizes probability of inadvertent, disabling writes to WDT registers

Can use eight (WDT_0) or sixteen (WDT_1) counter input clocks

Can be switched from Watchdog Timer mode to Interval Timer mode for use as an interval timer when watchdog function isn’t needed

Watchdog Timer mode If WDT counter overflows, an internal reset or an internal NMI interrupt is

generated

When MCU is selected to be internally reset at WDT counter overflow, signal at the RESO pin goes low when overflow occurs

Interval Timer mode If WDT counter overflows, an internal timer interrupt (WOVI) is generated


Watchdog Timer Circuit

Inte

rnal

Bus

Bus InterfaceModule Bus

TCNT TCSR

Clock Select

Interrupt Control

Reset Control

WOV1

Internal NMI

RESET

Internal reset

Overflow

Clock

Internal Clock SourceØ/2, Ø/64Ø/128, Ø/512Ø/2048, Ø/8192Ø/32768, Ø/131072Øsub/2, Øsub/4Øsub/8, Øsub/16Øsub/32, Øsub/64Øsub/128, Øsub/256


16-bit Timer Pulse Unit

Up to six channels of 16-bit TPU

Can use multiple internal or external clock signals

Input capture function detects rising edge, falling edge, or both

Provides 0, 1, or toggle output at compare-match

Counter can be cleared by compare-match or input capture

PWM output waveform can be produced with an arbitrary duty cycle

Phase counting mode can be set independently for each channel

Allows automatic transfer of register data using data transfer

controller (DTC) or DMA controller (DMAC)

Can generate programmable pulse generator (PPG) output trigger,

A/D conversion-start trigger


Circuit for 16-bit TPU

Control Logic for Channels 3, 4, 5

TIORH

TMDRTCR

TIORL

TIER TSR

TCNT

TGRA

TGRB

TGRC

TGRD

TIOR

TMDRTCR

TIER TSR

TCNT

TGRA

TGRB

TIOR

TMDRTCR

TIER TSR

TCNT

TGRA

TGRB

Control Logic

TSTR TSYR

Bus Interface

TIOR

TMDRTCR

TIER TSR

TCNT

TGRA

TGRB

TIOR

TMDRTCR

TIER TSR

TCNT

TGRA

TGRB

TIORH

TMDRTCR

TIORL

TIER TSR

TCNT

TGRA

TGRB

TGRC

TGRD

Channel 0 Channel 1 Channel 2 Channel 5 Channel 4 Channel 3

Control Logic for Channels 0, 1, 2


Free-Running/Periodic Counter

Free Running CounterOperation

Periodic Counter Operation

Time

CST bit

TGF

H’0000

TGR

Flag cleared by software or DTC activation

Counter cleared by TGR compare-matchTCNT value

Time

CST bit

TCFV

H’0000

H’FFFF

TCNT value


Output-Compare Mode

Time

TIOCA

TIOCB

H’0000

H’FFFFTCNT value

No changeNo change

1 output

0 output

TGRATGRB

Time

TIOCA

TIOCB

H’0000

H’FFFFTCNT value

Toggle output

Toggle output

TGRATGRB

Example of 0 Output /1 Output

Example of Toggle Output


Input-Capture Mode

TCNT value

H’0180H’0160

H’0010H’0005H’0000

TIOCA

TGRA

TIOCB

TGRB

H’0005 H’0160 H’0010

H’0180

Example of Input Capture Operation


Phase Counting, Modes 1 and 2

Calculate the amount of rotation, aswell as the directionof rotation of the motor

Calculate the amount of rotation when the second sensor changes value


Phase Counting, Modes 3 and 4

Checks which sensorgenerates data

Checks the correlationbetween two sensors


Programmable Pulse Generator

Can generate an arbitrary waveform based on a memory-

mapped image of the waveform stored in memory

Uses the 16-bit TPU as a time base and operates with data

transfer controller (DTC) or DMA controller (DMAC)

Can output up to 8-bit or 16-bit data, with output enabled on a

bit-by-bit basis

Pulses can be generated in groups of four bits, and up to four

groups are supported, normal or inverted

Output trigger signals can be selected in 4-bit groups using

compare-match signals

Non-overlap margin can be provided between pulse outputs

Can be put into Module Stop mode to save power


16-bit TPU and PPG

Internal Data B

us

NDRB

NDRA

PBDR

PADR

NDERB

TPCRTPMR

NDERA

16-bit TPUCompare-Match

Signals

TP12-TP15

TP8-TP11

TP4-TP7

TP0-TP3

Pulse O/P pins group 3




TPMR: TPC output mode register TPCR: TPC output control register NDERA: Next data enable register A NDERB: Next data enable register B NDRB:Next data register B NDRA:Next data register A PBDR: Port B data register PADR: Port A data register


Operation of TPU and PPG

TCNT Value

Time

Compare-MatchesTCNT

80 C0 40 60 20 30 10 18 08 88 80 C0 40

80 C0 40 60 20 30 10 18 08 88 80 C000

NDRB

PBDR

TP13

TP15

TP14

TP11

TP12


Motor Management Timer

MMT produces 6-phase complimentary PWM with non-overlap timesDead times can be generated by dedicated timers

Toggle output synchronized with PWM period

Counter clearing on external signal

DTC or DMAC activated

On-chip A/D converter started

Output-off functionality PWM halted by external signal

PWM halted when oscillator stops

Can be halted in Module Standby mode to save power


MMT Circuit

TBRU TBRV TSR

Magnitude Comparators

TG

RU

U

TG

RU

TG

RU

D

TG

RV

U

TG

RV

TG

RV

D

TG

RW

U

TG

RW

TG

RW

D

+2T

d

+2T

d

+2T

d

+T

d

+T

d

+T

d

TCNT

TMDR

TCNT

Comparators

TPDR

TPBR TDDR

Comparators

TDCNT0

Control Circuit

Pf to Pf / 1024PCIOPUOAPUOBPVOAPVOBPWOAPWOBADC start trigger

+2

Td

x2

TP

DR

Co

mp

are

Ma

tch

Inte

rru

pt

2T

d C

om

pa

re-M

atc

hIn

terr

up

t

TBRW


MMT 6-phase PWM Output

TGRUU

TGRUD

U

U’

TGRU

TGRVU

TGRVD

TGRV

TGRWU

TGRWD

TGRW

V

V’

W

W’

TCNT

2Td

Td: Dead Time

Bufferregisters

Generalregisters

TBRU

TBRV

TBRW


Module Summary

8-bit timer

16-bit TPU

WDT

PPG

MMT

To get detailed information about all MCU solutions from Renesas including H8S MCUs.

Please visit our website: www.renesas.com

© 2008, Renesas Technology America, Inc., All Rights Reserved 1 Module Introduction Purpose This...

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