© 2008 Altera Corporation—Public Why You’ll Want to Think Altera When You Think About Your Next...

© 2008 Altera Corporation—Public

Why You’ll Want to Think Altera When You Think About Your Next Embedded System

2


Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation

AgendaAgenda

Why developers choose Nios® II processors

Nios II Embedded Evaluation Kit (NEEK) demo—a real example

Nios II performance

System integration using Altera® embedded technology

Resources available

Conclusion

3



There are more soft cores than hard cores in the FPGA market Gartner believes that Altera is shipping the most soft processor cores in FPGAs (Nios

processor and, more recently, ARM®)

Estimated FPGA/PLD Design Starts, Worldwide, 1999-2011 Estimated FPGA/PLD Design Starts, Worldwide, 1999-2011

20,000

40,000

60,000

80,000

100,000102,000

107,100

94,248

84,82380,582 83,000 84,102 85,532 87,756 90,125 92,378

95,704100,010

With microprocessor core

Source: Gartner Dataquest

Without microprocessor core

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Why Developers Choose Nios II ProcessorsWhy Developers Choose Nios II Processors

Custom fit to users’ application

Works with all Altera FPGA devices

Scalable performance

Concept to system in minutes

5



Nios II Processor - World’s Most Popular Soft ProcessorNios II Processor - World’s Most Popular Soft Processor

Over 20,000 development kits shipped Used in communications, consumer, industrial, medical, automotive, and

broadcast products worldwide Used by all of the top 20 OEMs

Active Nios design community (www.niosforum.org) Over 8,000 active members


Nios II Embedded Evaluation Kit (NEEK): A Real Example

7



Nios II Evaluation Kit - HardwareNios II Evaluation Kit - Hardware

Cyclone® III EP3C25 FPGA

Drop-in design examples included on SD card

Great out-of-box experience for software developers

OnlyUSD $449

OnlyUSD $449

8




Cyclone III starter board EP3C25 FPGA 32-MByte DDR 1-MByte SSRAM 16-MByte flash USB-Blaster™ circuitry JTAG header HSMC connector

OnlyUSD $449

OnlyUSD $449

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Multimedia board Color touch-panel LCD 800 x 480 resolution Composite video input VGA output Audio input Microphone input Audio output SD card I/F 10/100 Ethernet (PHY) PS2 RS-232

OnlyUSD $449

OnlyUSD $449


Nios II Performance

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Performance RangePerformance Range

* Dhrystone 2.1 Benchmark

MIPS

MIPS

MIPS

MIPS

0

50

100

150

200

250

300

Nios II/e processor Nios II/s processor Nios II/f processor

Per

form

ance

(D

MIP

S*)

12



Device familyNios II/f

processorNios II/s

processorNios II/e

processor

Stratix® III FPGA 300 128 50

Stratix II FPGA 251 110 44

Stratix FPGA 168 82 27

Hardcopy® Stratix II device 228 129 49

Hardcopy Stratix device 166 84 27

Cyclone III FPGA 165 68 17

Cyclone II FPGA 144 55 18

Cyclone FPGA 130 53 17

Nios II Processor Performance (DMIPS)Nios II Processor Performance (DMIPS)

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ExternalCPU or

DSP

ExternalCPU or

DSP

3 Ways to Scale Performance3 Ways to Scale Performance

Multi-processorsystem

PC

IP

CI

FPGA

CPUCPU

CPUCPU

CPUCPU

CPUCPU

Custominstructions

FPGA

Hardwareaccelerators

FPGA CPUCPU

HardwareacceleratorHardware

accelerator

HardwareacceleratorHardware

accelerator

CPUCPU

Custominstructions

Custominstructions

Add processors(internal and/or external)

Accelerate individual CPU performance (add application-specific instructions)

Accelerate data transformation algorithms with application-specific hardware

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Custom InstructionsCustom Instructions

* Example: CRC 64-KByte buffer

0

40

60

80

100

120

Iter

atio

ns/

seco

nd

Softwareonly

Custominstruction

20

27Xfaster27X

faster Out<<>>

&

Customlogic

+-

A

B

Nios II embedded processor

Extends CPU performance CPU fetches data, stores results Ideal for math and logical operations

e.g., floating point, bit manipulation Hardware much faster than software

15



Hardware AcceleratorsHardware Accelerators

* Example: CRC 64-KByte buffer

CRCcoprocessor

CRCcoprocessor

Programmemory

CPU

Datamemory

ArbiterArbiter

Datamemory

ArbiterArbiter

Coprocessor0

5,000

1,000

1,500

2,000

2,500

Iter

atio

ns/

seco

nd

Softwareonly

Custominstruction

530X faster530X faster

Concurrent data coprocessing CPU starts/stops the coprocessor Coprocessor fetches data and stores results CPU runs application code concurrently Ideal for block data operations

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Automates creation and integration of hardware accelerators Intuitive user interface streamlines C acceleration Uses familiar Nios II IDE Support for standard ANSI C language

Right-click to accelerate

Nios II C-to-Hardware Acceleration CompilerNios II C-to-Hardware Acceleration Compiler

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C-to-Hardware AccelerationC-to-Hardware Acceleration

main (){ …variable declarations… init();

while (!error && got_data()) { do_user_interface(); gather_statistics(); if (got_new_data()) d_transform(in_buf, out_buf); check_for_errors(); } cleanup();}

Execution time

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main (){ …variable declarations… init();

while (!error && got_data()) { do_user_interface(); gather_statistics(); if (got_new_data()) d_transform(in_buf, out_buf); check_for_errors(); } cleanup();}

Execution time

d_transform

Right-Click to Accelerate FunctionRight-Click to Accelerate Function

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Nios II MHz

Accelerate Only What’s NeededAccelerate Only What’s Needed

µP

Tasks

0% 100%

Time budget

Nios II processor

Accelerator

Transfer processing from CPU to hardware

(95-MHz Nios processor with C2H Accelerator performs image rotation as fast as 1.4 GHz processor)

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High performance

High performance

Multi-processor Hardware acceleration Custom instructions

Automated system generation Hardware/software balance Fast prototype production

GreatestflexibilityGreatestflexibility

Powerful design tools Powerful

design tools

Fastest timeto market

Fastest timeto market

Processors Peripherals Optimized interconnect

On-chip processor debug SignalTap® II logic analyzer Real-time trace capability

Nios II Processor - Leading the IndustryNios II Processor - Leading the Industry


System Integration Using Altera Embedded Technology

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Flash

SDRAM

CPU

DSP

I/O

I/O

CPU

I/O FPGA

I/O I/O I/O

CPU DSP

Overcome System Design ChallengesOvercome System Design Challenges

FPGA

Too expensive, need to reduce

cost

Changing standard requires

new device, redesign board

Marketing requires new

features to stay competitive

Need to reduceboard size to meet form

factor requirements

16-week lead time, must qualify

2nd source

Obsolete in 2 years, must support for 7

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Flash

SDRAM

CPU

DSP

I/O

I/O

CPU

I/O FPGAFPGA

I/O I/O I/O

CPU DSP

Solution: integrate external devices within programmable device

CPU

System Design ChallengesSystem Design Challenges

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Flash

SDRAM

FPGA

System-Level IntegrationSystem-Level Integration

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First Step in System DesignFirst Step in System Design

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SOPC Builder – System Generation ToolSOPC Builder – System Generation Tool

Companion chip

Custom

SPI+

SPI

General-purpose

processor

Bu

s I/

F

UART

PCI

Bridge

Custom

General-purpose processor

Bus I/F

UARTPCI

ASSP System Device

Multi-processor

Custom

General-purpose

processor Bu

s I/

F

UART

PCI

SPI

Ethernet

Custom microcontroller

Ethernet

RAM

UART

SPI Custom

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SOPC Builder System DesignSOPC Builder System Design

Cuts weeks off development time

1. Select and configure IP 2. Select connections 3. Generate system

HDL simulator FPGA

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DMA

Read_ Master

Write_Master

Control port slave

Nios II Processor

Data _Master

Instruction _Master

ETHERNET_MAC

DMA _Master

Igor_the _Slave

SDRAM Onchip_Memory UART TIMER GPIO

SOPC Builder automatically generates system interconnect fabric

SOPC Builder automatically generates system interconnect fabric

Building a SOPC SystemBuilding a SOPC System

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Demo – SOPC BuilderDemo – SOPC Builder

Goal (in 10 minutes) Show how easy it is to build a system with SOPC Builder Show how easy it is to add a custom component to your system

Overview Using SOPC Builder, we will build a system from scratch. The

system will include a processor, memory, Ethernet, and USB

Basic steps1. Create a new Quartus II project

2. Create a new SOPC-based system

3. Add a Nios II processor to system (repeat for memory, Ethernet)

4. Add custom component – USB

5. View generated system in Quartus II software


Resources Available

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GNU tools debugger, C/C++Compiler

Nios II Embedded Design SuiteNios II Embedded Design Suite

Integrated software development:

manage, build, debug

Peripheral drivers and run-time

software library

Embedded Design SuiteIDE

HAL API

Command line-based software

build flow

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* Full evaluation included in kit &/or web download - license sold separately

Nios II Embedded Design SuiteNios II Embedded Design Suite

C to Hardware (C2H) Compiler*

Real-time operating system from Micrium*

Commercial-grade network stack

from Interniche*

Embedded Design Suite

Advanced debugging tools

from FS2 and Lauterbach*

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Nios II Hardware Abstraction Layer (HAL)The HAL provides a simple device driver interface to communicate with hardware

Nios II Hardware Abstraction Layer (HAL)The HAL provides a simple device driver interface to communicate with hardware

_exit()close()closedir()fstat()getpid()gettimeofday()ioctl()isatty()kill()lseek()

open()opendirread()readdir()rewinddir()sbrk()settimeofday()stat()usleep()wait()write()

HAL API

Nios II processor system hardware

Devicedriver

Devicedriver

Devicedriver…

HAL API

Shared libraryShared library

User program

HAL benefits Change your hardware without having to change your software code When hardware is generated, a matching custom software BSP is

created automatically

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Operating SystemsOperating Systems

Company name OSNios II IDE

Plug-InReal time Type

eCosCentric eCos - Open source

Euros Euros RTOS - Commercial

Evidence Erika Enterprise Commercial

Express Logic ThreadX Commercial

Mentor Graphics® Nucleus Plus - Commercial

Micrium MicroC/OS-II Commercial

Microtronix µCLinux - Open source

Segger embOS - Commercial

Vector osCAN - Commercial

Community Supported(www.niosforum.org)

µCLinux - Open source

For more information go to Operating Systems under www.altera.com.cn/embedded

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Nios II Technical DocumentationNios II Technical Documentation

Extensive literature section on Altera.com Nios II Software Developer’s Handbook Nios II Processor Reference Handbook Tutorials Application notes

Nios II processor design examples Ethernet Multiprocessor PLL tuning Web server and many more

Nios forum (www.niosforum.com) 7000+ registered Nios II users Over 5,800 topics

Nios Wiki (nioswiki.jot.com) Nearly 100 pages of Nios II

user-generated documentation

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Optimizing C Compiler

Partner Software Development ToolsPartner Software Development Tools

Nucleus RTOS

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ConclusionConclusion

Developers choose Nios II processors because of customization, flexibility, and time to market

NEEK demonstrates what Nios II processor can accomplish

Nios II performance ranges from 17-300 DMIPS

SOPC Builder makes system integration easier

© 2008 Altera Corporation—Public Why You’ll Want to Think Altera When You Think About Your Next...

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