© 2005 Virage Logic Corporation – COMPANY CONFIDENTIALSlide 1

EDAC Panel: Shaking Things Up in the EDAC Panel: Shaking Things Up in the

Electronic Design BusinessElectronic Design Business Dr. Alex Shubat, Co-Founder, VP R&D and CTODr. Alex Shubat, Co-Founder, VP R&D and CTO

May 2005

© 2005 Virage Logic Corporation – COMPANY CONFIDENTIALSlide 2

SoC Design LandscapeSoC Design Landscape

Semiconductor IP

Functional IP (RTL)

EDA

Physical IP

Infrastructure IP

Wafers / Manufacturing

mP DSP MPEG MP3BUS

InterfaceUSB …..

Design Tools / Flows

Foundries& IDMs

Silicon Aware IP

BIST, Repair, Diagnostics, Yield Enhancement, DFM

NonVolatile Memory

eFLASH

NOVeA

HighCapacityMemory

eDRAM

1T RAM

Memory

SRAM

ROM

CAM

Logic

Std CellLibraries

Metal ProgLibraries

Interfaces

SerDes

H-S I/O

Base I/O

Analog

PLL

DLL

DAC+

© 2005 Virage Logic Corporation – COMPANY CONFIDENTIALSlide 3

Existing SolutionsExisting Solutions

PHYSICAL IPMemory, Logic, I/O, Analog, Mixed-Signal

INFRASTRUCTURE IPBIST, Repair, Diagnostics, Yield Enhancements

BOLT ON

Independently developed Physical IP and Infrastructure IP

￭ Local optimization results in sub-optimal test, diagnostics and repair

￭ Test escapes

￭ Poor yield

￭ Unpredictable quality and time-to-volume

© 2005 Virage Logic Corporation – COMPANY CONFIDENTIALSlide 4

PHYSICAL IPMemory, Logic, I/O, Analog, Mixed-Signal

INFRASTRUCTURE IPBIST, Repair, Diagnostic, Yield Enhancements

INFRASTRUCTURE IPBIST, Repair, Diagnostic, Yield Enhancements

Silicon Aware IPSilicon Aware IP

Tightly Integrated Physical And Infrastructure IP

￭ Optimal yield

￭ Higher quality

￭ Shorter time-to-volume