© 2003 Xilinx, Inc. All Rights Reserved DSP Design Flows in FPGA.

© 2003 Xilinx, Inc. All Rights Reserved

DSP Design Flows in FPGA

DSP Design Flows in FPGA - 2 - 2 © 2003 Xilinx, Inc. All Rights Reserved For Academic Use Only

After completing this module, you will be able to:

Objectives

• Describe the advantages and disadvantages of three different design flows• Use HDL, CORE Generator, or System Generator for DSP depending

on design requirements and familiarity with the tools• Explain why there is a need for an integrated flow from system design

to implementation• Describe the System Generator and the tools it interfaces with• Build a model, simulate it, generate VHDL, and go through the design flow• Describe how Hardware in the Loop verification is beneficial in complex

system design


Outline

• Using HDL• Using the Xilinx CORE

Generator• Using the Xilinx System

Generator for DSP• HDL Co-Simulation• Hardware Verification• In System Debug• Resource Estimator• Summary• Simulink Tips and Tricks


HDL Design Verification

HDL

Synthesis

Implementation

Download

HDL

Implement your design using VHDL or Verilog

Functional Simulation

TimingSimulation

In-Circuit Verification

BehavioralSimulation


Synthesis Design Verification

BehavioralSimulationHDL

Synthesis

Implementation

Download

HDL

Synthesize the design to create an FPGA netlist


TimingSimulation



ImplementationDesign Verification

BehavioralSimulationHDL

Synthesis

Implementation

Download

HDL

Translate, place and route, and generate a bitstream to download in the FPGA


TimingSimulation



Outline



Generator for DSP• HDL Co-Simulation• Hardware Verification• Resource Estimator• Summary• Simulink Tips and Tricks


CORE GeneratorDesign Verification


Synthesis

Implementation

Download


TimingSimulation


HDL

COREGen

Instantiate optimized IP within the HDL code


Synthesize, Implement, DownloadDesign Verification


Synthesis

Implementation

Download


TimingSimulation


COREGen

Synthesize, Implement, and Download the bitstream, similar to the original design flow

HDL


IP CENTER http://www.xilinx.com/ipcenter

$P Additive White Gaussian Noise (AWGN) $P Reed Solomon$ 3GPP Turbo Code$P Viterbi DecoderP Convolution Encoder $P Interleaver/De-interleaverP LFSRP 1D DCTP 2D DCTP DA FIR P MACP MAC-based FIR filter Fixed FFTs 16, 64, 256, 1024 pointsP FFT 16- to 16384- pointsP FFT - 32 PointP Sine Cosine Look-Up Tables$P Turbo Product Code (TPC)P Direct Digital Synthesizer P Cascaded Integrator CombP Bit CorrelatorP Digital Down Converter

P Asynchronous FIFOP Block Memory modulesP Distributed MemoryP Distributed Mem EnhanceP Sync FIFO (SRL16)P Sync FIFO (Block RAM)P CAM (SRL16)P CAM (Block RAM)

P Binary DecoderP Twos ComplementP Shift Register RAM/FFP Gate modulesP Multiplexer functionsP Registers, FF & latch basedP Adder/SubtractorP AccumulatorP ComparatorP Binary Counter

P Multiplier Generator - Parallel Multiplier - Dyn Constant Coefficient Mult - Serial Sequential Multiplier - Multiplier EnhancementsP Pipelined DividerP CORDIC

Base FunctionsBase Functions

Memory FunctionsMemory FunctionsDSP FunctionsDSP Functions Math FunctionsMath Functions

Key: $ = License Fee, P = Parameterized, S = Project License Available, BOLD = Available in the Xilinx Blockset for the System Generator for DSP

Xilinx IP Solutions


Xilinx CORE Generator

List of available IP from or

FullyParameterizable


Relative Placement

Other logic has noeffect on the core

Fixed Placement & Pre-defined Routing

GuaranteesPerformance

Guarantees I/O andLogic Predictability

Fixed PlacementI/Os

Xilinx Smart-IP Technology

200 MHz

200 MHz

200 MHz

Core PlacementNumber of CoresDevice Size

200 MHz

• Pre-defined placement and routing enhances performance and predictability

• Performance is independent of:


Outputs

• .EDN (EDIF implementation netlist)• .XCO (core implementation data file / log file) • Optional:

– .ASY Foundation or Innoveda symbols– .VEO Verilog instantiation template– .V Verilog behavioral simulation model– .VHO VHDL instantiation template– .VHD VHDL behavioral simulation model


Labs 1-2: Generating a MAC

• You will be generating the MAC using three different methods– Using VHDL and the Xilinx CORE Generator– Using the Xilinx System Generator for DSP

• Compare the implementation results• Contrast the design methodologies


Lab 1

Creating a MAC using a combination of VHDL and Core Generator• Become familiar with the HDL and CORE Generator design flows, which

includes:– Coding a piece of HDL– Generating CORE Generator macros– Instantiating the macros in VHDL– Synthesizing a design using Xilinx XST– Implementation using the Xilinx ISE 6 tools– Performing an on-chip verification with Chipscope-Pro

• Create a 12 x 8 MAC by generating a multiply accumulator using the CORE Generator


Wrap up

• Implementation results: 71 slices, 175 MHz• Important to notice:

– Global clock buffer should be instantiated because the synthesis tool may not know which signal is the clock because it is looking at a black box


Outline





The Challenges for a DSP Software Platform

• Industry Trends– Trend towards platform chips (FPGAs, DSP) resulting in greater complexity– Highly flexible systems required to meet changing standards– Multiple design methodologies - control plane/datapath– Challenges in modeling and implementing an entire platform– Hardware in the loop verification is useful in complex system design and System

Generator supports it• System Design Challenges

– Leveraging legacy HDL code– Modeling & implementing control logic and datapath– No expert exists for all facets of system design


MATLAB

• MATLAB™, the most popular system design tool, is a programming language, interpreter, and modeling environment

– Extensive libraries for math functions, signal processing, DSP, communications, and much more

– Visualization: large array of functions to plot and visualize your data and system/design

– Open architecture: software model based on base system and domain-specific plug-ins


MATLAB

• Frequency response of input sound file


Simulink

• Simulink™ - Visual data flow environment for modeling and simulation of dynamical systems

– Fully integrated with the MATLAB engine– Graphical block editor– Event-driven simulator– Models parallelism– Extensive library of parameterizable functions

• Simulink Blockset - math, sinks, sources • DSP Blockset - filters, transforms, etc.• Communications Blockset - modulation, DPCM, etc.


MATLAB/Simulink

Real time frequency response from a microphone: emphasizes the dynamic nature of Simulink


Traditional Simulink FPGA Flow

GAP

System Architect

FPGA Designer

Verify Equivalence

HDL

Synthesis

Implementation

Download

Timing Simulation



System Verification

Simulink


System Generator forDSP v7.1 – An Overview

• Industry’s system-level design environment (IDE) for FPGAs– Integrated design flow from Simulink to bit file– Leverages existing technologies

• Matlab/Simulink R13.1 or R14 from The MathWorks• HDL synthesis• IP Core libraries• FPGA implementation tools

• Simulink library of arithmetic, logic operators and DSP functions (Xilinx Blockset)– Bit and cycle true to FPGA implementation

• Arithmetic abstraction– Arbitrary precision fixed-point, including quantization and overflow– Simulation of double precision as well as fixed point


System Generator for DSP v7.1 – An Overview

VHDL code generation for Virtex-4™, Virtex-II Pro™, Virtex™-II, Virtex™-E, Virtex™, Spartan™-3, Spartan™-IIE and Spartan™-II devices– Hardware expansion and mapping– Synthesizable VHDL with model hierarchy preserved– Mixed language support for Verilog – Automatic invocation of CORE Generator to utilize IP cores– ISE project generation to simplify the design flow– HDL testbench and test vector generation– Constraint file (.xcf), simulation ‘.do’ files generation– HDL Co-Simulation via HDL C-Simulation

• Verification acceleration using Hardware in the Loop


• System level modeling tool– Release 13.1 or R14

• Xilinx implementation tools - ISE 7.1i• Synthesis

– XST & Project Navigator within ISE 7.1i– Leonardo Spectrum LS 2003b.35 or later

– Synplify v7.2 or later • HDL Simulation

– ModelSim 5.7e or later

Mathworks R14 Compliant!


System Generator for DSP Platform Designs

PCI/JTAG


System Generator Based Design Flow

HDLSystem Generator

MATLAB/Simulink

System Verification

Synthesis

Implementation

Download

Timing Simulation





HDLSystem Generator

MATLAB/Simulink

System Verification

Synthesis

Implementation

Download

Timing Simulation



HDL-CoSimulation

Files Used•Configuration file •VHDL•IP•Constraints File



HDLSystem Generator

MATLAB/Simulink

System Verification

Files Used•Configuration file •VHDL•IP•Constraints File

Synthesis

Implementation

Download

Timing Simulation




Creating a SystemGenerator Design

• Invoke Simulink library browser• To open the Simulink library browser,

click the Simulink library browser button or type “Simulink” in MATLAB console

• The library browser contains all the blocks available to designers

• Start a new design by clicking the new sheet button



• Build the design by dragging and dropping blocks from the Xilinx blockset onto your new sheet.

• Design Entry is similar to a schematic editorConnect up blocks by pulling the arrows on the sides of each block


Finding Blocks• Use the Find feature to search ALL

Simulink libraries• Xilinx blockset has nine major sections

– Basic elements• Counters, delays

– Communication• Error correction blocks

– Control Logic• MCode, Black Box

– Data Types• Convert, Slice

– DSP• FDATool, FFT, FIR

– Index• All Xilinx blocks – quick way to view all blocks

– Math• Multiply, accumulate, inverter

– Memory• Dual Port RAM, Single Port RAM

– Tools• ModelSim, Resource Estimator


Configure Your Blocks

• Double-click or go to Block Parametersto view a block’s configurable parameters

– Arithmetic Type: Unsigned or twos complement– Implement with Xilinx Smart-IP Core (if possible)/

Generate Core– Latency: Specify the delay through the block– Overflow and Quantization: Users can saturate or

wrap overflow. Truncate or Round Quantization– Override with Doubles: Simulation only– Precision: Full or the user can define the number

of bits and where the decimal point is for the block– Sample Period: Can be inherent with a “-1” or

must be an integer value• Note: While all parameters can be simulated,

not all are realizable


Values Can Be Equations

• You can also enter equations in the block parameters, which can aid calculation and your own understanding of the model parameters

• The equations are calculated at the beginning of a simulation

• Useful MATLAB operators– + add– - subtract– * multiply– / divide– ^ power pi (3.1415926535897.…)– exp(x) exponential (ex)


Important Concept 1:The Numbers Game

• Simulink uses a “double” to represent numbers in a simulation. A double is a “64-bit twos complement floating point number”

– Because the binary point can move, a double can represent any number between +/- 9.223 x 1018 with a resolution of 1.08 x 10-19 …a wide desirable range, but not efficient or realistic for FPGAs

• Xilinx Blockset uses n-bit fixed point number (twos complement optional)

Design Hint: Always try to maximize the dynamic range of design by using only the required number of bits

1

-22

0

21

1

20

1

2-1

0

2-2

1

2-3

1

2-4

1

2-5

1

2-6

0

2-7

1

2-8

0

2-9

0

2-10

1

2-11

0

2-12

1

2-13

Integer Fraction

Value = -2.261108…

Format = Fix_16_13

(Sign: Fix = Signed Value

UFix = Unsigned value) Format = Sign_Width_Decimal point from the LSB

Thus, a conversion is required when communicating with Xilinx blocks with Simulink blocks (Xilinx blockset MATLAB I/O Gateway In/Out)


What About All ThoseOther Bits?

• The Gateway In and Out blocks support parameters to control the conversion from double precision to N - bit fixed point precision

. . . .

DOUBLE

1-22

021

120

12-1

02-2

12-3

12-4

12-5

12-6

02-7

12-8

02-9

FIX_12_9

122

021

120

12-1

02-2

12-3

12-4

12-5

12-6

02-7

12-8

02-9

02-10

12-11

02-12

12-13

1 1 1 1 . . . .232425-26

QUANTIZATIONOVERFLOW

- Truncate- Round

- Wrap- Saturate- Flag Error


Other Type: Boolean

• The Xilinx Blockset also uses the type Boolean for control ports like CE and RESET

• The Boolean type is a variant on the 1-bit unsigned number in that it will always be defined (High or Low). A 1-bit unsigned number can become invalid; a Boolean type cannot


Fractional Number Formats

• Define the format of the following twos complement binary fraction and calculate the value it represents

• What format should be used to represent a signal that has:

• Fill in the table:

Using the technique shown, convert the following fractional values…

1 1 0 0 0 1 1 0 1 0 1 1Format = < _ _ >

Value =

Format = < _ _ > Format = < _ _ > Format = < _ _ >

a) Max value: +1 Min value: -1 Quantized to 12 bit data

b) Max value: 0.8 Min value: 0.2 Quantized to 10 bit data

c) Max value: 278 Min value: -138 Quantized to 11 bit data

Operation Full Precision Output Type <Fix_12_9> + <Fix_8_3> <Fix_8_7> x <Ufix_8_6>



SysGen blocks realizable in Hardware

I/O blocks used as interface between the Xilinx Blockset and other Simulink blocks

Simulink sinks and library functions

Simulink sources


Important Concept 2:Sample Period

• Every SysGen signal must be “sampled”; transitions occur at equidistant discrete points in time called sample times

• Each block in a Simulink design has a “Sample Period” and it corresponds to how often that block’s function is calculated and the results outputted

• This sample period must be set explicitly for:• Gateway in• Blocks w/o inputs (note: constants are idiosyncratic)

• Sample period can be “derived” from input sample times for other blocks


Important Concept 2:Sample Period

• The units of the sample period can be thought of as arbitrary, BUT a lot of Simulink source blocks do have an essence of time– For example, a sample period of 1/44100 means the block’s function will be

executed every 1/44100 of a sec• Remember Nyquist Theorem (Fs 2fmax) when setting sample periods• The sample period of a block DIRECTLY relates to how that block will be

clocked in the actual hardware. More on this later


• The Simulink System Period MUST be set in the System Generator token. For single rate systems it will be the same as the Sample Periods set in the design. More on Multi Rate designs later

Setting the GlobalSample Period

Sample Period = 1


SysGen Token

Master Controls

Slave Controls

“Simulink System Period” MUST be set correctly for simulation to work


Using the Scope

• Click Properties to change the number ofaxes displayed and the time range value(X-axis)

• Use the Data History tab to control how many values are stored and displayed on the scope– Also can direct output to workspace

• Click Autoscale to quickly let the toolsconfigure the display to the correct axisvalues

• Right-click on the Y-axis to set its value


Design and Simulatein Simulink

Push “play” to simulate the design. Go to “Simulation Parameters” under the “Simulation” menu to control the length of simulations


Generate the VHDL Code

• Select the target device• Select to generate the testbench• Set the System clock period desired• Generate the VHDL

Once complete, double-click the System Generator token


System Generator Output Files

• Design files– .VHD : VHDL design files– .EDN : Core implementation file– .XCF : Xilinx constraints file for timing constraints

• Project files– .NPL : Project Navigator project file– .TCL : Scripts for Synplify and Leonardo project creation

• Simulation files– .DO : Simulation scripts for MTI– .DAT : Data files containing the test vectors from System Generator– .VHD : Simulation testbench


Outline





HDL Co-simulation Allows Import of HDL Code

• Being able to include new or legacy modules is essential for many DSP system designers

• HDL modules can be imported into Simulink – “Black box” function allows designers to import HDL– Single HDL simulator for multiple black boxes – HDL modules can be simulated in Simulink to significantly reduce development time

• HDL is co-simulated transparently– HDL simulated using industry-standard ModelSim tool from Mentor Graphics directly

from Simulink framework


Import HDL code

Drag a Black Boxinto the model

Configuration Wizarddetects VHDL files &customizes block


Co-Simulate with ModelSim

Drag a ModelSimblock into the model

Select ModelSimSimulation Mode

Simulink opensModelSim and co-simulates


Outline





Hardware-in-the-Loop Reduces Design Time & Cost

• Configure any development board for hardware-in-the-loop using JTAG header in <20 minutes– Automatically create FPGA bit-stream from Simulink– Transparent use of FPGA implementation tools– Accelerate and verify the Simulink design using

FPGA hardware– Mirrors traditional DSP processor design flows

• Combine with black box to simulate HDL & EDIF


Create Bit-stream

Step 2 Generate Bit-stream

Step 2 Generate Bit-stream

Step 1Select Target H/W Platform

Step 1Select Target H/W Platform


Co-Simulate in HardwareStep 3 contd.

Post-generation script creates a

new library containing a

parameterized run-time co-

simulation block.

Step 3 contd.Post-generation script creates a

new library containing a

parameterized run-time co-

simulation block.

Step 4Copy the a co-

simulation run-time block into the

original model.

Step 4Copy the a co-

simulation run-time block into the

original model.

Step 5Simulate for verification

Step 5Simulate for verification


Hardware in the Loop Performance Results

Application

SoftwareSimulation

Time(seconds)

HardwareSimulation

Time(seconds)

Speed-up

5 x 5 Image Filter

Cordic Arc Tangent

Additive White Gaussian Noise Channel

170 4 43X

187 27 7X

600 80 7.5X

QAM Demodulator + Extension 1203 18 67X

A free running clock is provided to the design, thus the hardware is no longer running in lockstep with the software. The test is started, and after some time a 'done' flag is set to read the results from the FPGA and display them in Simulink. Using this hardware co-simulation method, designers can achieve up to 6 orders of magnitude performance enhancement over original software simulation.

Free Running Clock Mode

Single Step Clock Mode (bit and cycle accurate)

Image Filtering 676 6 112X


• Hardware-in-the-loop development platforms:– Xilinx

• XtremeDSP Development kit• Multimedia Board

– Distributors: • Avnet, Insight, Nu Horizons

– Key board vendors• Alphadata, Annapolis, Nallatech, Lyrtech…

– You?• Configure your JTAG-based board in 20 minutes

Choice of Target Hardware


Outline





In-System Debug at Near System Speeds

• Insert Chipscope block into Simulink design

• Configure FPGA using JTAG interface

• Perform in-system debug at near system speeds


Outline





Resource Estimator

• The block provides fast estimates of FPGA resources required to implement the subsystem

• Most of the blocks in the System Generator Blockset carries the resources information

– LUTs– FFs– BRAM– Embedded multipliers– 3-state buffers– I/Os


Resource Estimator

• Three types of estimation– Estimate Area

• This option computes resources for the current level and all sub-levels

– Quick Sum• Uses the resources stored in

block directly and sum them up (no sub-levels functions are invoked)

– Post-Map Area• Opens up a file browser and

let user select map report file. The design should have been generated and gone through synthesis, translate, and mapping phases.


Lab 2

Build a MAC with System Generator:• Goals: Gain familiarity with the SysGen v6.3 and its design flow,

including ProjNav, synthesis tools (XST), ModelSim simulators, and the ISE implementation tools. Use Resource Estimator to estimate resources used by the design. Familiarize with hardware in the Loop flow

• Background: The multiply-accumulate (MAC) operation is fundamental in digital signal processing and numerous other applications

For example, the output of a digital filter with impulse response h i and input sequence xi, is given by:

+a

bc

yn = xn-i hii=0

N-1c = aibii


Outline



Generator for DSP• Hardware Verification• In System Debug• Resource Estimator• Summary• Simulink Tips and Tricks


Summary

• Full VHDL/Verilog (RTL code)– Advantages:

• Portability• Complete control of the design implementation and tradeoffs• Easier to debug and understand a code that you own

– Disadvantages:• Can be time-consuming • Don’t always have control over the Synthesis tool• Need to be familiar with the algorithm and how to write it• Must be conversant with the synthesis tools to obtain optimized design


Summary

• Full VHDL/Verilog (Instantiating Primitives)– Advantages:

• Full access to all architecture features• Carry on further with optimization• Best optimization

– Disadvantages:• Not as portable as RTL VHDL/Verilog• Must be an FPGA expert and know the architecture• Time-consuming


Summary

• CORE Generator– Advantages

• Can quickly access and generate existing functions• No need to reinvent the wheel and re-design a block if it meets specifications• IP is optimized for the specified architecture

– Disadvantages• IP doesn’t always do exactly what you are looking for• Need to understand signals and parameters and match them to your

specification• Dealing with black box and have little information on how the function is

implemented


Summary

• System Generator for DSP– Advantages

• Huge productivity gains through high-level modeling• Ability to simulate the complete designs at a system level• Very attractive for FPGA novices• Excellent capabilities for designing complex testbenches• HDL Testbench, test vector and golden data written automatically• Hardware in the loop simulation improves productivity and provides quick verification of

the system functioning correctly or not– Disadvantages

• Minor cost of abstraction: doesn’t always give the best result from an area usage point of view

• Customer may not be familiar with Simulink• Not well suited to multiple clock designs• No bi-directional bus supported


Outline



Generator for DSP• Hardware Verification• In System Debug• Resource Estimator• Summary• Simulink Tips and Tricks


Simulink Tips and Tricks

• Throughout this course, we will disperse various tips and tricks that we find useful when using Simulink to create System Generator designs


Complete Systems

• Throughout this course, we will build and study small sections of complete systems

• To get a flavor of the capability of System Generator, check out the demos

• Type “demos” from the MATLAB command line to view them


Combining Signals

• To be viewed on a scope, multiple signals must first be combined

• Use the MUX block (Simulink library Signals & Systems) to combine signals, thus making a vector out of them

• Check Format Signal Dimensions and Format Wide NonScalar Lines to view how many signals are combined

• Similarly, the DEMUX can be used to separate signals

Type ‘vector’ to view the example


Creating Subsystems

• All large designs will utilize hierarchy• Select the blocks to go into the

subsystem. Click and drag to highlight a design region

• Select “Create Subsystem” inthe Edit Menu– Ctrl+G has the same effect

• Use the modelbrowser under the “View” menu to navigate the hierarchy

• Hierarchy in the VHDL code generated is determined by subsystems


Documenting a Design

• Double-click the background to create a textbox

• Type in the text

• Right-click the text to change format• Left-click to move the textbox around• A masked subsystem can be given

“Help” documentation. More on this later


Inports and Outports

• Allow the transfer of signal values between a subsystemand a parent

• Inport and Outport blocknames are reflected on thesubsystem

• Can be found in Simulink Sinks (for the Outport)and Simulink Sources (for the Inport)


Inputting Data from the Workspace

• “From Workspace” block can be used to input MATLAB data to a Simulink model

• Format:– t = 0:time_step:final_time;– x = func(t);– make these into a matrix

for Simulink• Example:

– In the MATLAB console, type: t = 0:0.01:1;

x = sin(2*pi*t); simin = [t', x'];

Type ‘FromWorkspace’ to view the example


Outputting Datato the Workspace

• “To Workspace” block can be used to output a signal to the MATLAB workspace

• The output is written to the workspace when the simulation has finished or is paused

• Data can be saved as a structure (including time) or as an array

Type ‘ToWorkspace’ to view the example

© 2003 Xilinx, Inc. All Rights Reserved DSP Design Flows in FPGA.

Documents

Transcript of © 2003 Xilinx, Inc. All Rights Reserved DSP Design Flows in FPGA.