The International Conference on Fundamentals of Electronics. Communications and Computer Sciences. March 27, 28. 2002, Waseda Umv.. Tokyo. J

A High Speed and High Resolution, Parallel Pipeline AID Converter in 0.6 -11mCMOS

Jafar Talebzadeh Mohammad Yavari Mohammad Reza Hasanzadeh amid Shoaeijlalebzadeh@yahoo.com mmyavari@yahoo.com mrhreza@yahoo.com oshoaei@yahoo.com

Tel: +98-21-3188179 Tel: +98-21-8844386 Tel: +98-911-2767287 Tel: +98-911-2344174Electrical and Computer Eng. Dept., University of Tehran, Tehran 14395-515, Iran

Abstract-This paper describes a to-bit 150M5/s CMOS parallelpipeline ADc. The converter includes four parallel interleavedpipeline AID converters with analog background calibrationusing adaptive signal processing, an extra channel, and mi1:edsignal integrators that match the offsets and gains of time-interleand ADC channels. With monolithic analog backgroundcalibration, the SJ'iDR in all corner cases (55, SF, FS, FF, andTT) and temperature bem-een -40°C to 85°C is better than57dB. The power consumption is 1200mw at a 3.0V supplyvoltage. This work is achiend in a 0.6 pm CMO5 process.

I. Introduction

The increasing range of "ide-band wireless CommunicationStandard, like the Universal Mobile TelecommunicationSystem (UMTS), Wireless Local Loop (WLL), and LocalMultipoint Distribution Services (LMDS), will evolve tohigh data rate applications within the next few years. Thethroughput rate of digital signal processing systemsoperating on analog inputs is often limited by the speed ofthe analog-to-digital (A/D) interface, So, for theseapplications we need the high resolution and very highsampling rate AiD converters.To increase the speed of AiD converters beyond thetechnological limitations, more than one analog-to-digitalconverter (ADC) component, are interleaved in time asshown in Fig.l [1], [2], [3], [5], [7], [8], [9]. Unfortunatelythe use of parallel ADCs has limited application because 1)the siJicon area, and power consumption are increaseddramatically, and 2) the performance of time-interleaved isdegraded by the mismatches among the multiple channels.These mismatches include gain, offset, and timingmismatches that give rise to fixed-pattern effects, which aremanifested as spurious harmonics in the frequency domain[2]. Previous monolithic time-interleaved ADC arrays usedcareful layout, foreground calibration, digital filters, ortrimming to minimize the effects of these mismatches [3],[5], [10]. This paper describes a parallel pipeline ADC thatuses the adaptive background calibration to match the gainsand offsets of the channels [8], [9]. Background calibrationis able to track variations over time and, it dose not inteITIIptthe conversion process of ADc.In section II, brief views of l.5bit/stage pipeline ADCs aredescribed. In section Ill, the parallel pipeline architectureand their problems are presented. The circuit description ofthis ADC is brought in section IV. Finally, section Vcontains the adaptive calibration method, and section VI,contains the simulation results.

.-:..,...

~ ADC1 ~~analog Y Y Nbits

[(1)0---1\ ~ .t~

~ ; )p Y(nT)~Fig.l: Time-interleaved ADCs.

. i : \ .

f c;= \ :.\.

\ :: L

\ ~O,/ ,v", Cornct!on

-6 ~ $." v.~ I ..../~

Fig.2: A pipeline .-\DC with 1.5bitlstage architectUre.

II. Re\iew Of Pipeline ADC

The functional block diagram of a 1.5bit/stage pipeline ADCis shown in Fig. 2. The characteristics of this ADC 2.redescribed in [3] and [4]. The system consists of severalcascaded gain stages, as shown in Fig.3. Each stagecomprises of two comparators, a multiplexer, and a gainstage. Digital outpUt codes of comparators drive amultiplexer to make a quantized analog estimate of theinput. The multiplexer output is then subtracted from theinput to make a residue, which is gained up by two andtransferred to the next stage. The next stage manipulates onthe residue of previous stage. In each stage, 1.5bit of inputsignal is quantized except the last one, which has threecomparators, and 2bits are quantized. In implementation ofpipeline multistage ADCs, digital error correction is usua]]yemployed with D.5-bit or I-bit redundancy between stages

6-5

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The International Conference on Fundamentals of Electronics. Communications and Computer Sciences, March 27. 28. 2002, Waseda Univ., Tokyo, J-

analogInput

~~~f

~,/.

V'ifj

V'if /- /4

- -

-V'or Q v'if

Fig.3: A single ended configuration of a stage of 1.5bit/stagepipeline ADc.

TABLE I: Summary of performance limitation and solutions.

except the last one [3], [4], [6]. This relaxes the offsetrequirements of the comparator to 2-bit level. If thecomparators have offsets lower than VREF/4,the systemcorrects the fmal digital output code.

III. Parallel Pipeline ADCs

This ADC uses multiple pipeline ADCs in parallel time-interleaved configuration in order to increase throughput.Fig.l shows a block diagram of M time-interleaved ADCs.Each ADC operates at the sampling rate ofFs/M, where M isthe number of parallel ADC channels. On the left side, ananalog demultiplexer selects an ADC to quantize the inputI(t). On the right side, the corresponding multiplexer selectsthe digital output of the ADCs. The overall system operatesin sampling rate of Fs. Each channel contains, an input S/Hfollowed by a cascade of pipeline stages. Performance ofparallel pipeline ADCs is limited by two factors; first, bymatching among the ADC channels. Three major sources ofmismatch in time-interleaved ADCs are offset, gain, andsampling time mismatches among the channels. Second, thespeed of each individual channel is limited by settling timeof S/H and gain-stagein hold mode, which is determined, byop-amp settling time. In Table I, summary of performancelimitation, mismatcherror power, and solutions in the designof parallel pipeline ADCs are described [1], [2]. Here a; is

the channels offset variance; "'; is the channels gain

variance; "'; is the sampling-timevariance; A and OJI. areamplirude and frequency of the input signal, respectively.

v",; v".;

v., o-j

V'-J>1-j ~v..

Fig.4: A two-stage op-arnp.

IV. Circuit Description

In the main pipeline ADC, many basic building blocks areused. The speed of the ADC depends on the speed of theseblocks. In the following section, their schematics, andproperties are described.

A. High-Swing AmplifierIn pipeline .WCs, speed is limited by the settling time of theop-amp in its closed-loop configuration. So, op-amps withhigh GBW and high dc gain must be used. Most designersuse one-stage op-amps with gain boosting or two-stage op-amps; Gain boosting technique uses four auxiliary op-ampsthat increase power consumption and silicon area. So, in thiswork a two-stage op-amp is used as shown in FigA. Thisconfiguration gives enough dc gain and GBW. This op-ampis very fast, has high swing and is a good choice for lowvoltages. In this configuration, two SC Common ModeFeedback (CMF) are used. First-stage of this op-amp doesnot need to accommodate a large voltage swing, so smalltransistor sizes can be used. This makes the parasiticcapacitances smaller, which in turn makes the op-amp faster.

B. Latch ComparatorA 1.5bit/stage pipeline ADC employing digital correctiondoes not require a low-offset comparator. The djllamiccomparator shown in Fig.5 operates without samplingcapacitors and has fairly low power consumption [3]. Theinput nodes are connected to the outputs of the previousstage. When latch='Q', the comparator is in the reset modeand the outputs are low, when latch=' I " the comparatorcompares input signal with the scaled reference voltage, tomake a decision.This comparator has a poor common mode rejection ratio(PSRR) with an offset that is dependent on the inputcommon mode voltage.

Problem Effects Power Solutions

O1annel offset Tonesat:.;.offset cancelation

1 IX calibcationmismatch <7,

(analog or digital)1-1.. (M-I!

AmplitUdeModulationO1annel gain of input SIgnalat: 1,. capacitor matching

mismatch

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and share DAClevels

PI!ase Moduiationat use at Delay LockedSampling-time inputsignal at: 1 1 1 , Locp or Front-Rank

mismatch.i-iF.. TA (J}..<7, sample and hold

The International Conference on Fundamentals of Electronics, Communications and Computer Sciences, March 27,28,2002, Waseda Univ.. Tokyo, J

Vowi" ~'",-

- -

Fig.S: A dynamic latch comparator.

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(a)

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(b)

Fig.6: (a) The fully differential gain stage,And (b) the clock phases.

C. Gain StageThe fully differential implementation of the gain stage isshown in Fig.6 (a). The bootstrapped switches are used forhigh swing switches (the input and the feedback loopswitches). The clock booster circuit locally is used for eachbottom-plate sampling, DAC, and output switches. Thiscircuit decreases the on-resistance of a NMOS switch. The

MSB LSBv~,.C V.,K

V';v,;

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V~!

$1

v.;v,;

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Fig.?: The Sub-ADC and DAc.

clock phases are shown in Fig.6 (b), Corresponding tosampling on phase <1>"bottom-plate sampling on phase <1>;,

andresidueamplifyingonphase <1>,.

D. Su~ADC And DACThe fully differential sub-ADC and DAC circuit within eachpipeline stage is shown in Fig.? The threshold voltages ofcomparators are at -Vref /4 and V,ef /4. The input signal iscompared with the threshold voltages, and the comparatoroutputs are then decoded by some digital logic gate whichselects one of the three values, -Vref, 0, Vref for thedifferential DAC output. The output is also gated by theclock phase <1>,.The MSB and LSB bits are fed to latches.The NMOS switch with the clock booster circuit is used foreach switch in this circuit. The schematic of the comparatoris shown in Fig.5.

E. Bootstrapped MOS Switch,In low-voltage designs, transmission gates cannot be directlyrealized on a supply voltage below the sum of the twothreshold voltages. In high-speed designs, the transmissiongates aren't used, because the parallel NMOS and PMOS

Vd.

XCLK

J..~II'

-

Fig.8: The bootstrapped MOS switch.

The International Conference on Fundamentals of Electronics, Communications and Computer Sciences, March 27, 28, 2002, Waseda Univ., Tokyo. J

V"'~3V

I [1M ":"]

G

!

~ !S, Il-, J

D

Fig.9: The charge pump circuit to boost the clock voltage.

transistors increase the parasitic capacitances. Moreover, theon-resistance has a nonlinear voltage dependent, whichproduces distortion when the sv.itch tracks the input signal.For reducing the on-resistance, distortion, and parasiticcapacitances, the bootstrapped MOS switch was designed asshown in Fig.8 [4], [7]. In "off" phase, the capacitor C1 ischarged to supply voltage, and during the "on" phase, thecapacitor C1 is then connected across the gate and sourceterminals of the switching device MI. This capacitor will actas the battery across the gate and source during the "on"phase. Note that the body of the PMOS M4 is tied to its thesource and latch up effect is suppressed by it. Device M6reduces the Vdsand Vgdexperienced by device M7 whenXCLK=l. So, in this circuit no device experiences a relativeterminal voltage greater than Vdd.This circuit presents thelow and constant on-resistance switch, which reduces thedistortion and gain error. This circuit can be used in low-voltage and high-speed designs.

F. The NMOS Switch With Clock Booster CircuitIn standard CMOS technologies, the threshold voltage ofMOS transistor does not scale down with the supply voltage,and it lead to some problems, when the MOS transistor isused as switch at low-voltages. The threshold voltage withbody-effect has become a large value, which the driveeffective voltage reduces; hence the on-resistance of a MOSswitch increases. It degrades the speed of SC circuits.For reducing the switch on-resistance, width of the switchincreases. However, this will also increase the parasiticcapacitances associated with switch. Another way is toreduce the threshold voltage of the switches. However, thisrequires a few extra mask steps in the process, which are notavailable in typical CMOS process. The only option left is toincrease the gate drive voltage to 5V. The approach chosenhere is to simply use a dynamic charge pump circuit tolocally boost the clock drive. This circuit is shown in Fig.9[3].

1(1)MUX

OUT0EMUX

ColllntlonSIgn"

Goo_...

- analog

-digit..

Fig.IO: Adaptively calibrated ADC system.

Y.(n)

ADCI under

C.Ubntlon

1.5b"lb1t- .",'og- digit.,

Fig.ll: Mixed-signal adaptive calibration loop.

By applying a 3V clock signal, the capacitances C1 and Czare self-charged to 3V through the cross-coupled N1tfOStransistors. When the clock is low, the voltage will bepumped on Cz is greater than 3V, and the PMOS Ml will beon and transfers the voltage to the NMOS switch. TransistorM2 discharges the high voltage node to ground when the .

clock signal is high. The booster circuit converts a 3V clocksignal to 5V. The switch is on when the clock is low and it isoff when the clock is high.To avoid latch up in the circuit, the body of the PMOS MI istied to its source, and the latch up effect is suppressed by it.

V. Calibration

Fig.IO shows a block diagram of a time-interleaved ADCsystem that uses adaptive calibration to overcome gain andoffset mismatches [8]. Five high-speed pipeline ADCs areused in this work, of which, four ADCs are in samplingmode; while the other one is in calibration mode. Theselected ADC and reference ADC (that is usuallyalgorithmic) are fed with identical inputs from thecalibration signal generator. The gain and offset of theselected ADC is adjusted to match with the reference ADc.The gain and offset adjustment are made using simplified

The International Conferen~e on Fundamentals of Electronics, Communications and Computer Sciences. March 27,28.2002, Waseda Univ., Tokyo. J

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Fig.l2: ADC's OUtpUt spectrum before calibration.

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Fig. 13: ADe'S OUtpUt spectrum after calibration.

version of the Least Mean Square (LMS) algorithm [11].Once the calibration cycle is completed, another ADC isselected for calibration, and the most recently calibratedADC replaces it in the conversion mode.Fig.ll shows the calibration loops of one of the five ADCchannels. Here the ADC under calibration is ADCi; 0; is ithchannel offset adjustment coefficient; gi is ith channel gainadjustment coefficient; e; is the difference between theoutput codes of ADCi and the reference ADC, and n is thesampling time index. The LMS loop adjusts 0; and g; ofADCi, until the error power is minimized. This occurs whenthe overall offsets and gains of the reference ADC and ADCiare the same. The gain and offset terms are updated usingthe following equations [8]:

o/(n + 1) =OJ(n)+ }lsgn(e/(n))

gj(n + 1) = g/(n)+ }lsign(Yj(n)]sgn( ej(n)]

(1)

(2)

Equation (1) and (2) are simplified versions of the standardLMS equations [11]. This configuration simplifies therequired hardware. In this equations, the sgnO function isdefined as:

j

+l'

sgn(e.)= 0,-1,

e. >0

-O$e. $0

e. < -0

(3)

-0.2-

-0"-

Fig.l4: Differential nonlinearity versus code.

0.8-

INL i(LSB)0.6.

,~

/1 (!(I I

;[/: I if

0.2, , ' j

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/ ~1600 80' '000

CODE

uL

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!-o.8L

0 200 400

Fig.l5: Integral nonlinearity versus code.

TABLE II: Performance summary

The 0 in (3) is an LSB of the ADc.

VI. Simulation Results

The circuit is simulated in a 0.6-}lm CMOS process. The

circuit operates at a 3.0V supply, and with 2Vpp inputdifferential voltage.

Parameter Performance

Resoultion 10 bit

Sampling Rate 150Msample/sDNL 0.85 LSB

INL 0.80 LSB

SNDR@Fin=75MHz SUB In All Comer Cases

Offset Mismatch ( 0',) 3.94 LSB

Gain Mismatch (at) 0.295%

J1 - Update Step Size 0.0002

Power Consumption 1200mW

Supply Voltage 3.0V

The International Conference on Fundamentals of Electroni~,. Communications and Computer Sciences. March 27.28. 2002.WasedaUniv.. Tokyo. J

Fig.12showsa FastFourierTransform(FFT) of the outputbefore calibration, when a 3.9453125MHz full-scale sinewave input is sampled at the full clock rate (150MS/s). Thetones caused by the gain and offset mismatches are at33.80IMHz, 41.198MHz, 71.30 IMHz, 37.5MHz, and75MHz with amplitude of -54.2dB, -54.4dB, -72.4dB,-39.5dB, and -74.6dB, respectively.These tones correspond to the gain mismatch of 0.295% andan offset mismatch error of 3.94LSB. These spurious toneslimit the SJ';'DRof this ADC to 39.1dB.Fig.13 shows an FFT of the ADC output after calibration,the same input was applied. The calibration loop wasactivated for 2000 calibration cycles. After 150 cycles thecalibration loop converged and the gain and offset of theselected ADC channel was adjusted with the reference ADc.Tones caused by gain and offset mismatches are -73dB,-73.8dB, -70.9dB, -69.1dB, and -79.7dB, which werereduced by -18.8dB, -19.4dB, 1.5dB, -29.6dB, and -5.ldB,respectively.The system level Monte Carlo simulations were done, andthe simulation results show that the DNL and INL are betterthan O.85LSB and 0.8LSB, respectively as shown in Fig.14,and in Fig.15.

vll. Conclusion

This paper describes a 10bit 150MS/s parallel pipeline ADc.The gain and offset mismatches of channels are reduced byadaptive background calibration. The power consumptionand silicon area of time-interleaved ADC increase linearlyby the number of channels.

VllI. References

[I] C. S. G. Conroy, D. W. Cline, and P. R. Gray," An 8-b85-MS/s Parallel Pipeline AID Converter in !CMOS, "IEEE J. Solid-State Circuits, Vo1.28, pp. 447-454,Apr.1993.

[2] W. C. Black, Jr. and D. A. Hodges," Time interleavedconverter arrays, "IEEE J. Solid-State Circuits, Vol. SC-15, No.6, pp. 1022-1029, Dec.1980.

[3] T. B. Cho, and P. R. Gray, " A IO-b 20-MS/s 35-mWPipeline AID Converter," IEEE J. Solid-State Circuits,Vo1.30,pp.166-172,Mar.1995.

[4] A. M. Abo, and P. R. Gray, " A 1.5V 10-bit 14.3MS/sCMOS Pipeline analog-to-digital Converter," IEEE J.Solid-State Circuits, Vo1.34, pp. 599-606, May. 1999.

[5] K. Nakamura, M. Hotta, L. R. Carley, and D. J. Allstot," An 85-mW 10-b 40-MS/s CMOS Parallel-PipelineADC," IEEE J. Solid-State Circuits, V01.30, pp. 173-183, Mar.1995.

[6] S. H. Lewis, and P. R. Gray, " A Pipelined 5-Msample/s9-bit analog-to-digital Converter," IEEE J. Solid-StateCircuits, Vol. SC-22, pp. 954-961, Dec.1987.

[7] L. Sumanen, M. Waltari, K. A. 1. Halonen, " A 10-bit200-MS/s CMOS Parallel Pipeline AID Converter,"IEEE J.Solid-State Circuits, Vo1.36,NO.7, Ju1.2001.

[8] K. C. Dyer, S. H. Lewis, P. J. Hurst, " An AnalogBackground Calibration Technique for Time-IntegratedAnalog-to-Digital Converters," IEEE 1. Solid-StateCircuits, Vo1.33,No.12, Dec.1998.

[9] K. C. Dyer, S. H. Lewis, P. J. Hurst, " A DigitalBackground Calibration Technique for Time-IntegratedAnalog-to-Digital Converters," IEEE J. Solid-StateCircuits, Vo1.33,No.12, Dec.1998.

[10]M. Yotsuyanagi, T. Etoh, and K. Hirata, " A 10-b 50-MHz Pipelined CMOS AID Converter With SIH," IEEEJ. Solid-State Circuits, V01.28,pp. 292-300, Mar.1993.

[II]B. Widrow, and S. Steams, Adaptive Signal Processing,Englewood Cliffs, Nj: Prentice-Hall, 1985.