– 1 – EDA modelling of POI with direct CMOS-optics hybridization Integration of Modelling Tools...
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EDA modelling of POI with direct CMOS-optics hybridization– 1 –
Integration of Modelling ToolsIntegration of Modelling Toolsfor Parallel Optical for Parallel Optical
InterconnectsInterconnectsin a Standard EDA Design in a Standard EDA Design
EnvironmentEnvironmentMichiel De Wilde, Olivier Rits, Wim Meeus,Hannes Lambrecht, Jan Van Campenhout
Ghent University, BelgiumIMEC
EDA modelling of POI with direct CMOS-optics hybridization– 2 –
OverviewOverview
• Chip-to-chip Parallel Optical Interconnects (POI)– Concept: CMOS with hybridized optics
• Integration in EDA tools– EDA support for POI elements (IC and system level)
(compared to electrical interconnect)
• Coherent circuit-level simulation– Analog models
– Digital simulation
– Timing verification: random behaviour in POI
EDA modelling of POI with direct CMOS-optics hybridization– 3 –
Concept: CMOS with hybridized Concept: CMOS with hybridized opticsoptics
VCSELsCMOS substrate (top side visible)
Photodiodes
Package
Connector
Solder balls
Fiber bundle
PCB
EDA modelling of POI with direct CMOS-optics hybridization– 4 –
Clock re-synccircuitry
Driver & receivercircuitry
TX
POI elementsPOI elementsVCSELtechnology
Photodetectortechnology
Optics-CMOShybridization
Waveguide routing technology
Connectorization
Optical waveguides(POF/integrated)
IC packaging
EDA modelling of POI with direct CMOS-optics hybridization– 5 –
Interconnect data flowInterconnect data flow
paralleloptical
interconnect
electricalinterconnect
in
T X
LVDS
T LINE
100 diffRX
out
RT
c lock
100
FinT X VC PD RX
out
RT
clock
EDA modelling of POI with direct CMOS-optics hybridization– 6 –
FinT X VC PD RX
out
RT
in
T X
LVDS
T LINE
100 diff out
RTRX
100
EDA support for EDA support for interconnectionsinterconnections
For interconnect, design tools normally provide:• Design (instantiation) of system-specific parts• pre-production Validation• post-production Testing
IC levelD,V & T
IC levelD,V & T
PCB levelD, V (& T)
interface
Vinterface
V
+pads +pads
EDA modelling of POI with direct CMOS-optics hybridization– 7 –
IC-level EDA support for IC-level EDA support for interconnectinterconnect
• Electrical interconnect:– pads + I/O circuits– (reduced) layout view– analog & digital simulation
views
• Parallel optical interconnect:– VCSEL driver/photodiode
receiver + flip-chip pads– design kit: similar approach
RX TX
EDA modelling of POI with direct CMOS-optics hybridization– 8 –
Driver/receiver simulation Driver/receiver simulation modelmodel
• Normal analog electrical circuits• IP protection: compiled/no real circuit given• Alternative: parameterised flowchart• Validation: comparison with compiled circuit
Receiver flowchart
Transimpedance preamplifier
Postamplifier
Decision circuit
Equalizer
Limiting amplifier
Photocurrentinput
Digital output
EDA modelling of POI with direct CMOS-optics hybridization– 9 –
Post-assembly testing of optical Post-assembly testing of optical linkslinks
• JTAG Boundary Scan cells in RX/TX circuits• DC-free signal alternating on test clock: AC-JTAG
EDA modelling of POI with direct CMOS-optics hybridization– 10 –
Photonics in circuit-level Photonics in circuit-level simulatorssimulators
• Verilog-AMS and VHDL-AMS support “optical power”
• Options at the interface between models:
modelled
device A
modelled
device B
light power light powermodelle
ddevice A
modelled
device B
current-like approach potential-like approach
• Natural choice: current-like approach, but– Kirchhoff’s first law is enforced
– Photons from opposite directions would counteract each other?
• Potential-like: explicit optical propagation inside models
EDA modelling of POI with direct CMOS-optics hybridization– 11 –
VCSEL modellingVCSEL modelling• Highly nonlinear differential equation system
(image: M.X. Jungo)
carrier density
photon numberin the kth mode
• Spatial integration is too slow(and not possible with circuit-level simulators)
EDA modelling of POI with direct CMOS-optics hybridization– 12 –
Verilog-AMS VCSEL modelVerilog-AMS VCSEL model• Abstractions by Mena, Morikuni, Jungo:
– fix the shape of mode profiles– result: spatial integration becomes static
inout<1:2>
gnd!
fixed mode profiles
optical powerper mode
&
• Electrical model: diode + parasitics• Convergence and numerical issues
EDA modelling of POI with direct CMOS-optics hybridization– 13 –
Photodiode modellingPhotodiode modelling• Linear: electrical current vs. optical power
L (mW)
I (mA)
dark currentre
sponsiv
ity
IL
• Electrical parasitics overwhelm intrinsic responseResult: only total incident light power is required
EDA modelling of POI with direct CMOS-optics hybridization– 14 –
Verilog-AMS photodiode modelVerilog-AMS photodiode model
module pin_photodiode(in,anode,cathode); input in; inout anode, cathode; power in; electrical anode, cathode; parameter real Cdep=0, Cbo=0, Rbas=0, Resp=0, Id=0; parameter real pole=-1/(Cdep*Rbas); parameter real laplace_coeff_0=Cdep+Cbo; parameter real laplace_coeff_1=Cdep*Cbo*Rbas; charge rc; analog begin I(cathode,anode) <+ laplace_zp(Resp*Pwr(in)+Id,{},{pole,0}); Q(rc) <+ laplace_np(V(cathode,anode),{laplace_coeff_0,laplace_coeff_1},{pole,0}); endendmodule
•Terminals•Model parameters•Equations describing internal state and outputs
EDA modelling of POI with direct CMOS-optics hybridization– 15 –
Parameter extractionParameter extraction
• Photodiode model: easy– simple measurements– datasheet
• VCSEL model: difficult– nonlinearity– multiple modes– temperature sensitivity + self-heating– many model parameters (>60 for only 2 modes)– datasheet not sufficient
– Ideally: standardized model (~BSIM transistor model)
modelmeasurement
VCSEL current (A)
Out
put
pow
er (
W)
EDA modelling of POI with direct CMOS-optics hybridization– 16 –
Optical pathOptical path
• Two approaches for the optical path:
Routed POF Integrated waveguides
Ribbonisation
Routing on flexible foil
EDA modelling of POI with direct CMOS-optics hybridization– 17 –
Optical path modelOptical path model• Photodiode input = propagated VCSEL modes
• Categories: interface jumps & waveguides• Interface jumps:
– During simulation, multiply with 0 < < 1– To calculate (statically):
Fresnel diffraction of free-space propagation
in<1>
in<2>
in<3>
in<4>
out<1>
out<2>
out<3>
out<4>
opt icalpath
EDA modelling of POI with direct CMOS-optics hybridization– 18 –
Optical misalignmentOptical misalignment
Numerical aperture of POF
VC
SE
L-PO
F d
ista
nce
(µ
m)
Misalignment:0µm
Misalignment:10µm
VCSEL-POF coupling efficiencyVCSEL diameter: 8µm, fiber core: 50µm
EDA modelling of POI with direct CMOS-optics hybridization– 19 –
Propagation in waveguidesPropagation in waveguidesMultimode: apply raytracing
Numerical aperture of POF
Ben
din
g r
ad
ius
(µm
) Core diameter:50µm
Core diameter:98µm
Transmission of a step index POF after a 90° bend(input pattern: far field of VCSEL)
EDA modelling of POI with direct CMOS-optics hybridization– 20 –
Dispersion in waveguidesDispersion in waveguides
• POF with graded index: ~0.1ps for 1mlight travels faster nearby the cladding
• step index POF/PCB integrated: ~100ps for 1m
Dispersion cannot be neglected anymore
Dispersion is negligible here
EDA modelling of POI with direct CMOS-optics hybridization– 21 –
Coherent interconnect Coherent interconnect simulationsimulation
(exaggerated VCSEL model parameters)
EDA modelling of POI with direct CMOS-optics hybridization– 22 –
POI simulation within a digital POI simulation within a digital systemsystem
• Digital views with just signal propagation
• Cell with multiple views: interface correspondence
• Extract delays from analog simulation andannotate to digital model using SDF files
• Timing verification: minimal/maximal timings required…
outFinT X VC PD RX
propagate over fundamental mode
in out<1:N>
gnd!in out
vcc!
gnd!
EDA modelling of POI with direct CMOS-optics hybridization– 23 –
Random effects in POIRandom effects in POI
• Static deviations– Manufacturing process fluctuations– Mechanical tolerances
• Random noise processes– VCSEL relative intensity & phase noise– Receiver circuit: thermal noise
• Coupled noise– Optical crosstalk– Supply noise– Substrate noise
EDA modelling of POI with direct CMOS-optics hybridization– 24 –
AcknowledgementsAcknowledgements
• IST Interconnect by Optics project partners
• Fund for Scientific Research – Flanders (Belgium) (F.W.O.)– Research assistantship
EDA modelling of POI with direct CMOS-optics hybridization– 25 –
SummarySummary
• Chip-to-chip Parallel Optical Interconnects (POI)– Concept: CMOS with hybridized optics
• Integration in EDA tools– EDA support for POI elements (IC and system level)
(compared to electrical interconnect)
• Coherent circuit-level simulation– Analog models
– Digital simulation
– Timing verification: random behaviour in POI
EDA modelling of POI with direct CMOS-optics hybridization– 26 –
Application: optimization of the Application: optimization of the POIPOI
• Choices for operating currents, analog circuit design,numerical aperture, physical dimensions…
• Improvement at one place can get lost elsewhere
(not to scale)
Increase of numerical aperture of fiberbettercoupling
worsecoupling
lessbendinglosses
Choices parameter extraction simulation performance examine the opposite direction
EDA modelling of POI with direct CMOS-optics hybridization– 27 –
CMOS substrate noiseCMOS substrate noise
Simultaneous switching noise can disturb receiver circuits
p subst ra te
gndgnd
Digi ta lFET
An alo gFET
Pac kage p+ n+n+ n+ n+
(figure: Cadence)