Low-Power and Area-Efficient Carry Select Adder

A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing

A Novel Approach for Motion Artifact Reduction in PPG Signals Based on as-LMS Adaptive Filter

Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm

Design and Implementation of a Pipelined Datapath for High-Speed Face Detection Using FPGA

Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-Throughput MIMO-OfDM Systems

vlsi%Pjt%List(2k12-2k13)_v1_r6

Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm

Vlsi Consolidated v1 16.7