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UNIT II DESIGN "ULES
Syllabus:
L#(out Comction - Design rules - &ro*lem "ormul#tion - #lgorithms "or
constr#int gr#&h comction - &l#cement #nd rtitioning - Circuit
re&resent#tion 5 Pl#cement #lgorithms 5 rtitioning
O*6ectie7'o underst#nd the #rious design rules S(m*olic l#(out #nd Constr#int-gr#&h
comction.
LESSON PLAN LP VL9!
LP "ev# N$: %%
Date: &'%('!)
Pa*e %! $+ %(
Sub ,$-e'Na.e: VL9!/,AD 0O" VLSI ,I",UITS
U1it : II 23a1c4 : E, Se.este3: III
Sessi$1
N$# T$5ics t$ be c$ve3e- Ti.e "e+
Teac4i1*
Met4$-
10 L#(out Comction ,0m 18-84
21-
/PP'
11 Design rules ,0m 184-8,2-4 /PP'
12 &ro*lem "ormul#tion ,0m 18-30 /PP'
1 #lgorithms "or constr#int gr#&h
comction
,0m 131-3
2,-
/PP'
14 #lgorithms "or constr#int gr#&h
comction
,0m 131-3
2,-
/PP'
1, &l#cement #nd rtitioning ,0m 1101-102
210-103
/PP'
1 Circuit re&resent#tion ,0m 1102-10, /PP'
1 Pl#cement #lgorithms ,0m 110-110
2112-113
/PP'
18 rtitioning ,0m 1112-118
21-182
/PP'
C$'-I ,m
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UNIT III 0LOO" PLANNING
Syllabus:
9loor &l#nning conce&ts - sh#&e "unctions #nd "loor &l#n si+ing - '(&es o" loc#l
routing &ro*lems - $re# routing - ch#nnel routing - glo*#l routing - #lgorithms
"or glo*#l routing.
Objective:
'o underst#nd the conce&ts o" "loor &l#nning #nd #rious routing
#lgorithms.
LESSON PLAN LP VL9!
LP "ev# N$: %%Date: &'%('!)
Pa*e %! $+ %(
Sub ,$-e'Na.e: VL9!/,AD 0O" VLSI ,I",UITSU1it : III 23a1c4 : E, Se.este3: III
Sessi$1
N$#
T$5ics t$ be c$ve3e- Ti.e "e+ Teac4i1*
Met4$-
13 9loor &l#nning conce&ts ,0m 1113-124 /PP'
20 sh#&e "unctions ,0m 112,-12218-28
/PP'
22 "loor &l#n si+ing 100m 112-123
228-283
/PP'
2 '(&es o" loc#l routing
&ro*lems
,0m 11-14
213-134
/PP'
2, $re# routing 100m 114-1,
213,-138
/PP'
2 ch#nnel routing ,0m 118-14
2200-203
/PP'
2 glo*#l routing ,0m 11,0-1, /PP'
28 $lgorithms "or glo*#l
routing.
,0m 11,4-1
2210-212
/PP'
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UNIT IV SIMULATION
Syllabus:
Simul#tion - %#te-leel modeling #nd simul#tion - S!itch-leel modeling #nd
simul#tion - Com*in#tion#l Logic S(nthesis - in#r( Decision Di#gr#ms - '!o
Leel Logic S(nthesis.
Objective:'o introduce the "und#ment#l conce&ts o" #rious modeling #nd simul#tions #nd
s(nthesis.
LESSON PLAN LP VL9!
LP "ev# N$: %%
Date: &'%('!)
Pa*e %! $+ %(
Sub ,$-e'Na.e: VL9!/,AD 0O" VLSI ,I",UITS
U1it : IV 23a1c4 : E, Se.este3: III
Sessi$1
N$#
T$5ics t$ be c$ve3e- Ti.e "e+ Teac4i1*
Met4$-
23 Simul#tion ,0m 11-18 /PP'
0 %#te-leel modeling ,0m 111 /PP'
1 S!itch-leel modeling ,0m 110 /PP'
2 %#te-leel modeling simul#tion ,0m 113-1 /PP'
S!itch-leel modeling simul#tion ,0m 1180-18 /PP'
4 Com*in#tion#l Logic S(nthesis ,0m 113,-133 /PP'
, in#r( Decision Di#gr#ms ,0m 1201-213 /PP'
'!o Leel Logic S(nthesis ,0m 1222-22, /PP'
'!o Leel Logic S(nthesis ,0m 1222-22, /PP'
C$'-II 180m
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UNIT V MODELLING AND S6NTHESIS
S(ll#*us7
:igh leel S(nthesis - :#rd!#re models - Intern#l re&resent#tion - $lloc#tion -
#ssignment #nd scheduling - Sim&le scheduling #lgorithm - $ssignment
&ro*lem 5 :igh leel tr#ns"orm#tions.
Objective:
'o underst#nd the conce&t o" #rious s(nthesis #nd scheduling #lgorithm in C$D VLSI.
LESSON PLAN LP VL9!
LP "ev# N$: %%
Date: &'%('!)
Pa*e %! $+ %(
Sub ,$-e'Na.e: VL9!/,AD 0O" VLSI ,I",UITS
U1it : V 23a1c4 : E, Se.este3: III
Sessi$1
N$#
T$5ics t$ be c$ve3e- Ti.e "e+ Teac4i1*
Met4$-
8 :igh leel S(nthesis ,0m 12,-2 /PP'
3 :#rd!#re models ,0m 12-28 /PP'
40 Intern#l re&resent#tion 100m 123-24, /PP'
42 $lloc#tion ,0m 124-2,1 /PP'
44 #ssignment #nd scheduling 100m 124-2,1 /PP'
4 Sim&le scheduling #lgorithm 100m 12,-20 /PP'
48 $ssignment &ro*lem ,0m 121-2, /PP'
,1 :igh leel tr#ns"orm#tions ,0m 12-20 /PP'C$'-III ,m
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"E0E"EN,ES:
1. S.:. %ere+ ?$lgorithms "or VLSI Design $utom#tion? @ohn ;ile( A Sons 2002.
2. >.$. Sher!#ni ?$lgorithms "or VLSI Ph(sic#l Design $utom#tion? Blu!er $c#demic
Pu*lishers 2002.
LESSON PLAN LP VL9!
LP "ev# N$: %%
Date: &'%('!)
Pa*e %! $+ %(
Sub ,$-e'Na.e: VL9!/,AD 0O" VLSI ,I",UITS
U1it : I /V 23a1c4 : E, Se.este3: III
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