Post on 18-Jan-2018
description
http://wwwhephy.oeaw.ac.at/p3w/cms/trigger
Vienna GroupVienna Group
Discussion Meeting on LuminosityCERN, 9 May 2006
Presented byClaudia-Elisabeth WulzClaudia-Elisabeth Wulz
Luminosity and theLuminosity and theGlobal TriggerGlobal Trigger
A. Taurok, I. Magrans de Abril, C.-E. WulzA. Taurok, I. Magrans de Abril, C.-E. Wulz
C. - E. Wulz Luminosity Meeting, May 20062
Global Trigger Crate
L1 GLOBAL TRIGGER 9U Crate
CLK,BCRES, L1A
8 FinOR +8 TechTrig
A.T. 16.3.04
PC: RUN Control
4MUONS
VME
VME
VME
Top viewFRONT SIDE BACK SIDE
GTL9U
GTL9U
BACKPLANESIGNALS
TIM6UTTC
4TAU, ET*, JetNr, 4 free(ET*=total E T,HT,ME T)
Technical Triggersignals
4IEG, 4EG, 4JET, 4fJET
PSB9U
PSB9U
PSB9U
RO-data13 ChLinks
slot not used
8 RPC, 4 DT4 CSC muons
12 CABLESMIP/QUIET
PSB9U
PSB9U
PSB9U
GMT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
SLOT_Nr
L1A_OUT
32 TTCciTTC racks
TTS racks
ConvCrate
GCT crate
M/Q bits
GCT data
L1A, Bgo32 cables to 32 TTCci
FDL9U128 Algo
Status Signals
TCS 9U
PSB9U
L1A_OUT
TOTEM
EmuCrate
aTTSDAQ
APVE
128 ALGOs
S-links: DAQ, EVM GTFETTC - GPS
PSB (Pipelined Synchronizing Buffer)Input and Synchronisation
GMT (Global Muon Trigger)Global Muon Trigger logicGTL (Global Trigger Logic) Algorithm logic
FDL (Final Decision Logic) Level-1 Accept decision
GTFE (Global Trigger Frontend) Readout
TCS (Trigger Control System Module) Central Trigger Control
L1A_OUT (Level-1 Accept Module) Distribution of Level-1 Accept
CONV6U (Conversion Boards) Reception of status signals from the subsystems
TIM (Timing Module) Timing
C. - E. Wulz Luminosity Meeting, May 20063
Final Decision Logic (FDL) Board
C. - E. Wulz Luminosity Meeting, May 20064
FDL functionality
The Final Decision Logic (FDL) board receives 128 algorithm bits from the Global Trigger Logic (GTL) board and 64 Technical Trigger bits from a dedicated Pipeline Synchronizing Buffer input board (PSB0).
8 Final OR’s are available (only 1 in normal running).
A mask (also a veto mask for technical triggers if required) is applied to the 128 + 64 algorithm bits to determine the Final OR’s.
The Final OR’s go to the Trigger Control System (TCS) board, which delivers the L1A signals to the front-end electronics through two L1AOUT boards.
C. - E. Wulz Luminosity Meeting, May 20065
FDL block diagram
VME
INTERFACE
IDC connectors
4(6) x 32 bitsCLOCK
L1A BCRES RESET
JTAG
CHANNEL LINK
LVDS signals
FDL9U board
8 Final_OR 8 Techn_OR
LVTTL
40 MHz parallel
VME160
ZPACK
2mm
ZPACK
2mm
POWER
+1.5V/3A
+2.5V/3A
LEDs
STATUS bits
Technical Trigger bits
CHANNEL LINK
DAQ_record
EVM_record
128 ALGO bits
32 Technical Trigger bits
FDL chip
XC2V2000-4BF957
DOWN
SCALERS
RING
BUFFER
DERANDOMIZING BUFFERS
READOUT CIRCUITS
STATUS logic
Registers,
Mask bits
RATE
cntrs
2x8
Final
OR
Rate counters monitor each trigger algorithm bit and prescalers downscale the average rate if required (maximum reduction factor 216 = 65536, down to 600 Hz). Each algo and technical trigger bit first goes to the corresponding prescaler. Each prescaled trigger bit then goes to a rate counter and the ring buffer for readout.
C. - E. Wulz Luminosity Meeting, May 20066
FDL Rate counters
• 128 rate counters for physics triggers• 64 rate counters for technical triggers
All these counters are currently 16-bit, which overflow after 0.6 s at 100 kHz. A mimimal number of 32-bit counters, which overflow after 11.9 h at 100 kHz, could be implemented for algorithms used for luminosity measurement. How many depends on space of the chip. TBD!
Rate counters stop at ‘FFFF’. The update period of these counters is programmable (8 possible values from 10-5 s to 105 s). Each time a counter is reset its value is moved to the RATE_COUNTER register, which can be read out through VME. The values will be stored in the Conditions Database, and should be accessible for monitoring from there.
C. - E. Wulz Luminosity Meeting, May 20067
L1AOUT, TCS
C. - E. Wulz Luminosity Meeting, May 20068
TCS functionality
The central Trigger Control System (TCS) board controls instantaneous and average L1A rates according to:- trigger throttling rules- emulation of front-end buffers- status of subdetector partitions
It generates fast commands (BCRes, L1Reset and other Bgo commands) to be distributed to the subdetectors by the TTC network.
It generates calibration and test trigger sequences.
It has several counters for monitoring purposes, including dead-time counters.
C. - E. Wulz Luminosity Meeting, May 20069
TCS block diagram
C. - E. Wulz Luminosity Meeting, May 200610
Monitoring and dead-time counters on TCS chip
Counters in each of the 8 DAQ partitions:
- Nr. of beam crossings (BC) where L1A was inhibited (dead-time counter for all BC).- Nr. of active (according to LHC BC structure) BC where L1A was inhibited (dead-time counter for active BC).- Nr. of BC where L1A was inhibited and L1A is true (lost triggers).- Nr. of distributed physics triggers (physics L1A with dead-time).- Orbit nr. (32-bit).
C. - E. Wulz Luminosity Meeting, May 200611
Monitoring and dead-time counters on TCS chip
Counters existing only DAQ partition 0 (DAQ0):
- Nr. of active BC where L1A was inhibited by private orbits.- Nr. of active BC where L1A was inhibited by subdetector partitions.- Nr. of active BC where L1A was inhibited by trigger throttling rules.- Nr. of active BC where L1A was inhibited by calibration or test cycles.- Nr. of physics triggers (physics L1A without dead-time). Note that FDL has counters for all Final OR’s and technical triggers.- Nr. of distributed calibration triggers.- Nr. of distributed random (test) triggers.- Nr. of missing BC (no beam).- Event number (total number of distributed L1A for all partitions, for EVM).
Note that the requested dead-time counters for normal rate (all DAQ partitions) and throttled rate (only DAQ0 partition) are now available.
C. - E. Wulz Luminosity Meeting, May 200612
L1AOUT
2 LVDS signals on an Ethernet connector are available to gate luminosity counters:
LUM1: Running (reset by start/stop)
LUM2: Active time for L1A(OR of all dead-times, inverted)
C. - E. Wulz Luminosity Meeting, May 200613
Trigger Supervisor Monitoring and Conditions DB
XDAQ executive
FL1.xml
XDAQ executive
FL2.xml
Monitor Collector
FL1.xml
Control Cell #1 (GT/TCS Leaf)
FL1.xml
Monitor Sensor
XDAQ executive
Control Cell #2 (Other subsystem Leaf)
Monitor Sensor
pull pull
DataSource DataSourceFL2.xml
Cell (TS)
Cell (#2) Cell (#1)
Controller side
TS client (Web page)
L1-Trigger Conditions
DB
Luminosity DB
Luminosity Server
I. Magrans
C. - E. Wulz Luminosity Meeting, May 200614
Summary
The FDL, TCS and L1AOUT boards are relevant for The FDL, TCS and L1AOUT boards are relevant for luminosity.luminosity.
Counters for measuring rates and dead-times are Counters for measuring rates and dead-times are available on FDL and TCS boards.available on FDL and TCS boards.
Counters can be accessed though VME for monitoring Counters can be accessed though VME for monitoring purposes.purposes.
The luminosity monitoring will be integrated in the The luminosity monitoring will be integrated in the central monitoring, using the Conditions Database and central monitoring, using the Conditions Database and the Trigger Supervisor.the Trigger Supervisor.