VHDL - Introduction - · PDF fileBehavioral, structural, ... Library declaration in VHDL 8...

TDT4255 Fall-2011 VKG@NTNU

VHDL - Introduction

TDT4255: Hardware Design Vinay Gautam (vkgautam@idi.ntnu.no)

Requirements /specification

Simulation Behavioural

RTL Model (in VHDL)

Gate-level Model

Synthesize

Simulation Gate-level

Test Bench (in VHDL)

Place & Route

Bit file

Basic FPGA based HW design flow

Basic things about VHDL

VHDL- Very high speed Integrated circuit Hardware Description Language

What is HDL and how does it differs from programming languages like C?

How to learn VHDL?

most „reliable‟ design process, with minimum cost and time

avoid design errors!

Applications of HDL

Model and document digital systems

Different levels of abstraction

Behavioral, structural, etc.

Verify design

Synthesize circuits

Convert from higher abstraction levels to lower abstraction levels

General template for VHDL description

Library declarations

Entity

Architecture

An example

AND-OR-INVERT GATE

-- VHDL code for AND-OR-INVERT gate

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity AOI is

port (

A, B, C, D: in STD_LOGIC;

F : out STD_LOGIC

end AOI;

architecture V1 of AOI is

F <= not ((A and B) or (C and D));

end V1;

-- end of VHDL code

Library declaration section

Entity declaration

Architecture body

-- comment

Library declaration in VHDL

Library

packages

Functions procedures components

Library IEEE; Use ieee.std_logic_1164.all;

Library std; Use std.standard.all;

Library declaration:

Library library_name; Use library_name. package_name.package_parts;

1.ieee.std_logic_1164 2.standard 3.work

These are three essential packages From three different libraries

By default visible, NO NEED TO DECLARE

Library contd..Be careful!!

STD_LOGIC_ARITH……….. This specifies the signed and unsigned data types and related arithmetic/comparison operators

STD_LOGIC_SIGNED………This contains the functions that allows operations with STD_LOGIC_VECTOR to be performed as if the data were of type SIGNED

STD_LOGIC_UNSIGNED….same as STD_LOGIC_SIGNED case but treats like UNSIGNED

IEEE.NUMERIC_STD.all.... IEEE standard to avoid the problems involved with earlier three………FIND OUT WHAT WERE THE PROBLEMS???

ENTITY Input-Output specification of circuit

entity AOI is

port (

A, B, C, D: in STD_LOGIC;

F : out STD_LOGIC

end AOI;

A couple observations concerning the entity declaration…

entity, port, is – these are keywords/reserved words in VHDL

A, B,C and D are input 1 bit STD_LOGIC

F is an output 1 bit STD_LOGIC

The entity declaration describes the entity being modeled – it‟s a black box view.

Entity declaration from last example

Port maps and modes

These port declarations describe the signals coming in and out of the entity. The mode describes the direction in which data is transferred through a port…

in – data flows into the entity out – data flows out of the entity buffer – data flows out but is also available for internal feedback (can act as a driver within the architecture body)

data only flows out – cannot drive this signal externally. May not have multiple drivers

in/out – can do all of the above (really do not want to do this unless you need to)

Data Types in VHDL

• Package standard of library STD: Defines BIT,BOOLEAN,INTEGER and REAL • Package std_logic_1164 of library IEEE: Defines STD_LOGIC and STD_ULOGIC • BIT •BOOLEAN •INTEGER •REAL •STD_LOGIC

Data Types contd..

BIT-DATA TYPE ------- (0,1) Signal x: BIT -- x is declared as a one digit signal of type bit Signal y: BIT_VECTOR (3 DOWN TO 0) -- y is a 4 bit vector with the left most bit being MSB X<=„1‟…………………..single quotes are used for single bit Y<=“0111”……………….y is a 4-bit signal (bit_vector) and double quotes are used for vectors

Data Types contd…

BOOLEAN-DATA TYPE…….(TRUE,FALSE) Ex. Variable test:BOOLEAN:=FALSE; CHARACTER …….(ANY LEGAL VHDL CHARACTER) Ex. Variable val: CHARACTER:=„$‟; INTEGER ……..range -(2^31-1) to (2^31-1) Constant constt: INTEGER:=236; NATURAL…….range starting from 0 to max specified REAL…… range -1.0x10^38 to 1.0x10^38 Not supported by synthesis POSITIVE… range 1 to max specified

STD_LOGIC and STD_LOGIC_VECTOR

type STD_LOGIC is ( „U‟ -- undefined „X‟ -- forcing unknown „0‟ -- forcing 0 „1‟ -- forcing 1 „Z‟ -- high impedance „W‟ -- weak unknown „L‟ -- weak 0 „H‟ -- weak 1 „-‟ -- don‟t care );

Notice that std_logic is an enumeration

type, itself. It is used to represent physical wire states.

The IEEE 1164 standard describes std_logic, which represents a physical wire/signal…

STD_LOGIC contd…

Signal x: STD_LOGIC -- x is declared as a one digit (scaler) signal of type STD_LOGIC Signal y: STD_LOGIC_VECTOR (3 down to 0):=“0001”;

User-defined datatype

Construct datatypes arbitrarily or using built-in datatypes

Examples: type temperature is (high, medium, low);

type byte is array(0 to 7) of bit;

Operators in VHDL

Logic operators

Logic operators precedence

and or nand nor xor not xnor

and or nand nor xor xnor

Highest

Lowest

only in VHDL-93

and later

19 TDT4255 Fall-2011 VKG@NTNU

Arithmetic Operators

Integer operations

+ addition

- subtraction

* multiplication

/ division

mod modulo division

rem modulo remainder

abs absolute value

** exponentiation

Concatenation SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);

a <= "0000";

b <= "1111";

c <= a & b; -- c = "00001111"

d <= '0' & "0001111"; -- d <= "00001111"

e <= '0' & '0' & '0' & '0' & '1' & '1' &

'1' & '1'; -- e <= "00001111"

a(3) a(2) a(1) a(0)

a(2) a(1) a(0) a(3)

a_rotL <= a(2 down to 0) & a(3);

Rotations in VHDL

Shifts in VHDL (zero-stuff)

a(3) a(2) a(1) a(0)

a(2) a(1) a(0) a(3)

a_shiftL <= a(2 downto 0) & ‘0’;

Be careful if doing sign-extension

‘0’

Shifts in VHDL (using libraries)

Using std_logic_arith package:

function SHL(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;

function SHL(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;

function SHR(ARG: UNSIGNED; COUNT: UNSIGNED) return UNSIGNED;

function SHR(ARG: SIGNED; COUNT: UNSIGNED) return SIGNED;

Make sure your syntax is correct

I Recommend not using these functions, but "hard-wiring" the shifts as in previous examples

Relational operators

Logic and relational operators precedence

= /= < <= > >=

and or nand nor xor xnor

Highest

Lowest

Operators

compare a = bc

Incorrect

… when a = b and c else …

equivalent to

… when (a = b) and c else …

Correct

… when a = (b and c) else …

Priority of Logic and Relational Operators

VHDL Design Styles (Architecture)

STRUCTURAL

components and

interconnects

VHDL Design

Styles

DATAFLOW

“concurrent”

statements • State machines

• Registers

• Complex Comb.

“sequential” statements

NON- SYNTHESIZABLE

SYTHESIZABLE

BEHAVIORAL

• Test Benches

• Modeling IP • Gates

• Simple Comb.

Combinational

Logic Combinational

Registers

Register Transfer Level (RTL) Design Description (synthesizable VHDL!!)

Data flow style

The dataflow model is written as a set of concurrent assignment statements.

It specifies how data is transferred through the system.

There are no process statements. Rather dataflow modeling using simple equations, when-else, with-select-when, and some other forms.

These statements are evaluated concurrently!!!, not sequentially!

Example of data flow style

architecture my_full_adder of full_adder is begin sum <= a xor b xor cin; cout <= (a and b) or (b and cin) or (a and cin); end my_full_adder;

…..Using equations

library ieee; use ieee.std_logic_1164.all; entity eqcomp8 is port ( a,b: in std_logic_vector(7 downto 0); equals: out std_logic); end eqcomp8; architecture dataflow of eqcomp8 is ( begin equals <= „1‟ when (a = b) else „0‟; -- equals is active high end dataflow;

…..Using when-else

y <= x0 when sel = 0

else x1 when sel = 1

x1 4:1 MUX:

……With select-when

Structural style

-- VHDL structural modelling

architecture struct_V1 of AOI is signal AB,CD,o: STD_LOGIC; component AND2 is port(a,b : in std_logic; c: out std_logic); end component; component OR2 is port (a,b:in std_logic; c: out std_logic); end component; Component INVERTER is Port a: in std_logic; B: out std_logic); End component; Begin U1: AND2 port map (A,B,AB); U2: AND2 port map (C,D,CD); U3: OR2 port map (AB,CD,o); U4: INVERTER port map (o,F) end struct_V1; -- end of VHDL code

Sequential style library ieee;

use ieee.std_logic_1164.all;

entity dff_async_reset is

port ( data :in std_logic; -- Data input

clk :in std_logic; -- Clock input

reset :in std_logic; -- Reset input

q :out std_logic -- Q output );

end entity;

architecture rtl of dff_async_reset is

process (clk, reset)

if (reset = '0') then q <= '0';

elsif (rising_edge(clk)) then

q <= data; end if;

end process; end architecture;

Clk‟event and clk=„1‟

Sequential style contd..

Includes process statement

Inside the process statement the code is executed sequentially line by line

In an architecture there can be multiple processes but all processes will be mutually concurrent

In sensitivity list of process, include all the signals used in right hand side of operators and also left hand signals those are being compared with others.

Signals vs Variables

Signals

Signals follow the notion of „event scheduling‟

An event is characterized by a (time,value) pair

Signal assignment example:

X <= Xtmp; means

Schedule the assignment of the value of signal Xtmp to signal X at (Current time + delta)

where delta: infinitesimal time unit used by simulator for processing the signals

Signals vs Variables

Variables Variables do not have notion of „events‟ Variables can be defined and used only inside the

process block and some other special blocks.

Variable declaration and assignment example: process (…)

variable K : bit;

-- Assign the value of signal L to var. K immediately

K := L;

end process;

Variables can only be defined and used inside the process

construct and can be defined only in this place

BEHAVIORAL ( Processes using signals)

Sig2 = 1

Sig1 = 2 + 3 = 5

Sig3 = 2

Sum = 1 + 2 + 3 = 6

BEHAVIORAL ( Processes using Variables)

var1 = 2 + 3 = 5

var2 = 5

var3 = 5

Sum = 5 + 5 + 5 = 15

Sequential statements

If –then-else statement

elsif statement

Reusability feature in VHDL: Components, Packages

A component represents an entity-architecture pair.

Component allows hierarchical design of complex circuits.

• A component instantiation statement defines a part lower in the

hierarchy of the design entity in which it appears. It associates ports

of the component with the signals of the entity. It assigns values to

the generics of the component.

• A component has to be declared in either a package or in the

declaration part of the architecture prior to its instantiation.

Component

• Syntax(Declaration)

component component_name

[generic list]

[port list]

end component;

Component Declaration and Instantiation

• Syntax(Instantiation) label:component_name

[generic map]

port map;

entity my_and is

port( a : in std_logic;

b : in std_logic;

c : out std_logic);

end my_and;

architecture my_and_A of my_and is

component and2

generic (tpd: time := 2 ns);

port (x : in std_logic;

y : in std_logic;

z : out std_logic);

end component;

signal temp : std_logic;

c <= temp;

-- component instantiation here

end my_and_A;

U1: my_and

generic map (tpd => 5 ns)

port map (x => a,

y => b,

z => temp);

U2: my_and

port map (x => a,

y => b,

z => temp);

Example

architecture exor_A of exor is

component my_or

port (a : in std_logic;

b : in std_logic;

y : out std_logic

end component;

component my_and

port (a : in std_logic;

b : in std_logic;

y : out std_logic

end component;

signal a_n, b_n : std_logic;

signal y1, y2, y3 : std_logic;

. . . . .

end exor_A;

u1 : my_or

port map (y2,

u2 : my_and

port map (a_n,

u3 : my_and

port map (a,

a_n <= not a ;

b_n <= not b ;

Positional association

Named Association

U1:my_and

port map (x => a,

y => b,

z => temp);

U1: my_and

generic map(5 ns)

port map(a, b, temp);

Port and generic association in component

The formal and the actual can have the same name

Packages

Multiple VHDL model descriptions tend to use the same component declarations, etc.

Lots of wasted effort to repeat declarations

Good opportunities for mistakes

Packages provide a method for collecting common declarations in a central location

Package declarations can then be reused by referencing the package via ‘use’ statement

E.G. Use WORK.LOGIC_OPS.All;

Package Definition Example

package LOGIC_OPS is

component AND2_OP port (A, B: in BIT; Z: out BIT);

end component; component OR2_OP

port (A, B: in BIT; Z: out BIT); end component; component NOT_OP

port (A: in BIT; Z: out BIT); end component;

end LOGIC_OPS;

Example of Package Usage

entity XOR2_OP is port (A, B: in BIT; Z: out BIT);

end XOR2_OP; use WORK.LOGIC_OPS.all architecture STRUCT of XOR2_OP is

signal ABAR, BBAR, I1, I2: BIT; begin

N1: NOT_OP port map (A, ABAR); N2: NOT_OP port map (B, BBAR); A1: AND2_OP port map (A, BBAR, I1); A2: AND2_OP port map (B, ABAR, I2); O1: OR2_OP port map (I1, I2, Z);

end STRUCT;

Library

Package

Finite State Machines (FSMs)

What is an FSM?

Two types:

Figure from Computer Organization & Design. 2nd Ed. (Patterson,

Hennessy)

Moore FSM

Output depends ONLY on current state

Outputs associated with each state are set at clock transition

Mealy FSM

Output depends on inputs AND current state

Outputs are set during transitions

FSMs in VHDL

Finite State Machines can be easily described with processes

Synthesis Tools Understand FSM Description If Certain Rules Are Followed

State transitions should be described in a process sensitive to clock and asynchronous reset signals only

Outputs described as concurrent statements outside the process

FSM States (1)

architecture behavior of FSM is

type state is (list of states);

signal FSM_state: state;

process(clk, reset)

if reset = ‘1’ then

FSM_state <= initial state;

case FSM_state is

FSM States (2)

case FSM_state is

when state_1 =>

if transition condition 1 then

FSM_state <= state_1;

end if;

when state_2 =>

if transition condition 2 then

FSM_state <= state_2;

end if;

end case;

end if; end process;

Test bench in VHDL

VHDL test bench is VHDL code that produces stimuli to test your design correctness

It can automatically verify accuracy of the VHDL code Given a known input, does the

system generate the expected output

Verifies that the VHDL code meets the circuits specifications

Test benches should be easily modified, allowing for future use with other code

Should be Easy to understand the behavior of the test bench

Test bench contd..

Test bench contd…

entity TEST_MUX4 is end; library IEEE; Use IEEE.STD_LOGIC_1164.all; architecture BENCH of TEST_MUX4 is component MUX4 ... end component; -- signals begin -- signal assignments to create

stimulus M: MUX4 port map (...); end BENCH;

entity TEST_MUX4 is

library IEEE;

use IEEE.STD_LOGIC_1164.all;

architecture BENCH of TEST_MUX4 is

component MUX4

port (SEL :in STD_LOGIC_VECTOR(1 downto 0);

A, B, C, D:in STD_LOGIC;

F :out STD_LOGIC);

end component;

signal SEL: STD_LOGIC_VECTOR(1 downto 0);

signal A, B, C, D, F: STD_LOGIC;

begin SEL <= "00", "01" after 30 NS, "10" after 60 NS, "11"

after 90 NS, "XX" after 120 NS, "00" after 130 NS;

A <= 'X', '0' after 10 NS, '1' after 20 NS;

B <= 'X', '0' after 40 NS, '1' after 50 NS;

C <= 'X', '0' after 70 NS, '1' after 80 NS;

D <= 'X', '0' after 100 NS, '1' after 110 NS;

M: MUX4 port map (SEL, A, B, C, D, F);

end BENCH;

Thank you for attention

VHDL - Introduction - · PDF fileBehavioral, structural, ... Library declaration in VHDL 8...

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