Post on 05-Sep-2020
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-1
Course contents
Introduction
Digital design
Combinatorial circuits: without status
Sequential circuits: with status
FSMD design: hardwired processors
Language based HW design: VHDL
Electrical aspects of HW design
Microprocessors
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-2
• Introduction• First look• Language
elements• Hardware
description• Simulation• Synthesis
Introduction
A first look at VHDL
VHDL language elements
Hardware description using VHDL
VHDL hardware simulation
VHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-3
Definition
Introduction• First look• Language
elements• Hardware
description• Simulation• Synthesis
Acronym VHDL:VHDL = VHSIC Hardware Description LanguageVHSIC = Very High Speed Integrated Circuit
What is VHDL?1. A programming language for describing the behavior
of digital systems2. Design entry language, used for
unambiguous specification at behavioral andRTL levelsimulationsynthesisdocumentation
Standardization: IEEE 1076First version: VHDL-87Second version: VHDL-93Third version: VHDL-2001
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 VHDL versus schematics: drawbacks
6-4
Introduction• First look• Language
elements• Hardware
description• Simulation• Synthesis
VHDL is easy to learn but hard to master.Semantics are quite different from software languages.VHDL is said to have a difficult syntax.Use language sensitive editors with templates for all language constructs.
VHDL is very ‘wordy’.Lots of code to type for just a few simple things.A list of instructions is less intuitive to understand than a block diagram for a human being.VHDL is designed to make simulation efficient: contains aspects that have hardly anything to do with hardware behavior, but is useful tospeed-up event driven simulation.
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 VHDL versus schematics: advantages
6-5
Introduction• First look• Language
elements• Hardware
description• Simulation• Synthesis
Easier to capture complex circuits: higher level of abstraction with automated synthesis
you specify ‘add’ instead of jotting down a specific type of adder: the synthesis tool will instantiate the best type of adder under timing, area & power constraintseasy to parameterize(e.g., word length, queue depth)easy to specify arrays of components
Portable across many tools for simulation, synthesis, analysis, verification, … of different vendors (e.g., Synopsys, Mentor Graphics, …)
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-6
Limitations of VHDL
Introduction• First look• Language
elements• Hardware
description• Simulation• Synthesis
The standard only describes syntax and semantics, but not the coding style.
You can specify the same behavior (e.g., MUX) in an almost unlimited number of wayseach leading to a completely different implementation (e.g., Multiplexer or tri-state bus)which is synthesis tool dependent.You should do lots of experimentation with style-tool combinations to be able to predict how the hardware will look like that will be synthesized.
Is prediction necessary?You also do not predict the ASM generated by C;C is less efficient than ASM but faster to write.Currently, it is hard to tolerate the inefficiency caused by the higher level specification for hardware.
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-7
Limitations of VHDL
Introduction• First look• Language
elements• Hardware
description• Simulation• Synthesis
Only a subset of VHDL can be automatically synthesized; each vendor supports a different subset.Only digital; special extension (not yet widely adopted) for analog: VHDL-AMS (acronym for VHDL Analog and Mixed Signal)
IEEE standard 1076.1-1999is a super-set of the full IEEE VHDL 1076-1993 standard for digital designadds the continuous time model to the existingevent-driven model of digital VHDL:the continuous time model consists of a set of simultaneous differential and algebraic equationsmore info on http://www.vhdl.org/vhdl-ams/ and http://www.vhdl-ams.com/
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-8
Abstraction levels
Introduction• First look• Language
elements• Hardware
description• Simulation• Synthesis
BehavioralInterconnected functionsOnly info on functions or algorithms (what)Only timing needed to let the function work correctlyOK for VHDLBehavioral synthesizers immature; used for high level executable specification in top-down design and manual synthesis into RTLSee course:“Architectuursynthese en -compilatie”
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-9
Abstraction levels
Introduction• First look• Language
elements• Hardware
description• Simulation• Synthesis
RTLInterconnected registers and combinatorial unitsInfo on function (what) and architecture (how)Cycle accurateNo technology dependent timing infoOK for VHDLGood synthesizers
Gate levelInterconnected gates and flip-flopsInfo on function and architectureInfo on technology dependent timing (gate delays)
LayoutInfo on layout on siliconContinuous timingAnalog effects
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 OtherHardware Description Languages
6-10
Verilog (IEEE 1364)More widespread in USA than in EuropeSyntactic roots in C ⇔ VHDL more like AdaOften required for gate level or RTL level ASIC sign-offNever ending discussion which is better
but “Both languages are easy to learn and hard to master. And once you have learned one of these languages, you will have no trouble transitioning to the other.”
PLD languages like ABEL, PALASM, …These are more at the gate level, capturing also technology dependent features (e.g., detailed timing)
Introduction• First look• Language
elements• Hardware
description• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-11
• IntroductionFirst look
• Language elements
• Hardware description
• Simulation• Synthesis
Introduction
A first look at VHDL
VHDL language elements
Hardware description using VHDL
VHDL hardware simulation
VHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-12
Example 1: task description
• IntroductionFirst look
• Language elements
• Hardware description
• Simulation• Synthesis
Design a circuit named ‘Test’ with
three 8-bit inputs (In1, In2, In3)
two boolean outputs:
Out1 = 1 ⇔ In1 ≡ In2
Out2 = 1 ⇔ In1 ≡ In3
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-13
Schematic specification (1)
• IntroductionFirst look
• Language elements
• Hardware description
• Simulation• Synthesis
The circuit will be hierarchically decomposed into a top level component ‘Test’ containing two instantiations of a comparator component ‘Compare’.
In1
In2
In3
Test
Out1
Out2
Compare
A
BEQ
Compare
A
BEQ
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-14
Schematic specification (2)
• IntroductionFirst look
• Language elements
• Hardware description
• Simulation• Synthesis
The comparator is then hierarchically decomposed into a gate level combinatorial circuit.
A
B
EQ
Compare
A[0]
B[0]
A[1]
B[1]
A[7]
B[7]
EQ
XNOR
AND
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-15
Entity and Architecture
• IntroductionFirst look
• Language elements
• Hardware description
• Simulation• Synthesis
Declaration of the ‘Compare’ design entity:-- Eight bit comparator--entity Compare isport(A,B: in bit_vector(0 to 7);
EQ: out bit);end entity Compare;
architecture Behav1 of Compare isbeginEQ <= '1' when (A=B) else '0';
end architecture Behav1;
‘Entity’ specifies the interface to the circuit, the
black box of a schematic
Input and output signals are called ‘ports’
‘Architecture’ describes the behavior and structure of
the entity, the internals of the box
Notes:• Multiple architectures per entity are possible:
different ways of implementing same behavior• This architecture specifies behavior at RTL level and not the
actual structure of gates; synthesis tool will automatically translate this RTL behavioral description into gate level
• Ports have an explicit direction and are (vectors of) bits
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-16
Component and Instantiation
• IntroductionFirst look
• Language elements
• Hardware description
• Simulation• Synthesis
Specification of the next higher level ‘Test’:-- Dual comparator Test component--entity Test isport(In1,In2,In3: in bit_vector(0 to 7);
Out1,Out2: out bit);end entity Test;
architecture Struct1 of Test iscomponent Comparator isport(X,Y: in bit_vector(0 to 7);
Z: out bit);end component Comparator;beginCompare1: component Comparator port map (In1,In2,Out1);Compare2: component Comparator port map (In1,In3,Out2);
end architecture Struct1;
Virtual device: allows for concurrent development of both hierarchical levels, by
different persons. ‘Comparator’ will be bound
to ‘Compare’ later
Two instantiations of the same component with its signal bindingNotes:
• The two ‘comparator’ components work concurrently!• This architecture describes structure, i.e., how this entity consists
of an interconnection of lower level components.
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-17
Configuration
• IntroductionFirst look
• Language elements
• Hardware description
• Simulation• Synthesis
When an entity has multiple architectures, how do you indicate which one to use?How do you bind ‘Components’ to ‘Entities’?
-- Configuration information: architecture selection-- and component-entity binding
configuration Build1 of Test isfor Struct1for Compare1: Comparator use entity Compare(Behav1)port map (A => X, B => Y, EQ => Z);
end for;for others: Comparator use entity Compare(Behav1)port map (A => X, B => Y, EQ => Z);
end for;end for;
end configuration Build1; Both ‘use entity’s could be combined in one:
for All: Comparator ...Note:• ‘configuration’ corresponds in software to ‘linking’
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-18
Comparison with C
• IntroductionFirst look
• Language elements
• Hardware description
• Simulation• Synthesis
This is very similar to software programming languages, e.g., C
/* Eight bit comparator */
int Compare(int A, int B)
{return (A == B);
}
Interface to the function
Inputs and outputs arecalled ‘arguments’
Behavior of the function
Notes:• Only one behavior per function possible• Behavior is specified at rather high level and will be automatically
translated by the compiler into ASM instructions• Function arguments do not have a direction and are of type int
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-19
Comparison with C
• IntroductionFirst look
• Language elements
• Hardware description
• Simulation• Synthesis
This is how the higher hierarchical level looks like in C
/* Dual comparator Test program */
main(){
int In1, In2, In3;int Out1, Out2;
Out1 = Compare(In1, In2);Out2 = Compare(In1, In3);
}
Two calls to the function‘Compare’ with itsargument binding
Notes:• The two ‘compare’ function calls are executed sequentially.• This main program is executed once and stops. In VHDL, all
components describe relations that are valid continuously and forever.
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 HDLs versus traditional programming languages
6-20
• IntroductionFirst look
• Language elements
• Hardware description
• Simulation• Synthesis
Concurrency:all hardware components operate in parallel
Data types:support is needed for arbitrary size integers, bit vectors, fixed point numbers
Concept of time
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-21
IntroductionA first look at VHDLVHDL language elements
Lexical elementsData objects & typesOperationsControl statementsSubprogramsPackages
Hardware description using VHDLVHDL hardware simulationVHDL hardware synthesis
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-22
Lexical elements
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
Comments: from ‘--’ till end of lineIdentifiers (or names)= succession of alpha-numeric characters or
non-successive ‘_’, starting with a letter & not ending with ‘_’: “Next_value_0”Identifiers are case-insensitive!
NumbersInteger literal : whole number “1480”Real literal : fractional number “1480.0”Both can use exponential notation “148E1”‘_’ is allowed but ignored “1_480”Non-decimal bases : base#literal#exp253.5 = 16#FD.8# 2#1#E10 = 16#4#E2
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-23
Lexical elements
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
CharactersCharacter literal = a single character between single quotes : 'a' 'A' '''
StringsString literal = sequence of characters between double quotes : "A string"
Character quoting by doubling :"""Quote it"", she said."
Bit stringsBit string literal = sequence of bits, represented by a string of digits preceded by a base specifier (‘B’, ‘O’, or ‘X’) :O"12" = b"001_010" ⇔ X"a" = B"1010"
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-24
• Introduction• First look
Language elements
LexicalData
objectstypesattributes
OperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
IntroductionA first look at VHDLVHDL language elements
Lexical elementsData objects & types
VHDL objectsVHDL typesAttributes
OperationsControl statementsSubprogramsPackages
Hardware description using VHDLVHDL hardware simulationVHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-25
VHDL objects
• Introduction• First look
Language elements
LexicalData
objectstypesattributes
OperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
= named item that has a value of a specified type
Constantmake model more intelligible
Variabletraditional intermediate result holder without physical meaning
Signalwire, (internal) connectionwaveform visible during simulation
File
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-26
VHDL object declaration
Constantsconstant name(s): (sub)type := expression;
constant num_bytes: integer := 4;constant num_bits: integer := 8 * num_bytes;
Variablesvariable name(s): (sub)type [:= expression];
variable cnt, index: integer := 0;
note: default initial value = first (leftmost) value(e.g., smallest representable integer)
Signalssignal name(s): (sub)type [:= expression];
signal a, b: bit;
comma separated names
initial value
reserved word
• Introduction• First look
Language elements
LexicalData
objectstypesattributes
OperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-27
VHDL object assignment
Variablesname := expression;
index := index + 1;
Signalsname <= waveform;
Simple waveform (synthesis) : expressiony <= a and b;
Complex waveform (simulation) :[delay_mechanism] expression [after time]
[, expression [after time]]…line_out <= transport line_in after 100 ps;pulse <= '1', '0' after T_pw;
• Introduction• First look
Language elements
LexicalData
objectstypesattributes
OperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-28
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
IntroductionA first look at VHDLVHDL language elements
Lexical elementsData objects & types
VHDL objectsVHDL typesAttributes
OperationsControl statementsSubprogramsPackages
Hardware description using VHDLVHDL hardware simulationVHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-29
VHDL (sub)types
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
Type declarationtype name is type_definition;
type int_8 is range -128 to 127;
VHDL typesScalar types : set of valuesComposite types : collection of setsAccess types : pointers for linked listsFile types
Subtype declaration= restricted set of values of base typesubtype name is scalar_(sub)type
[range expression (down)to expression];subtype nat_8 is int_8 range 0 to 127;
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-30
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
IntroductionA first look at VHDLVHDL language elements
Lexical elementsData objects & types
VHDL objectsVHDL types
Scalar types– Composite types
AttributesOperationsControl statementsSubprogramsPackages
Hardware description using VHDLVHDL hardware simulationVHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-31
Scalar type declarations (1)
Discrete typesInteger typesrange integer_expression (down)to integer_expression
type mem_address is range 65535 downto 0;
Enumeration types(name_or_charliteral [, name_or_charliteral]…)
type FSM_state is (reset,wait,input,calculate,output);
type tri_val is ('0', '1', 'Z');
Floating point types range real_expression (down)to real_expression
type probability is range 0.0 to 1.0;
Physical types
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-32
Scalar type declarations (2)
Physical typesrange expression (down)to expressionunits
identifier;[identifier = physical_literal;]…
end units
type length is range 0 to 1E9units
um;mm = 1000 um;m = 1000 mm;km = 1000 m;mil = 254 um;inch = 1000 mil;foot = 12 inch;yard = 3 foot;
end units;
Secondary units
Primary unit:resolution limit
Primary unit
Metric secondary units
Imperial secondary units
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-33
Predefined scalar types (1)
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
Enumeration typestype bit is ('0','1');
type boolean is (false, true);
type character is (ASCII set);identifiers used for non-printable control characters,e.g., nul, cr, lf, esc, del
type severity_level is (note, warning,error, failure);
Integer typestype integer is range implementation_defined;
range at least −231+1 to +231−1 subtype natural is integerrange 0 to integer'high;
subtype positive is integerrange 1 to integer'high;
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-34
Predefined scalar types (2)
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
Floating point typestype real is range implementation_defined;
range at least IEEE 32-bit single precision
Physical typestype time is range implementation_defined
unitsfs;ps = 1000 fs;ns = 1000 ps;us = 1000 ns;ms = 1000 us;sec = 1000 ms;min = 60 sec;hr = 60 min;
end units;
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-35
Standard logic (IEEE 1164)
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
We need more logic levels than just ‘0’ and ‘1’, so IEEE standard 1164 defines 9-valued logic signals & operations.Use always ‘std_logic’ instead of ‘bit’!
library IEEE; use IEEE.Std_logic_1164.all;type std_ulogic is (
'U', -- uninitialized, e.g., after power-up 'X', -- strongly driven unknown
-- e.g., after setup violation'0', -- strongly driven logic zero'1', -- strongly driven logic one'Z', -- high impedance
-- e.g., not driven at all'W', -- weakly driven unknown'L', -- weakly driven logic zero'H', -- weakly driven logic one'-'); -- don’t care
type std_logic is resolved std_ulogic;subtype X01 is resolved std_ulogic range 'X' to '1';
active drivers
resistive drivers
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-36
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
IntroductionA first look at VHDLVHDL language elements
Lexical elementsData objects & types
VHDL objectsVHDL types
– Scalar typesComposite types
AttributesOperationsControl statementsSubprogramsPackages
Hardware description using VHDLVHDL hardware simulationVHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-37
Composite type declarations
Array typesConstrained : bounded indexesarray (range [, range]…) of (sub)typewith range either a discrete subtype or
expression (down)to expressiontype word is array (15 downto 0) of bit;
type next_state isarray (FSM_state, bit) of FSM_state;
variable next: next_state;next(calculate, '1') := output;
Unconstrained : bounds not specifiedarray ((sub)type range <>
[, (sub)type range <>]…) of (sub)typetype sample is
array (natural range <>) of integer;subtype buf_type is sample(0 to 255); variable sample_buf: sample(0 to 63);
Record types
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
multidimensional array
LSB, bit 0
MSB
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-38
Predefined composite types
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
Unconstrained array typestype string isarray (positive range <>) of character;
constant Error_message: string:= "Unknown error: ask your for help";
type bit_vector isarray (natural range <>) of bit;
constant State1: bit_vector(4 downto 0):= "00100";
Predefined in IEEE packages:type std_[u]logic_vector is
array (natural range <>) of std_[u]logic;
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-39
Assigning arrays
When an array is assigned to another array, both arrays must have same sizeAssignment is by position, not by index!
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
signal Down: std_logic_vector (3 downto 0);signal Up: std_logic_vector (0 to 3);Up <= Down;
Which of the two following interpretations is correct?
Up(0)
Up(1)
Up(2)
Up(3)
Down(3)
Down(2)
Down(1)
Down(0)
or
Up(0)
Up(1)
Up(2)
Up(3)
Down(0)
Down(1)
Down(2)
Down(3)
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-39
Assigning arrays
When an array is assigned to another array, both arrays must have same sizeAssignment is by position, not by index!
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
signal Down: std_logic_vector (3 downto 0);signal Up: std_logic_vector (0 to 3);Up <= Down;
Which of the two following interpretations is correct?
Up(0)
Up(1)
Up(2)
Up(3)
Down(3)
Down(2)
Down(1)
Down(0)
or
Up(0)
Up(1)
Up(2)
Up(3)
Down(0)
Down(1)
Down(2)
Down(3)
Correspondence by position!
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-40
Literal array values
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
(Bit) string literalvariable w: word := "1010000101111111";variable w: word := x"A17F";
Array aggregatePositional association(expression [, expression]…)
type point is array (1 to 3) of integer;variable p: point := (4, 5, 5);
Named association(choice [| choice]… => expression
[, choice [| choice]… => expression]…)with choice either an expression, a discrete range
or the keyword othersvariable p: point := (1 => 4 , 2 => 5, 3 => 5);variable p: point := (1 => 4, 2 | 3 => 5);variable p: point := (1 => 4, 2 to 3 => 5);variable p: point := (1 => 4, others => 5);
sample_buf := (others => 0); init irrespective of size
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-41
Array slices
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
= contiguous subset of array elementsMake sure that the direction (to or downto) isthe same as in the declaration!
Constraining array using subtype definitionsubtype halfword is bit_vector(0 to 15);
Assigning parts of arrayssignal Bus: std_logic_vector (7 downto 0);
signal A: std_logic_vector (0 to 3);
Bus <= A;
Bus(0 to 3) <= A;
Bus(3 downto 0) <= A;
Bus(5 downto 4) <= A(0 to 1);
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-41
Array slices
= contiguous subset of array elementsMake sure that the direction (to or downto) isthe same as in the declaration!
Constraining array using subtype definitionsubtype halfword is bit_vector(0 to 15);
Assigning parts of arrayssignal Bus: std_logic_vector (7 downto 0);
signal A: std_logic_vector (0 to 3);
Bus <= A;
Bus(0 to 3) <= A;
Bus(3 downto 0) <= A;
Bus(5 downto 4) <= A(0 to 1);
array sizes do not match
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-41
Array slices
= contiguous subset of array elementsMake sure that the direction (to or downto) isthe same as in the declaration!
Constraining array using subtype definitionsubtype halfword is bit_vector(0 to 15);
Assigning parts of arrayssignal Bus: std_logic_vector (7 downto 0);
signal A: std_logic_vector (0 to 3);
Bus <= A;
Bus(0 to 3) <= A;
Bus(3 downto 0) <= A;
Bus(5 downto 4) <= A(0 to 1);
direction of Bus differs from declaration
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-41
Array slices
= contiguous subset of array elementsMake sure that the direction (to or downto) isthe same as in the declaration!
Constraining array using subtype definitionsubtype halfword is bit_vector(0 to 15);
Assigning parts of arrayssignal Bus: std_logic_vector (7 downto 0);
signal A: std_logic_vector (0 to 3);
Bus <= A;
Bus(0 to 3) <= A;
Bus(3 downto 0) <= A;
Bus(5 downto 4) <= A(0 to 1);OK! Bus(3) is driven by A(0)
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-41
Array slices
= contiguous subset of array elementsMake sure that the direction (to or downto) isthe same as in the declaration!
Constraining array using subtype definitionsubtype halfword is bit_vector(0 to 15);
Assigning parts of arrayssignal Bus: std_logic_vector (7 downto 0);
signal A: std_logic_vector (0 to 3);
Bus <= A;
Bus(0 to 3) <= A;
Bus(3 downto 0) <= A;
Bus(5 downto 4) <= A(0 to 1);
OK! Bus(5) is driven by A(0)
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-42
Array concatenation
= join 2 one-dimensional arraysBring wire bundles together to assign them to a bigger array
signal Byte_bus: bit_vector(7 downto 0);signal Nibble_busA, Nibble_busB:bit_vector(3 downto 0);
Byte_bus <= Nibble_busA & Nibble_busB;
Byte_bus(7)
Byte_bus(6)
Byte_bus(5)
Byte_bus(4)
Byte_bus(3)
Byte_bus(2)
Byte_bus(1)
Byte_bus(0)
Nibble_busA(3)
Nibble_busA(2)
Nibble_busA(1)
Nibble_busA(0)
Nibble_busB(3)
Nibble_busB(2)
Nibble_busB(1)
Nibble_busB(0)
• Introduction• First look
Language elements
LexicalData
objectstypes
scalararray
attributesOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-43
• Introduction• First look
Language elements
LexicalData
objectstypesattributes
OperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
IntroductionA first look at VHDLVHDL language elements
Lexical elementsData objects & types
VHDL objectsVHDL typesAttributes
OperationsControl statementsSubprogramsPackages
Hardware description using VHDLVHDL hardware simulationVHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-44
Attributes
• Introduction• First look
Language elements
LexicalData
objectstypesattributes
OperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
= retrieve information about objects & typesSome examples of predefined attributes
of scalar typesT'left : leftmost value in TT'low : least value in TT'pos(x) : position number of x in T
of array types & objectsA'range[(n)] : index range of dimension nA'length[(n)] : length of index rangeA'left[(n)] : leftmost value in index range
of signalsS'event : true if an event occurred on S in
the current simulation cycleS'last_event : time since last event on S
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-45
User-defined attributes
⇒add non-structural/non-behavioral information or constraintsAttribute declarationattribute name : sub(type);
attribute pin_number : positive;attribute encoding : bit_vector;
Attribute specificationattribute name of name(s) :
class is expression;attribute pin_number of EN_1, EN_2:signal is 14;
attribute encoding of state1:literal is b"0000";
• Introduction• First look
Language elements
LexicalData
objectstypesattributes
OperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-46
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
IntroductionA first look at VHDLVHDL language elements
Lexical elementsData objects & typesOperations:logical, relational, arithmetic & shiftControl statementsSubprogramsPackages
Hardware description using VHDLVHDL hardware simulationVHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-47
Logical operators
List of logical operators:not, and, or, xor, nand, nor, xnorPrecedence:
‘not’ has highest precedenceall others have equal precedence,lower than ‘not’
Logical operators are predefined for following data types: bit[_vector], boolean, std_[u]logic[_vector]A logical operator may work on an array:
arrays should have same sizeelements are matched by position
Returns a (array of) boolean
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
not in VHDL-87
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-48
Relational operators
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
List of relational operators: <, <=, =>, >, =, /=
Both operands need to be of the same type
Relational operators return a boolean
A relational operator may work on an array:Arrays may have different size. They are left aligned and the number of bits equal to the smallest array are compared; the comparison is done bit by bit, from left to right. E.g., "1110" > "10111" is true because the first leftmost bit is identical and the second bit is larger.Although vectors of bits do not have a numerical meaning, this comparison works on vectors of bits with the meaning of an unsigned integer when both vectors have equal length.
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-49
Arithmetic operators
List of arithmetic operators: +, −, *, /,** (exponential), abs (absolute value), mod (modulus), rem (remainder)They are defined on types integer and real (except mod and rem) and not on vectors of bits; use overloading package for the latter (vendor dependent).Both operands have to be of same type; different ranges are allowed.A variable of physical type (e.g., time) may be multiplied by an integer or real and will still return a variable of the physical type.
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-50
Shift operators
List of shift operators: sll (shift-left logical), srl,sla (shift-left arithmetic), sra,rol (rotate left), rorNot defined in VHDL-87.The second operand is an integer. If negative, shift in the opposite direction. The first operand is a 1-D array of bits or booleans. They return the same type.
B"10001010" sll 3 = B"01010000"B"10001010" sll -2 = B"00100010"B"10001010" sra 3 = B"11110001"B"10001010" ror 3 = B"01010001"
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-51
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
IntroductionA first look at VHDLVHDL language elements
Lexical elementsData objects & typesOperationsControl statements:conditional & loop statementsSubprogramsPackages
Hardware description using VHDLVHDL hardware simulationVHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-52
Conditional statements
“if” statementif boolean_expression then
statement(s)[elsif boolean_expression then
statement(s)]…[else
statement(s)]end if;
Notes• Built-in priority: the first condition which turns out to
be true determines which statement(s) are executed
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-53
Conditional statements
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
“case” statementcase expression iswhen choice(s) => statement(s) [when choice(s) => statement(s)]…
end case;
case x iswhen 0 to 4 => y <= 'Z';when 5 => y <= '1';when 7 | 9 => y <= '0';when others => null;
end case;
Requirements1. All possible values should be specified but only once.2. The values should have the same type as the
expression.3. The values should be constant and known at design
time.
evaluated only once
do nothing
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-54
Loop statements
Infinite looploop
statement(s)end loop;
useful in hardware modeling!-- 4 bit counter with output “count”val := 0;loopcount <= val;wait until clk = '1' ;
val := (val + 1) mod 16;end loop;
“exit” statementexit [when boolean_expression];
“next” statementnext [when boolean_expression];
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
wait untilclk becomes '1'
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-54
Loop statements
Infinite looploop
statement(s)end loop;
useful in hardware modeling!-- 4 bit counter with output “count”val := 0;loopcount <= val;wait until clk = '1' ;
val := (val + 1) mod 16;end loop;
“exit” statementexit [when boolean_expression];
“next” statementnext [when boolean_expression];
or reset = '1'exit when reset = '1';
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-55
Loop statements
While loopwhile boolean_expression loop
statement(s)end loop;
For loopfor name in range loop
statement(s)end loop;
The loop variable name• must not be declared;• is only usable inside the loop.
Some examples for range:for i in 0 to 3 loop …for i in an_array'range loop …for state in FSM_state loop …
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-56
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
IntroductionA first look at VHDLVHDL language elements
Lexical elementsData objects & typesOperationsControl statementsSubprograms: procedures & functionsPackages
Hardware description using VHDLVHDL hardware simulationVHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-57
Subprograms
= collection of sequential statementssubprogram_specification is
[constant, variable, (sub)type declaration]…[subprogram]…
beginstatement(s)
end;
Possible subprogram_specification:Procedure: called as a statementprocedure name [(interface_list)]
interface_list is a ‘;’ separated list of[signal] param_name(s) : [mode] (sub)typemode is one of in, out, inout, buffer
Function: called as (a part of) an expressionfunction name [(interface_list)] return (sub)type
At least one of the statement(s) is a return statement:return expression;
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-58
Subprograms
Subprogram callPositional associationname(expression [, expression]…)Named associationname(param_name => expression
[, param_name => expression]…)
Function examplefunction bv_to_nat ( bv : in bit_vector )
return natural isvariable result : natural := 0;
beginfor index in bv'range loopresult := result * 2 + bit'pos(bv(index));
end loop;return result;
end;
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-59
Subprogram name overloading
= allow different subprograms with the same name but different interface lists⇒ context determines which one is used
procedure incr(a : inout integer) is …procedure incr(a : inout bit_vector) is …
To overload operators, quote themfunction "+"(a,b: in bit_vector)
return bit_vector is …function "+" (a: in bit_vector, b: in integer)
return bit_vector is …
Used to implement arithmetic operations on bit vectors (they have no numerical meaning), e.g., in the IEEE packages “numeric_bit” & “numeric_std”.
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-60
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
IntroductionA first look at VHDLVHDL language elements
Lexical elementsData objects & typesOperationsControl statementsSubprogramsPackages
Hardware description using VHDLVHDL hardware simulationVHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-61
Re-use
Often, parts of a design can be re-used in another design: new products in industry often contain 95% of re-used parts and 5% is newly designed (evolutionary design).A ‘Package’ groups definitions of constant values, component declarations, user data types, and sub-programs of VHDL code.A ‘Library’ is the name of the place where the binary code resulting from analysis/compilation is stored (e.g., directory, database entry, ...).Default: work (current working directory)
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-62
VHDL package
Package declaration: interfacepackage name is
[constant, signal, component, (sub)type, attribute, subprogram declaration]…
end [package] [name];
Package body: subprogramspackage body name is
[constant, (sub)type declaration]…[subprogram]…
end [package body] [name];
Package uselibrary library_name;use library_name.package_name.all;
library ieee; use ieee.std_logic_1164.all;
not needed for “work”
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-63
IEEE standard packages
• Introduction• First look
Language elements
LexicalDataOperationsControlSubprogramsPackages
• Hardware description
• Simulation• Synthesis
std_logic_1164
operations on std_[u]logic[_vector]
numeric_bitoperations on [un]signedtype [un]signed is array (natural range <> ) of bit;
numeric_stdidem but on std_logic i.o. bit
math_realoperations on real
math_complexoperations on complex numbers
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-64
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
Introduction
A first look at VHDL
VHDL language elementsHardware description using VHDL
Behavioral hardware descriptionStructural hardware descriptionGenerate statements
VHDL hardware simulation
VHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-65
VHDL digital module description
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
External view : module interface = one entity declaration
entity name is[generic (generic_list);][port (port_list);]
end [entity] [name];generic_list is a ‘;’ separated list ofname(s) : (sub)type [:= expression]port_list is a ‘;’ separated list ofsignal_name(s) : [mode] (sub)type
entity reg isgeneric (width : positive;
T_pd : time := 5 ns);port (D : in bit_vector(0 to width-1);
Q : out bit_vector(0 to width-1);clk : in bit);
end entity reg;
generic constants: instantiation dependant
constants
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-65
VHDL digital module description
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
External view : module interface = one entity declaration
entity name is[generic (generic_list);][port (port_list);]
end [entity] [name];generic_list is a ‘;’ separated list ofname(s) : (sub)type [:= expression]port_list is a ‘;’ separated list ofsignal_name(s) : [mode] (sub)type
entity reg isgeneric (width : positive;
T_pd : time := 5 ns);port (D : in bit_vector(0 to width-1);
Q : out bit_vector(0 to width-1);clk : in bit);
end entity reg;
interface to the entity;absent in top level entities
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-65
VHDL digital module description
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
External view : module interface = one entity declaration
entity name is[generic (generic_list);][port (port_list);]
end [entity] [name];generic_list is a ‘;’ separated list ofname(s) : (sub)type [:= expression]port_list is a ‘;’ separated list ofsignal_name(s) : [mode] (sub)type
entity reg isgeneric (width : positive;
T_pd : time := 5 ns);port (D : in bit_vector(0 to width-1);
Q : out bit_vector(0 to width-1);clk : in bit);
end entity reg;
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-66
VHDL digital module description
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
Generic constantsentity reg isgeneric (width : positive;
T_pd : time := 5 ns);port (D : in bit_vector(0 to width-1);
Q : out bit_vector(0 to width-1);clk : in bit);
end entity reg;
Allows to parameterize behavior as well as port sizes. Enables re-use of entities in slightly changing environments ⇒ makes VHDL much more powerful than schematic entryGeneric constants need to have a value at synthesis time!
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-67
VHDL digital module description
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
Internal view : module implementation = one or more architecture bodies, which
describe alternative implementationsarchitecture name of entity_name is
[constant, variable, signal declaration]…[(sub)type, attribute declaration]…[component declaration]…[subprogram]…
begin{[label :] concurrent_statement}…
end [architecture] [name];
name the statement/component;useful for debugging/simulation
and configuration
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-68
Concurrent statements
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
All concurrent_statements are concurrent and continuously valid: this mimics the behavior of hardware, where all gates operate concurrently
What is the difference in behavior when NAND1 is specified after NAND2?
entity TwoNAND2 isport (A,B,C,D: in std_logic;
Y,Z: out std_logic);end entity TwoNAND2;architecture Struct of TwoNAND2 isbegin
NAND1: entity NAND2 port map (A,B,Y);NAND2: entity NAND2 port map (C,D,Z);
end architecture Struct;
None!
AB
CD
Y
Z
Schematic:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-69
Concurrent statements
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
Does this schematic specify sequential behavior, i.e., is Z updated one moment later than T1?
entity Concurrent isport (A,B,D: in std_logic;
Z: out std_logic);end entity Concurrent;architecture Struct of Concurrent is
signal T1: std_logic;begin
NAND2: entity NAND2 port map (T1,D,Z);NAND1: entity NAND2 port map (A,B,T1);
end architecture Struct;
No!Both gates continuously update their outputs.All (non-delayed) actions take place at the same time.
AB
DZ
T1
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-70
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
Introduction
A first look at VHDL
VHDL language elementsHardware description using VHDL
Behavioral hardware descriptiondescribe the component behaviorStructural hardware descriptionGenerate statements
VHDL hardware simulation
VHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 The process statement:the basic concurrent statement
6-71
= program of sequential statements as a single concurrent statementprocess [is]
[constant, variable, (sub)type declaration]…[subprogram]…
beginsequential_statement(s)
end process [label];
Repeats its sequential_statement(s) endlessly like an infinite loop⇒ at least one wait (sequential) statement
clock_gen: process isvariable val: std_logic := '0';
beginclk <= val;val := not val;wait for T_pw;
end process clock_gen;
must be the same as the label before the statement
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 The process statement:the basic concurrent statement
6-71
= program of sequential statements as a single concurrent statementprocess [is]
[constant, variable, (sub)type declaration]…[subprogram]…
beginsequential_statement(s)
end process [label];
Repeats its sequential_statement(s) endlessly like an infinite loop⇒ at least one wait (sequential) statement
clock_gen: process isvariable val: std_logic := '0';
beginclk <= val;val := not val;wait for T_pw;
end process clock_gen;global constant
local variable
global signal
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-72
Variables versus signals
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
A variable can only be used within a subprogram or a process.A variable is updated immediately;a signal is stored in the signal update queue till the process suspends.
v := '1';if v = '0' then
-- never happensend if;
Variables are used as intermediate values to facilitate the specification of the process; when the value of a variable needs to be accessible outside the process, it should be assigned to a signal.
s <= '1';if s = '0' then
-- s was 0 beforeend if;
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-73
Variables versus signals
Signals usually have a physical meaning, variables don’t necessarily.
process isvariable T1,T2: std_logic;
beginif (S='1') then
T1 := A nand B;T2 := C nand D;
elseT1 := E nand F;T2 := G nand H;
end if;Y <= T1 nand T2;wait on A,B,C,D,E,F,G,H,S;
end process;
T1 and T2 have no physical meaning since each refers to 2 different physical wires.
ABCDEFGH
S
Y
T1 T2
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-74
The wait (sequential) statement
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
= specify when processes respond to signalswait [on signal_name(s)]
[until boolean_expression][for time_expression];sensitivity clause: process resumes when one of the signal_name(s) changescondition clause: process resumes when boolean_expression is true or becomes true when no sensitivity clause is presenttimeout clause: wait (not longer than) a time time_expression
wait; -- wait foreverwait until clk = '1';
= resume when clk becomes 1wait on clk until reset = '0' for 1 ms;
= resume after a simulation time of 1 msor earlier when reset is 0 on a clk change
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-75
Process with sensitivity list
The process statement can take a sensitivity list as parameter:process(signal_name(s)) [is]
[declarations and subprograms]…begin
sequential_statement(s)end process [label];
This is equivalent toprocess [is]
[declarations and subprograms]…begin
sequential_statement(s)wait on signal_name(s);
end process [label];
None of the sequential_statement(s) can be a wait statement!
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-76
Introduction
A first look at VHDL
VHDL language elementsHardware description using VHDL
Behavioral hardware descriptioncombinatorial logicsequential logic
Structural hardware descriptionGenerate statements
VHDL hardware simulation
VHDL hardware synthesis
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-77
Concurrent signal assignments
Shorthand notations for functional modelingConditional signal assignment statementname <= [waveform when boolean_expr else]…
waveform [when boolean_expr];equivalent toprocess(all_signals_except_name)begin
[if boolean_expr then] name <= waveform;[elsif boolean_expr then name <= waveform;]…[else boolean_expr then name <= waveform;][end if;]
end process;y <= d1 when s = '1' else
d0 when s = '0' else'X';
process(d0,d1,s) beginif s = '1' theny <= d1;
elsif s = '0' theny <= d0;
else y <= 'X';end if;
end process;
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-78
Concurrent signal assignments
Selected signal assignment statementwith expression select
name <= [waveform when choice(s) ,]…waveform when choice(s);
equivalent toprocess(all_signals_except_name)begincase expression is
[when choice(s) => name <= waveform;]…when choice(s) => name <= waveform;
end case;end process;
with op selecty <= a+b when addop,
a-b when minop;
process(op,a,b) begincase op iswhen addop =>y <= a+b;
when minop =>y <= a-b;
end case;end process;
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-79
Example: 2-to-1 MUX
Behavioral description
entity MUX21 isport (A,B,S: in bit;
Y: out bit);end entity MUX21;
A
S
BY
• Introduction• First look• Language
elementsHardware description
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StructuralGenerate
• Simulation• Synthesis
The black boxinterface
architecture Behav of MUX21 isbegin
Y <= A when S='1' else B;end architecture Behav;
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Multiple assignmentsto the same signal
6-80
What is the effect of these statements?Y <= A;Y <= B;
Inside a process (sequential)The first one is ignored.
Inside an architecture (concurrent)Invalid code: it gives acompilation error sinceVHDL is a singleassignment language.
Reason: when A='0' and B='1',we have a short circuit
A
BY
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-81
Resolved signals
= include a resolution function in their definition, used tocalculate the final signal valuefrom the values of all of its sources
function resolved (s: std_ulogic_vector)return std_ulogic;
type std_logic is resolved std_ulogic;
For inout ports/arguments,the out usage refers to a resolver input, the in usage to the resolver output.
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
Out2
Out1
In1
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-82
Std_logic_1164 resolution functionconstant resolution_table :array (std_ulogic, std_ulogic) of std_ulogic :=-- 'U','X','0','1','Z','W','L','H','-'(('U','U','U','U','U','U','U','U','U'), -- 'U'('U','X','X','X','X','X','X','X','X'), -- 'X'('U','X','0','X','0','0','0','0','X'), -- '0'('U','X','X','1','1','1','1','1','X'), -- '1'('U','X','0','1','Z','W','L','H','X'), -- 'Z'('U','X','0','1','W','W','W','W','X'), -- 'W'('U','X','0','1','L','W','L','W','X'), -- 'L'('U','X','0','1','H','W','W','H','X'), -- 'H'('U','X','X','X','X','X','X','X','X')); -- '-'
function resolved(s : std_ulogic_vector)return std_ulogic is
variable result : std_ulogic := 'Z'; begin
if s'length = 1 then return s(s'low); end if;for i in s'range loop
result := resolution_table(result, s(i));end loop;return result;
end function resolved;
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-83
Introduction
A first look at VHDL
VHDL language elementsHardware description using VHDL
Behavioral hardware descriptioncombinatorial logicsequential logic
Structural hardware descriptionGenerate statements
VHDL hardware simulation
VHDL hardware synthesis
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-84
Flip-flops in VHDL
VHDL has no dedicated statements for flip-flops!They are inferred when a signal/variable holds its value over a period of time, i.e., in one process sometimes it gets a new value and sometimes not.This typically happens with incomplete if or case statements.
process (D, Clk) isbegin
if (Clk='1') thenQ <= D;
end if;end process;
this is a latch: when Clk is high, Q follows DClk-event & Clk is low, nothing happens.Clk-event & Clk is high, D input copied to Q output.D-event & Clk is high, D input copied to Q output.
Mux: process(D,Clk)begin
if Clk = '1' thenQ <= D;
else Q <= '0';end if;
end process Mux;
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-84
Flip-flops in VHDL
VHDL has no dedicated statements for flip-flops!They are inferred when a signal/variable holds its value over a period of time, i.e., in one process sometimes it gets a new value and sometimes not.This typically happens with incomplete if or case statements.
process (D, Clk) isbegin
if (Clk='1') thenQ <= D;
end if;end process;
this is a latch: when Clk is high, Q follows DClk-event & Clk is low, nothing happens.Clk-event & Clk is high, D input copied to Q output.D-event & Clk is high, D input copied to Q output.
Mux: process(D,Clk)begin
if Clk = '1' thenQ <= D;
else Q <= '0';end if;
end process Mux;
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-85
How to describe a rising clock edge?
Using a wait until statementDFF: process isbeginwait until Clk='1';Q <= D;
end process DFF;
Using the event attributeDFF: process (D,Clk) isbeginif (Clk'event and Clk='1') then
Q <= D;end if;
end process DFF;
rising_edge(clk) as boolean expression is preferred for std_[u]logic to cater for 'H', …
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-86
Flip-flop with reset
Synchronous reset process(D,Clk,Rst)
beginifrising_edge(Clk)thenif Rst='1‘ thenQ <= 0;
elseQ <= D;
end if;end if;
end process;
Can be generalized to combinatorial circuits with registered outputs
Asynchronous reset process(D,Clk,Rst)
beginif Rst = '1' thenQ <= '0';
elsifrising_edge(Clk)thenQ <= D;
end if;end process;
Can not be described using the wait untilstatement
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-87
Finite State Machine
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
UpStart
Nextstatelogic
Output
logic
StateReg
ResetOutput
NextState
CurrentState
Start=0
Wait00
Up101
Up210
Up311
Start=1Up=1
Down311
Down210
Down101
Start=1Up=0
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-88
Finite State Machine
Wait00
Up101
Up210
Up311
Start=1Up=1
entity FSM isport (Start, Up, Reset, Clk: in std_logic;
Output: out std_logic_vector(0 to 1));end entity FSM;
architecture Behav of FSM istype FSM_States = (Wait,Up1,Up2,
Up3,Down1,Down2,Down3);signal CurrentState, NextState :
FSM_States;beginOutputLogic:process(CurrentState) is…
end process OutputLogic;NextStateLogic:process(CurrentState,Start,Up) is…
end process NextStateLogic;StateRegister:process(NextState,Clk,Reset) is…
end process StateRegister;end architecture Behav;
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
Start=0
Down311
Down210
Down101
Start=1Up=0
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-89
Finite State Machine
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
OutputLogic:process(CurrentState) isbegincase CurrentState iswhen Wait =>Output <= "00";
when Up1|Down1 =>Output <= "01";
when Up2|Down2 =>Output <= "10";
when Up3|Down3 =>Output <= "11";
end case;end process OutputLogic;
Start=0
Wait00
Up101
Up210
Up311
Start=1Up=1
Down311
Down210
Down101
Start=1Up=0
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-90
Finite State MachineNextStateLogic:process(CurrentState,Start,Up) isbegincase CurrentState iswhen Wait =>if Start = '0' thenNextState <= Wait;
elsif Up = '1' thenNextState <= Up1;
elseNextState <= Down3;
end if;when Up1 =>NextState <= Up2;
when Up2 =>NextState <= Up3;
when Up3|Down1 =>NextState <= Wait;
when Down3 =>NextState <= Down2;
when Down2 =>NextState <= Down1;
end case;end process NextStateLogic;
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
Start=0
Wait00
Up101
Up210
Up311
Start=1Up=1
Down311
Down210
Down101
Start=1Up=0
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-91
Finite State Machine
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
StateRegister:process(NextState,Clk,Reset) isbeginif Reset='1' thenCurrentState <= Wait;
elsif (Clk'eventand Clk='1') then
CurrentState <= NextState;end if;
end process StateRegister;
Start=0
Wait00
Up101
Up210
Up311
Start=1Up=1
Down311
Down210
Down101
Start=1Up=0
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-92
Safe state machines
Assume a state machine of three states, encoded with 2 bits.What would happen when the state machine enters the 4th state, due to some error (noise, power-up, …)? Will it be able to recover?Make provisions forthis situationin your VHDL code:
NextStateLogic:process(CurrentState) isbegincase CurrentState iswhen Idle =>NextState <= S1;
when S1 =>NextState <= S2;
when S2 =>NextState <= Idle;
when others =>NextState <= Idle;
end case;end process NextStateLogic;
• Introduction• First look• Language
elementsHardware description
Behavioralcombina-torialsequential
StructuralGenerate
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-93
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
Introduction
A first look at VHDL
VHDL language elementsHardware description using VHDL
Behavioral hardware descriptionStructural hardware description:describe the component hierarchy,as interconnected subsystemsGenerate statements
VHDL hardware simulation
VHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-94
Component instantiation statement
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
= specify module (entity/component) usageDirect instantiation (not in VHDL-87)
entity entity_name [(architecture_name)][generic map (generic_association(s))][port map (port_association(s))];Positional or named association possible for the generic constants and the ports(cf. subprograms)entity work.reg(struct)generic map (width => 4);port map (D_in, Q_out, clock);
Implies bottom-up design!⇒ not suitable for large designs
Using component declaration
default T_pd
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-95
Using component declaration
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
Component declaration component name [is]
[generic (generic_list);][port (port_list);]
end component [name];component: virtual device
↔ entity: real deviceallows top-down design
better put it into a package if multiple use
Component instantiation [component] name
[generic map (generic_association(s))][port map (port_association(s))];
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-96
Example: 2-to-1 MUX
architecture Struct of MUX21 issignal U,V,W : bit;component AND2 isport (X,Y: in bit;
Z: out bit);end component AND2;component OR2 isport (X,Y: in bit;
Z: out bit);end component OR2;component INV isport (X: in bit;
Z: out bit);end component INV;
beginGate1: component INV port map (X=>S,Z=>U);Gate2: component AND2 port map (X=>A,Y=>S,Z=>W);Gate3: component AND2 port map (X=>U,Y=>B,Z=>V);Gate4: component OR2 port map (X=>W,Y=>V,Z=>Y);
end architecture Struct;
A
S
BY
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
Structural description
A
S
B
Y
U V
W
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Binding component instancesto design entities
6-97
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
configuration declaration configuration name of entity_name is
for architecture_name[for label(s): component_name
use use_info[generic map (generic_association(s))][port map (port_association(s))];
end for;]…end for;
end [configuration] [name];use_info is one of the following
entity entity_name [(architecture_name)]configuration configuration_name
label(s) is the keyword others or all or a comma separated list of instantiation labels
If no binding is given for a component instance, it is bound to an entity with the same name.Hierarchical designs re-use architecture configuration as binding.
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Binding component instancesto design entities
6-97
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
configuration declaration configuration name of entity_name is
for architecture_name[for label(s): component_name
use use_info[generic map (generic_association(s))][port map (port_association(s))];
end for;]…end for;
end [configuration] [name];use_info is one of the following
entity entity_name [(architecture_name)]configuration configuration_name
label(s) is the keyword others or all or a comma separated list of instantiation labels
If no binding is given for a component instance, it is bound to an entity with the same name.Hierarchical designs re-use architecture configuration as binding.
binding can be different for each instance
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Binding component instancesto design entities
6-97
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
configuration declaration configuration name of entity_name is
for architecture_name[for label(s): component_name
use use_info[generic map (generic_association(s))][port map (port_association(s))];
end for;]…end for;
end [configuration] [name];use_info is one of the following
entity entity_name [(architecture_name)]configuration configuration_name
label(s) is the keyword others or all or a comma separated list of instantiation labels
If no binding is given for a component instance, it is bound to an entity with the same name.Hierarchical designs re-use architecture configuration as binding.
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Binding component instancesto design entities
6-97
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
configuration declaration configuration name of entity_name is
for architecture_name[for label(s): component_name
use use_info[generic map (generic_association(s))][port map (port_association(s))];
end for;]…end for;
end [configuration] [name];use_info is one of the following
entity entity_name [(architecture_name)]configuration configuration_name
label(s) is the keyword others or all or a comma separated list of instantiation labels
If no binding is given for a component instance, it is bound to an entity with the same name.Hierarchical designs re-use architecture configuration as binding.
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-98
Example: 2-to-1 MUX
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
To implement the MUX21, we want to use the implementations for AND3, OR3 and INV gates, available in our design library. An architecture “RTL” is available for these entities.
entity AND3 isport (A,B,C: in bit; Y: out bit);
end entity AND3;
entity OR3 isport (A,B,C: in bit; Y: out bit);
end entity OR3;
entity INV isport (A: in bit; Y: out bit);
end entity INV;
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-99
Example: 2-to-1 MUX
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
Corresponding configuration
configuration Use3InputGates of MUX21 isfor Struct
for Gate1:INV use entity INV(RTL)port map (A=>X,Y=>Z);
end for;for all:AND2 use entity AND3(RTL)
port map (A=>X,B=>Y,C=>'1',Y=>Z);end for;for Gate4:OR2 use entity OR3(RTL)
port map (A=>X,B=>Y,C=>'0',Y=>Z);end for;
end for;end Use3InputGates;
AND3 entityABC
Y
AND2 componentXY
Z
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-100
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
Introduction
A first look at VHDL
VHDL language elementsHardware description using VHDL
Behavioral hardware descriptionStructural hardware descriptionGenerate statements:describe regular iterative structures
VHDL hardware simulation
VHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-101
Generate statement (concurrent)
Generating iterative structures:replicate identical cells
for identifier in range generate[declaration(s)
begin]{[label :] concurrent_statement}…
end generate [this_label];Conditionally generating structures:treat some cells differently
if boolean_expression generate[declaration(s)
begin]{[label :] concurrent_statement}…
end generate [this_label];
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
no begin if no declaration(s)
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Example: 3-stateserial to parallel converter
D Q
Qn
D Q
Qn
D Q
Qn
…serin
clken
parn
6-102
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
library ieee; use ieee.std_logic_1164.all;
entity ser2parinv isgeneric(width: positive);port(clk, en, ser_in: in std_logic;
par_n: out std_logic_vector(1 to width));end entity ser2parinv;
architecture cells of ser2parinv iscomponent DFF is
port(clk, D: in std_logic;Q, Qn: out std_logic);
end component;component tristate is
port(en, A: in std_logic; Y: out std_logic)end component; -- continued on next page
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Example: 3-stateserial to parallel converter
6-103
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
signal state: std_logic_vector(1 to width));begin
cell_array: for index in 1 to width generatesignal prebuf: std_logic;
beginfirst_FF: if index = 1 generate
FF: component DFFport map(clk, ser_in,
state(index), prebuf);end generate first_FF;
other_FF: if index > 1 generateFF: component DFF
port map(clk, state(index-1),state(index), prebuf);
end generate other_FF;buf: component tristate
port map(en, prebuf, par_n(index));end generate cell_array;
end architecture cells;
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-104
Configuration
Instead of architecture_name, use the label of the generate statement, eventually restricted to a subrange: generate_label [(range)]
configuration struct of ser2parinv isfor cells -- architecturefor cell_array(width) -- last FF
for other_FFfor FF:DFF use entity …; end for;
end for;for buf:tristate use entity …; end for;
end for;for cell_array(1 to width-1) -- other cells
for first_FF -- 1st inner generatefor FF:DFF …; end for; end for;
for other_FF -- 2nd inner generatefor FF:DFF …; end for; end for;
for buf:tristate use entity …; end for;end for;
end for;end configuration struct;
• Introduction• First look• Language
elementsHardware description
BehavioralStructuralGenerate
• Simulation• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-105
• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
Introduction
A first look at VHDL
VHDL language elements
Hardware description using VHDL
VHDL hardware simulationEvent-driven simulationVHDL timing informationTest bench
VHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-106
Event-driven simulation
The continuously updating of outputs poses problems to the simulator: even if nothing in the circuit changes, the simulator has to compute continuously the ‘new’ outputs of all gatesSolution: event-driven simulation
A signal assignment schedules a transaction(new value @ new simulation time).When simulation time advances to the new time, the signal is updated (signal active during this delta cycle)An event occurs if the new value differs from the old one.Only concurrent statements with one or more events on their sensitivity list signals are re-evaluated.Keep in mind that this mechanism is only for making simulation fast while maintaining the same behavior as in reality, where all gates work continuously!
• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-107
Simulator implementation
• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
1. Put all statements with at least one changed input in the ‘process execution queue’.
2. Execute all statements in the process execution queue one by one (or concurrently if the simulator is executed on a parallel computer) without updating the output signals (transaction scheduling).
3. After all statements in the process execution queue are processed, update the (active) output signals.
4. Add all statements to the process execution queue that have an event because of the updated output signals.
5. Repeat until the process execution queue is empty.6. Advance system time to the next time where a timed
event is planned.
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-107
Simulator implementation
• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
1. Put all statements with at least one changed input in the ‘process execution queue’.
2. Execute all statements in the process execution queue one by one (or concurrently if the simulator is executed on a parallel computer) without updating the output signals (transaction scheduling).
3. After all statements in the process execution queue are processed, update the (active) output signals.
4. Add all statements to the process execution queue that have an event because of the updated output signals.
5. Repeat until the process execution queue is empty.6. Advance system time to the next time where a timed
event is planned.
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-107
Simulator implementation
• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
1. Put all statements with at least one changed input in the ‘process execution queue’.
2. Execute all statements in the process execution queue one by one (or concurrently if the simulator is executed on a parallel computer) without updating the output signals (transaction scheduling).
3. After all statements in the process execution queue are processed, update the (active) output signals.
4. Add all statements to the process execution queue that have an event because of the updated output signals.
5. Repeat until the process execution queue is empty.6. Advance system time to the next time where a timed
event is planned.
Delta cycle
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-107
Simulator implementation
• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
1. Put all statements with at least one changed input in the ‘process execution queue’.
2. Execute all statements in the process execution queue one by one (or concurrently if the simulator is executed on a parallel computer) without updating the output signals (transaction scheduling).
3. After all statements in the process execution queue are processed, update the (active) output signals.
4. Add all statements to the process execution queue that have an event because of the updated output signals.
5. Repeat until the process execution queue is empty.6. Advance system time to the next time where a timed
event is planned.
Delta cycle convergence
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-108
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
Simulation time: T1
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-108
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
Queue
NAND1A
B
Q
Qn
T1 T2
Simulation time: T1
1. Put statements with input event in PEQ
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-109
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 1
Simulation time: T1
NAND1
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-109
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 1
Simulation time: T1
NAND1
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-109
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 1
Simulation time: T1
RememberedOutputs:
Qn <= 1
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-109
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 1
3. Update outputs
Simulation time: T1
RememberedOutputs:
Qn <= 1
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-109
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 1
3. Update outputs
Simulation time: T1
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-109
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 1
3. Update outputs
4. Add statements with event to PEQ
Simulation time: T1
NAND2
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-110
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 2
Simulation time: T1
NAND2
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-110
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 2
Simulation time: T1
NAND2
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-110
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 2
Simulation time: T1
RememberedOutputs:
Q <= 0
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-110
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 2
3. Update outputs
Simulation time: T1
RememberedOutputs:
Q <= 0
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-110
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 2
3. Update outputs
Simulation time: T1
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-110
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 2
3. Update outputs
4. Add statements with event to PEQ
Simulation time: T1
NAND1
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-111
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 3
Simulation time: T1
NAND1
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-111
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 3
Simulation time: T1
NAND1
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-111
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 3
Simulation time: T1
NAND1
RememberedOutputs:
Qn <= 1
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-111
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 3
3. Update outputs:output does not change
Simulation time: T1
NAND1
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-111
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
A
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
NAND1Delta cycle 3
3. Update outputs:output does not change
4. No statements to add to PEQ:T1 delta cycle convergence
ProcessExecution
QueueSimulation time: T1
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-112
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
6. Advance system time
Simulation time: T2
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-112
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
6. Advance system time
1. Put statements with input event in PEQ
Simulation time: T2
NAND1
NAND2
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-113
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 1
Simulation time: T2
NAND1
NAND2
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-113
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 1
Simulation time: T2
NAND1
NAND2
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-113
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 1
Simulation time: T2
NAND1NAND2
NAND2
RememberedOutputs:Qn <= 1
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-113
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
A
B
Q
Qn
T1 T2
NAND22. Execute statements in PEQ
and remember output
Delta cycle 1
NAND2 computed using old Qn, not new
ProcessExecution
QueueSimulation time: T2
NAND1NAND2
RememberedOutputs:Qn <= 1
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-113
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 1
Simulation time: T2
NAND1NAND2
NAND2
RememberedOutputs:Qn <= 1Q <= 1
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-113
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 1
3. Update outputs
Simulation time: T2
NAND1NAND2
NAND2
RememberedOutputs:Qn <= 1Q <= 1
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-113
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 1
3. Update outputs
Simulation time: T2
NAND1NAND2
NAND2
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-113
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 1
3. Update outputs
4. Add statements with event to PEQ
Simulation time: T2
NAND1NAND2
NAND2
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-113
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 1
3. Update outputs
4. Add statements with event to PEQ
Simulation time: T2
NAND1NAND2NAND1
NAND2
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-114
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 2
Simulation time: T2
NAND1
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-114
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 2
Simulation time: T2
NAND1
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-114
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 2
Simulation time: T2
NAND1
RememberedOutputs:
Qn <= 0
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-114
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 2
3. Update outputs
Simulation time: T2
NAND1
RememberedOutputs:
Qn <= 0
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-114
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 2
3. Update outputs
Simulation time: T2
NAND1
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-114
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 2
3. Update outputs
4. Add statements with event to PEQ
Simulation time: T2
NAND1NAND2
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-115
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 3
Simulation time: T2
NAND2
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-115
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 3
Simulation time: T2
NAND2
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-115
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 3
Simulation time: T2
NAND2
RememberedOutputs:
Q <= 1
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-115
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
2. Execute statements in PEQ and remember output
Delta cycle 3
3. Update outputs:output does not change
Simulation time: T2
NAND2
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-115
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
A
B
Q
Qn
T1 T2
NAND22. Execute statements in PEQ
and remember output
Delta cycle 3
3. Update outputs:output does not change
4. No statements to add to PEQ:T2 delta cycle convergence
ProcessExecution
QueueSimulation time: T2
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-116
Simulation of a SR-FF
entity Flipflop isport (A,B: in std_logic;
Q,Qn: buffer std_logic);end entity Flipflop;
architecture Struct of FlipFlop isbeginNAND2: entity NAND2 port map (Qn,B,Q);NAND1: entity NAND2 port map (A,Q,Qn);
end architecture Struct;
A
BQ
Qn• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis ProcessExecution
QueueA
B
Q
Qn
T1 T2
6. Advance system time
Simulation time: T3
RememberedOutputs:
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-117
Process & delta cycle convergence
process (A,B,M) isbegin
Y <= A;M <= B;Z <= M;
end process;
Old M!
1. Assume event at B with new value Ba.2. The process is executed once sequentially. Following
outputs are remembered: Yb = A, Mb = Ba, Zb = M.3. The process suspends at the implicit wait (i.e., at end
process); Y, M and Z get their new values Yb, Mb, Zb.4. Since M is in the sensitivity list, the process is placed
again in the Process Execution Queue.5. The process is executed: Yc = A, Mc = Ba, Zc = Mb.6. Outputs Y, M and Z get their new values Yc, Mc, Zc.7. No signals of the sensitivity list changed
⇒ delta cycle convergence
• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-118
• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
Introduction
A first look at VHDL
VHDL language elements
Hardware description using VHDL
VHDL hardware simulationEvent-driven simulationVHDL timing informationTest bench
VHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-119
Waveforms
• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
Signals are assigned a waveform:[delay_mechanism] expression [after a_time]
[, expression [after a_time]]…
Transactions are scheduled withwith value = expressionat time = a_time + current simulation time(default a_time = 0 fs)
-- NAND gate with 10 ns prop. delayy <= a nand b after 10 ns;
-- 20 ns wide reset pulse after 5 nsrst <= '1' after 5 ns, '0' after 25 ns;
delay_mechanism applies to the first element only; the other ones have a transport delay (cf. next slide)
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-120
Delay mechanisms
Transport delay mechanismtransport
output is delayed input
Inertial delay mechanism[[reject reject_time] inertial]
device inertia due to capacitance/inductance⇒ pulses shorter than reject_time disappear(default reject_time = a_time)
delay inertial
by default
• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-120
Delay mechanisms
Transport delay mechanismtransport
output is delayed input
Inertial delay mechanism[[reject reject_time] inertial]
device inertia due to capacitance/inductance⇒ pulses shorter than reject_time disappear(default reject_time = a_time)
2 4 6 8 10 ns
a
y
y <= transporta after 3 ns;
• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-120
Delay mechanisms
Transport delay mechanismtransport
output is delayed input
Inertial delay mechanism[[reject reject_time] inertial]
device inertia due to capacitance/inductance⇒ pulses shorter than reject_time disappear(default reject_time = a_time)
2 4 6 8 10 ns
a
y
y <= transporta after 3 ns;
2 4 6 8 10 ns
a
y
y <= a after 3 ns;
• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-121
• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
Introduction
A first look at VHDL
VHDL language elements
Hardware description using VHDL
VHDL hardware simulationEvent-driven simulationVHDL timing informationTest bench
VHDL hardware synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-122
Test bench
How can we verify the circuit that we made?We have to apply representative stimulito the circuit andcheck whether the outputs are correct.
A VHDL ‘test bench’ can be considered to be the top level of a design
It instantiates the Design Under Test (DUT),applies stimuli to it,checks the outputs by
analyzing the outputs, e.g., with assertion or report statements;capturing the outputs for visualization in a waveform viewer.
• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-123
MUX example test bench
entity Testbench isend entity Testbench;
architecture BehavTest of Testbench issignal in1, in2, select, out : bit;
beginDUT: entity MUX21(Behav)
port map (in1, in2, select, out);Stimulus: process is
beginin1 <= '0', '1' after 50 ns,
'0' after 100 ns, '1' after 150 ns;in2 <= '0', '1' after 100 ns;for i in 1 to 4 loop
select <= '0', '1' after 25 ns;wait for 50 ns;
end loop;end process Stimulus;
end architecture BehavTest;
MUX21
A
BY
S
• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
Testbench is self-contained: no ports
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-123
MUX example test bench
entity Testbench isend entity Testbench;
architecture BehavTest of Testbench issignal in1, in2, select, out : bit;
beginDUT: entity MUX21(Behav)
port map (in1, in2, select, out);Stimulus: process is
beginin1 <= '0', '1' after 50 ns,
'0' after 100 ns, '1' after 150 ns;in2 <= '0', '1' after 100 ns;for i in 1 to 4 loop
select <= '0', '1' after 25 ns;wait for 50 ns;
end loop;end process Stimulus;
end architecture BehavTest;
MUX21
A
BY
S
• Introduction• First look• Language
elements• Hardware
descriptionSimulation
Event-drivenTimingTest bench
• Synthesis
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-124
• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
Introduction
A first look at VHDL
VHDL language elements
Hardware description using VHDL
VHDL hardware simulation
VHDL hardware synthesisWriting synthesizable VHDLImproving VHDL synthesisSynthesis issues for Xilinx:trading portability for higher performance
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-125
Synthesizing hardware from VHDL
• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
A synthesis tool (a.k.a. hardware compiler) converts the description into a structural description at a lower level (gates/cells).
Behavioral synthesis (still?) too complex for most synthesis tools.RTL synthesis supported by most tools.
Tools differ in the subsets of VHDL they accept as input.
IEEE 1076.6 standard for VHDL RTL synthesis= lowest common denominator
e.g., in the 1999 version only VHDL-87 is allowed
Timing information is ignored.A waveform can only be an expression;no delay_mechanism nor after part is allowed.The wait for construct is ignored.
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-126
A combinatorial example
• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
With which hardware schematic does following code correspond?
entity Parity isgeneric (width : integer);port (A: in std_logic_vector (0 to width-1);
Odd: out std_logic);end entity Parity;
architecture Struct of Parity isbeginParity: process(A) isvariable Temp: std_logic;
beginTemp := '0';for I in A'low to A'high loopTemp := Temp xor A(I);
end loop;Odd <= Temp;
end process Parity;end architecture Struct;
This is the HW structureas it is given to the synthesis
tool. The synthesis toolwill optimize away the xor
with constant ‘0’ inputand will transform it to
a binary tree of less depth
0A(0)
A(1)
A(2)
Temp
Temp
Odd
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-127
A sequential example
process (clk) isvariable P: std_ulogic;
beginif rising_edge(clk) thenP := A and B;Y <= P or C;
end if;end process;
process (clk) isbeginif rising_edge(clk) thenP <= A and B;Y <= P or C;
end if;end process;
AB YC
P
AB YC
P
• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-128
Allowed data types
• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
Hardware bits:bit, boolean, std_[u]logicGrouped hardware bits:
integer and its subtypestype addr is range -64 to 63;
⇒ 2’s complement, 7 bitsuser-defined enumeration typeencoding is tool dependant, e.g.,
enum_encoding attributeattribute enum_encoding: string;attribute enum_encoding of FSM_states:
type is "000 001 010 100 110";
specifying the encoding for each possible value:constant reset: bit_vector := "000"; …constant output: bit_vector := "110";
1-D array of the above
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-129
Some other restrictions
Allowed std_logic values: '1'/'H', '0'/'L', 'Z''Z' generates a tristate bufferY <= A when Enable else 'Z';
No initial value in signal assignmentFor loops allowed but no while or plain loops:impossible to unfold at synthesis timeSequential circuits
Asynchronous circuits not supportedSynchronous circuits:
edge-triggered:only the two templates discussed beforeinferred (level-sensitive) storage less supported
No other use of wait statements
• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Combinatorial circuits with registered outputs
6-130
AB
CD
Z
‘Wait until’ has to be the first line of the process,
followed by the description of the combinatorial circuit
1. Using wait until statement
entity RegisteredCircuit isport (A,B,C,D: in std_logic;
Clk: in std_logic;Z: out std_logic);
end entity RegisteredCircuit;
architecture RTL of RegisteredCircuit isbegin
process isbegin
wait until Clk='1';-- combinatorial circuitZ <= (A and B) or (C and D);
end process;end architecture RTL;
• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Combinatorial circuits with registered outputs
6-131
AB
CD
Z
2. Using the event attribute
entity RegisteredCircuit isport (A,B,C,D: in std_logic;
Clk,Rst: in std_logic;Z: out std_logic);
end entity RegisteredCircuit;
architecture RTL of RegisteredCircuit isbegin
process (A,B,C,D,Clk,Rst) isbegin
if Rst = '1' thenZ <= '0';
elsif (Clk'event and Clk='1') then-- combinatorial circuitZ <= (A and B) or (C and D);
end if;end process;
end architecture RTL;
The if statement is the only statement of the process.
It has no else part.
The ‘Clk'event’ condition is always
the last one.
• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-132
• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
Introduction
A first look at VHDL
VHDL language elements
Hardware description using VHDL
VHDL hardware simulation
VHDL hardware synthesisWriting synthesizable VHDLImproving VHDL synthesisSynthesis issues for Xilinx:trading portability for higher performance
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-133
Improving VHDL synthesis
• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
Rewriting your code can improve the synthesized result
Any real tool can only try to understand what your code means, so it is not aware of all possible implementations.
Which state encoding is optimal?Did you really want a latch or will a FF also be OK?
A tool can’t take all real constraints into account, e.g., area, fan-out, timing (delay can only be estimated), …You made the wrong assumptions about the available hardware, e.g., using an asynchronous set when none of the available FFs has one.
The VHDL coding style and the synthesis tool capabilities determine the circuit that is eventually synthesized.
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-134
Conditional assignments
• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
A conditional assignment of if statement has a built-in priority
Y <= C when Sel[1]='1' elseB when Sel[0]='1' elseA;
A selected assignment or case statement often gives more simple hardware
with Sel selectY <= A when "00",
B when "01",C when others;
01
AB
C
Sel
01 Y
Y
00011011
AB
C
Sel
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-135
Resource sharing
Original code:if Sel = '1' then
Z <= A + B;else
Z <= A + C;end if;
Some tools can transform this (often only within the scope of a process) toif Sel = '1' then
X := B;else
X := C;end if;Z <= A + X;
Otherwise, you must rewrite the code yourself.
+ +
MUX
A B CA
Sel
Z
• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-135
Resource sharing
Original code:if Sel = '1' then
Z <= A + B;else
Z <= A + C;end if;
Some tools can transform this (often only within the scope of a process) toif Sel = '1' then
X := B;else
X := C;end if;Z <= A + X;
Otherwise, you must rewrite the code yourself.
+ +
MUX
A B CA
Sel
Z
+
MUX
B C A
Z
Sel
• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J03 Language based HW design:a VHDL primer
6-136
• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
Introduction
A first look at VHDL
VHDL language elements
Hardware description using VHDL
VHDL hardware simulation
VHDL hardware synthesisWriting synthesizable VHDLImproving VHDL synthesisSynthesis issues for Xilinx:trading portability for higher performance
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-137
Some Xilinx specific issues
When using VHDL, synthesis isan additional design step.Constraints can be specifiedor fixed ones are known:
It synthesizes automatically clock buffers (⇐ fan-out).The default encoding isone-hot since this matchesthe structure of a CLB(a little bit of combinatoriallogic in front of a D-FF).
Encoding can also be specified in VHDL using the enum_encoding attribute.
Some additionally known components:LogiBLOX modulesI/O buffer, eventually with pull-up/pull-down resistorGlobal Reset module
• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-138
Using LogiBLOX in VHDL
LogiBLOX high-level customizable modules(e.g., ALU, MUX, counters, RAM, …) lead to highly efficient FPGA implementations.
The LogiBLOX module generator creates, apart from the FPGA implementation, also a behavioral level VHDL module for simulation.
Always use LogiBLOX for RAM, because RAM would otherwise be created out of separateflip-flops.
Using LogiBLOX modules makes your VHDL implementation more efficient on Xilinx FPGA but less portable to other devices!
• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-139
Pull-up resistor example
entity Pullup_in isport (In_pad: in std_logic;
Core_in: out std_logic);end entity Pullup_in;
architecture RTL of Pullup_in iscomponent PULLUP
port (o: out std_logic);end component PULLUP;component IBUF
port (I: in std_logic;O: out std_logic);
end component IBUF;signal Dummy: std_logic;
beginDummy <= In_pad;component PULLUP port map (Dummy);component IBUF port map (Dummy, Core_in);
end architecture RTL;
Core_inIn_pad
Vcc• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
For simulation purposes, it works likeo <= 'H';
VHDL
KATHOLIEKE UNIVERSITEIT
03–04H0J036-140
Using the Global Set Reset block
entity OneHot isport (Rst, Clk: in std_logic;
Q: out std_logic_vector (0 to 3));end entity OneHot;
architecture Behav of OneHot iscomponent STARTUP
port (GSR: in std_logic);end component STARTUP;
begincomponent STARTUP port map (Rst);process (Clk, Rst) isbeginif Rst = '1' then
Q <= "0001";elsif Clk'event and Clk = '1' then
Q <= Q(1 to 3) & Q(0);end if;
end process;end architecture RTL;
• Introduction• First look• Language
elements• Hardware
description• Simulation
SynthesisSynthesizableImprovingXilinx
this makes all FF use Rst as reset
the reset value