Unit 2 Combinational Circuits. Introduction Logic circuits for digital systems may be either...

Unit 2Combinational Circuits

Introduction

Logic circuits for digital systems may be eithercombinational or sequential.

A combinational circuit consists of logic gates whoseoutputspresent

at any time are determined from only thecombination of inputs.

Combinational Circuits

A combinational circuits

2 possible combinations

nof input values

n inputvariables

m outputvariables

Specific functions Adders, subtractors, multiplexers

comparators, decoders, encoders, and

MSI circuits or standard cells

CombinationalLogic Circuit

Analysis Procedure

Step 1: Label all gate outputs that are a function ofinput variables with arbitrary symbols – but with meaningful names. Determine the Boolean functions for each gate output.

Step 2: Label the gates that are a function of input variables and previously labeled gates with other arbitrary symbols. Find the Boolean functions for these gates.

Step 3: Repeat the process outlined in step 2 untiloutputs of the circuit are obtained.

Step 4: By repeated substitution of previously definedfunctions, obtain the output Boolean functions in terms of input variables.

Analysis Procedure Example

A straight-forward procedure

Analysis Procedure Example

Step 1: F2

= AB+AC+BC= A+B+C

2: T3 = F2'T1

Step 3: F1 = T3+T2

Step 4: F1 = T3+T2 = F2'T1+ABC

(AB+AC+BC)'(A+B+C)+ABC(A'+B')(A'+C')(B'+C')(A+B+C)+ABC(A'+B'C')(AB'+AC'+BC'+B'C)+ABC A'BC'+A'B'C+AB'C'+ABC

Truth Table

Design Procedure

The design procedure of combinational circuitsStep 1: State the problem (system spec.)

Step 2: From the specifications of the circuits, determine the required number of inputs and outputs and assign a symbol to each.Step 3: Derive the truth table that defined therequired relationship between inputs and outputs

Step 4: Obtain the simplified Boolean functions for each output as a function of the input variables.

Step 5: Draw the logic diagram and verifycorrectness of the design (manually or by

thesimulation).

Design Method and Constraint

Functional description Boolean function HDL (Hardware description Verilog HDL VHDL

Schematic entry

Logic constraint number of gates number of inputs to a gate propagation delay number of interconnections

language)

limitations of the driving capabilities

BCD to Excess-3 Code Conversion

Simplified functions

D'CD +C'D'B'C + B'D+BC'D'

w = A+BC+BD

Efficient implementation z

D'CD +C'D'= CD + (C+D)‘B'C + B'D+BC'D‘ = B'(C+D) +B(C+D)'A+BC+BD= A+ B(C+D)

Logic Diagram for BCD toExcess-3 Code Converter

1-Bit Half Adder

Half adder 0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1 + 1 =

two input variables: x, y(10)2

two output variables: C (carry), S (sum)

truth table

S = x'y+xy'=xy=C = xy= (x'+y')' S' = xy+x'y'S = (C+x'y')'

(x+y)(x'+y')

Logic Diagram of 1-BitHalf Adder

Lan-Da Van DCD-

1-Bit Full AdderFull-Adder

The arithmetic sum of threeinput bits

three input bits x, y: two significant bits

z: the carry bit from theprevious lower significant bit

Two output bits: C, S

Logic Diagram of 1-BitFull Adder

S = x'y'z+x'yz'+ xy'z'+xyz= x’(yz) +x(yz)’ = xyz

C = xy + xz + yz= xy + xyz + xy’z + xyz + x’yz= xy + z (xy + xy)

= xy + z (xy)

4-Bit Full Adder

Binary adder

Subtractors

• Half Subtractor

• Full Subtractor

• Adder/Subtractor - 1

• Adder/Subtractor - 2

Half Subtractor

C A B D 0 0 0 1

0 0 0 00 1 1 11 0 1 01 1 0 0

A 0 B 0

Full Subtractor

0 0 0 0 00 0 1 1 10 1 0 1 00 1 1 0 01 0 0 1 11 0 1 0 11 1 0 0 01 1 1 1 1

Ci Ai Bi Di Ci+1

00 01 11 10

Di = Ci $ (Ai $ Bi)

Same as Si in full adder

Full Subtractor

0 0 0 0 00 0 1 1 10 1 0 1 00 1 1 0 01 0 0 1 11 0 1 0 11 1 0 0 01 1 1 1 1

Ci Ai Bi Di Ci+1 Ci

00 01 11 10

Ci+1 = !Ai & Bi

# Ci & !Ai & !Bi

# Ci & Ai & Bi

Full SubtractorCi+1 = !Ai & Bi

# Ci & !Ai & !Bi

# Ci & Ai & Bi

Ci+1 = !Ai & Bi

# Ci & (!Ai & !Bi # Ai & Bi)

Ci+1 = !Ai & Bi # Ci & !(Ai $ Bi)

Recall:Di = Ci $ (Ai $ Bi)

Ci+1 = !Ai & Bi # Ci & !(Ai $ Bi)

Full Subtractor

Di = Ci $ (Ai $ Bi)

Ci+1 = !Ai & Bi # Ci & !(Ai $ Bi)

half subtractorhalf subtractor

Carry Lookahead Adder (1/7)

Given Stage i from a Full Adder, weknow that there will be a carry generated when Ai = Bi = "1", whether or not there is a carry-in.

Alternately, therepropagated if theand a carry-in, Ci

These two signal

will be a carry“half-sum” is "1"occurs.

iconditions areGi, and

Cicalled generate, denoted aspropagate, denoted as Pi

respectively and are identified in thecircuit.

Ci+1 Si

In the ripple carry adder:

Gi, Pi, and Si are local function to each cell of the

adder Ci is also local function for each cell

In the carry lookahead adder, in order to reduce the length of the carry chain, Ci is changed to a more global function spanning multiple cells

Defining the equationsthe Pi and Gi:

for the Full Adder in term of

Ai Bi G iC

Ai BiPi C i G i Pi C i

Ci+1 can be removed from the cells and used toderive a set of carry equations spanning multipleBeginning at the cell 0 with carry in C0:

cells.

======

++++++

P1 C1 = G1 + P1(G0 + P0 C0)P1G0 + P1P0 C0

C3 P2 C2 = G2 + P2(G1 + P1G0 + P1P0 C0)P2G1 + P2P1G0 + P2P1P0 C0

C4 P3 C3 = G3 + P3G2 + P3P2G1++ P3P2P1P0 C0

P3P2P1G0

CLA GEN

This lookahead scheme could be extended to more thanfour bits; in practice, due to limited gate fan-in, such extension is not feasible.Instead, the concept is extended another level by considering group generate (G0-3) and group propagate (P0-3) functions:

G 0 3 G 3 P3 G 2 P3 P2 G1 P3 P2 P1G 0Using these two equations:

C4 = G3 + P3 C3 = G3 + P3G2 + P3P2G1+ P3P2P1G0

+ P3P2P1P0 C0P03 P3 P2 P1 P0

C 4 G 0 3 P03 C 0

Thus, it isgenerator

possiblecircuit to

to have five 4-bit carry lookaheadspeed up 16-bit addition (see next

slide).

16-bit 2-level Carry Lookahead Adder

c9 c3c11 c8 c4

G14P14 G10P10

G PG13P13G15P15

c12 c4 c0c8

G12-15 P12-15 G4-7 G0-3G8-11 P4-7 P0-3P8-11

G0-15 P0-15

CLA GEN

G6P6G5P5

CLA GEN

11 11 G9P9

CLA GEN

G12P12

CLA GEN

4-Bit Adder/Subtractor

A-B = A+(2’s complement4-bit adder-subtractor

M=0, A+B; M=1, A+B’+1

Overflow Discussion

Overflow The storage is limited.

Add two positive numbers and obtain a negative numbernumber Add two negative numbers and obtain a positive

V = 0, no overflow; V = 1, overflow

Example:

BCD AdderAdd two decimal digits in BCD together with ana previous stage 9 inputs: two BCD's and one carry-in

5 outputs: one BCD and one carry-out

Design approaches

input carry from

Since each input digit does not exceed 9, the output sumgrater than 9+9+1 =19, where 1 denotes an input carry.

A truth table with 19 entries

Use two 4-bit binary full adders

cannot be

Modifications are needed C = 1 K = 1

if the binary sum > 9

Z8Z4 = 1 Z8Z2 = 1

modification: +6

8 4 8 2C = K +Z Z + Z Z

Truth Table of BCD Adder

Logic Diagram of BCD AdderBCD

BCD Output

Binary Multiplier

4-Bit by 3-Bit Binary Multiplier

Magnitude ComparatorThe comparison of two numbers outputs: A>B, A=B, A<B

Design Approaches the truth table 2 entries - too cumbersome for large n

use inherent regularity of the problem reduce design efforts reduce human errors

Algorithm -> logic A = A3A2A1A0 ; B = B3B2B1B0

A=B if A3=B3, A2=B2, A1=B1and A0=B0

equality: xi= AiBi+Ai'Bi'

(A=B) = x3x2x1x0

(A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'

(A<B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0

Implementation xi = (AiBi'+Ai'Bi)'

Four-Bit Magnitude Comparator

DecoderAn n-to-m decoder

n a binary code of n bits = 2 distinct information n input variables; up to 2 output linesn

only one output can be active (high) at any time

Three-to-Eight Line Decoder

x’y’z’

Decoder with Enable/Demultiplexer

Demultiplexers a decoder with an enable input

receive information on a single line and transmits it on one ofn

2 possible output lines

Two-to-four-line decoder

with enable input

Decoder with Enable/Demultiplexer

4x16 Decoder

Expansion two 3-to-8 decoder: a 4-to-16 decoder

4 16 decoderconstructed with3 8 decoders

Combinational LogicImplementation

Each output = a mintermUse a decoder and an external OR gate to implement anyBoolean function ofA full-adder

S(x,y,x)=(1,2,4,7)

C(x,y,z)= (3,5,6,7)

n input variables

Encoder

with three

OR gates.

The encoder can be implemented

z D1 D3 D5 D7

y D2 D3 D6 D7

x D4 D5 D6 D7

Encoder

An implementation

x=D4+D5+D6+D

y=D2+D3+D6+D

z=D1+D3+D5+D

limitations illegal input: e.g. D3=D6=1 the output = 111 (¹3 and ¹6)

Priority Encoder Resolve the ambiguity of illegal inputs Only one of the input is encoded

D3 has the highest prioritythe lowest priority D0 has

X: don't-care conditions V: valid output indicator

Priority Encoder

x D2 D3

y D3 D1D2

V D0 D1 D2 D3

Multiplexer

Select binary information from one of many inputlines and direct it to a single output line

n2 input lines, n selection lines and one output line

E.g.: 2-to-1-line multiplexer

Two-to-one-line

multiplexer

4-to-1-Line Multiplexer

Boolean Function Implementation Using MUX

MUX: a decoder + an OR gate2 -to-1 MUX can implement any Boolean function of ninput variable.

Procedure: assign an ordering sequence of the input variable

the rightmost variable (D) will be used for the input lines

assign the remaining n-1 variables to the selection lines w.r.t.their corresponding sequence

construct the truth table

consider a pair of consecutive determine the input lines

minterms starting from m0

Example: Given F(x,y,z) = (1,2,6,7)

Example: Given F(A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)

Three-State Gate

A multiplexergates.

can be constructed with three-state

Output state: 0, 1, and high-impedance (open ckts)

Four-to-One-Line Multiplexer

Conclusion

Adder/Subtractor

Multiplier

Decoder

Encoder

Multiplexer

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