Types of BJT Biasing Circuits

ByG.KavithaECE Dept

Paavai Engineering College

Biasing Circuits of the BJT

• Normally, three types of circuits are used to establish dc biasing in a BJT, these are;

(a) Fixed bias circuit(b) Collector-to-Base Bias Circuit(c) Voltage-Divider with Self-Bias Circuit (or) Self-Bias (or) Emitter Bias (or) Emitter-Stabilized Bias Circuit

While designing the all four types of biasing circuits of BJT it is aimed to obtain Q-point parameters (IBQ, ICQ, VCEQ)

Fixed Bias

The Base-Emitter LoopThe Base-Emitter Loop

• From Kirchhoff’s voltage law:

+VCC – IBRB – VBE = 0

• Solving for base current:

B

BECCB R

VVI

Collector-Emitter LoopCollector-Emitter Loop

Collector current:

BIIC

From Kirchhoff’s voltage law:

CCCCCE RIVV

SaturationSaturation

When the transistor is operating in saturation, current through the transistor is at its maximum possible value.

CRCCV

CsatI

V 0CEV

Load Line AnalysisLoad Line Analysis

IICsatCsat

ICC = VCCCC / RCC

VCECE = 0 V

VVCEcutoffCEcutoff

VCECE = VCCCC

ICC = 0 mA

• where the value of RBB sets the value of IBB

• that sets the values of VCECE and ICC

The Q-point is the operating point:

The end points of the load line are:

Collector to Base Bias

Base-Emitter LoopBase-Emitter Loop

)(RR

VVI

CB

BECCB

From Kirchhoff’s voltage law:From Kirchhoff’s voltage law:

0V–RI–RI– V BEBBCCCC

Where IWhere IBB << I << ICC::

CI

BI

CI

CI'

Knowing IKnowing ICC = = IIBB and I and IEE I ICC, the loop , the loop

equation becomes: equation becomes:

0– VCC BEBBCB VRIRI

Solving for ISolving for IBB::

Collector-Emitter LoopCollector-Emitter Loop

From Kirchhoff’s voltage law:

Since ISince ICC I ICC and I and ICC = = IIBB::

0 V-RI V CCCCCE Solving for VSolving for VCECE::

CCCCCE RI - V V

0V–RI V CCCCCE

Voltage Divider Bias (or) Self Bias

Approximate AnalysisApproximate Analysis

Where IB << I1 and I1 I2 :

Where RE > 10R2:

From Kirchhoff’s voltage law:

21

CC2B RR

VRV

E

EE R

VI

BEBE VVV

EECCCCCE RI RI V V

)R (RIV V

II

ECCCCCE

CE

Voltage Divider Bias AnalysisVoltage Divider Bias Analysis

Transistor Saturation LevelTransistor Saturation Level

EC

CCCmaxCsat RR

VII

Load Line AnalysisLoad Line Analysis

Cutoff:Cutoff: Saturation:Saturation:

mA0I

VV

C

CCCE

V0VCE

ERCRCCV

CI

Emitter-Stabilized Bias Circuit

Base-Emitter LoopBase-Emitter Loop

From Kirchhoff’s voltage law:

0R1)I(-RI-V EBBBCC

0 RI-V-RI-V EEBEEECC

EB

BECCB 1)R(R

V-VI

Since IE = ( + 1)IB:

Solving for IB:

Collector-Emitter LoopCollector-Emitter Loop

From Kirchhoff’s voltage law:

0 CC

VC

RC

I CE

V E

RE

I

Since IE IC:

)R (RI– V V ECCCCCE

Also:

EBEBRCCB

CCCCECEC

EEE

V V RI– V V

RI - V V V V

RI V

Improved Biased StabilityImproved Biased Stability

Stability refers to a circuit condition in which the currents and voltages will remain fairly constant over a wide range of temperatures and transistor Beta () values.

Adding RE to the emitter improves the stability of a transistor.

Saturation LevelSaturation Level

VCEcutoff:: ICsat:

The endpoints can be determined from the load line.

mA 0 I

V V

C

CCCE

ERCR

CCVCI

CE V 0V

Emitter-Stabilized Bias Circuit

Base-Emitter LoopBase-Emitter Loop

)R(RR

VVI

ECB

BECCB

From Kirchhoff’s voltage law:From Kirchhoff’s voltage law:

0RI–V–RI–RI– V EEBEBBCCCC

Where IWhere IBB << I << ICC::

CI

BI

CI

CI'

Knowing IKnowing ICC = = IIBB and I and IEE I ICC, the loop , the loop

equation becomes: equation becomes:

0RIVRIRI– V EBBEBBCBCC

Solving for ISolving for IBB::

Collector-Emitter LoopCollector-Emitter Loop

From Kirchhoff’s voltage law:

Since ISince ICC I ICC and I and ICC = = IIBB::

0 V-)R(RI V CCECCCE Solving for VSolving for VCECE::

)R(RI - V V ECCCCCE

0V–RI VRI CCCCCEEE

Base-Emitter Bias AnalysisBase-Emitter Bias Analysis

Transistor Saturation LevelTransistor Saturation Level

EC

CCCmaxCsat RR

VII

Load Line AnalysisLoad Line Analysis

Cutoff:Cutoff: Saturation:Saturation:

mA 0I

VV

C

CCCE

V 0VCE

ER

CR

CCV

CI